LM26001_0609 NSC | Alldatasheet
Document overview
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Technical content
Features
n High efficiency sleep mode n 40 µA typical Iq in sleep mode n 10 µA typical Iq in shutdown mode n 3.0V minimum input voltage n 4.0V to 38V continuous input range n 1.5% reference accuracy n Cycle-by-cycle current limit n Adjustable Frequency (150 kHz to 500 kHz) n Synchronizable to an external clock n Power Good Flag n Forced PWM function n Adjustable Soft-start n TSSOP-16 exposed pad package n Thermal Shut Down
Applications
n Battery Powered Applications n Stand-by power for home gateways/set-top boxes Typical Application Circuit 20179401 September 2006 LM26001 1.5A Switching Regulator with High Efficiency Sleep Mode © 2006 National Semiconductor Corporation DS201794 www.national.com
Ordering Information
Order Number Package Type Package Drawing Package Marking Supplied As LM26001MXA TSSOP-16EXP MXA16A LM26001EM 92 Units of Rail LM26001MXAX TSSOP-16EXP MXA16A LM26001EM 2500 Units of Tape and Reel Pin Descriptions Pin # Pin Name Description
1 VIN Power supply input
2 VIN Power supply input
3 PGOOD Power Good pin. An open drain output which goes high when the output voltage is greater than 92% of nominal. 4 EN Enable is an analog level input pin. When pulled below 0.8V, the device enters shutdown mode. 5 SS Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time. 6 COMP Compensation pin. Connect to a resistor capacitor pair to compensate the control loop. 7 FB Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage.
8 GND Ground
9 FREQ Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency. 10 FPWM FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled. 11 SYNC Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation.
12 VBIAS Connect to an external 3V or greater supply to bypass the internal regulator for improved
efficiency. If not used, VBIAS should be tied to GND. 13 VDD The output of the internal regulator. Bypass with a minimum 1.0 µF capacitor. 14 BOOT Bootstrap capacitor pin. Connect a 0.1µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage. 15 SW Switch pin. The source of the internal N-channel switch. 16 SW Switch pin. The source of the internal N-channel switch. EP EP Exposed Pad thermal connection. Connect to GND. LM26001 www.national.com 2
Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltages from the indicated pins to GND: VIN -0.3V to 40V SW (Note 7) -0.5V to 40V VDD -0.3V to 7V VBIAS -0.3V to 10V FB -0.3V to 6V BOOT SW-0.3V to SW+7V PGOOD -0.3V to 7V FREQ -0.3V to 7V SYNC -0.3V to 7V EN -0.3V to 40V FPWM -0.3V to 7V SS -0.3V to 7V Storage Temperature -65˚C to +150˚C Power Dissipation (Note 2) 2.6 W Recommended Lead Temperature Vapor Phase (70s) 215˚C Infrared (15s) 220˚C ESD Susceptibility (Note 3) Machine Model 200V Human Body Model 2KV Charged Device Model 1kV Operating Ratings (Note 1) Operating Junction Temp. −40˚C to 125˚C Supply Voltage (Note 4) 3.0V to 38V Electrical Characteristics Specifications in standard type are for TJ = 25˚C only, and limits in boldface type apply over the junction temperature (TJ) range of -40˚C to +125˚C. Unless otherwise stated, Vin=12V. Minimum and Maxi- mum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T J = 25˚C, and are provided for reference purposes only. (Note 5) Symbol Parameter Conditions Min Typ Max Unit System I SD (Note 6) Shutdown Current EN = 0V 9.5 20 µA Iq_Sleep_VB (Note Quiescent Current Sleep mode, VBIAS = 5V 38 70 µA Iq_Sleep_VDD Quiescent Current Sleep mode, VBIAS = GND 83 150 µA Iq_PWM_VB Quiescent Current PWM mode, VBIAS = 5V 150 230 µA Iq_PWM_VDD Quiescent Current PWM mode, VBIAS = GND 0.65 0.85 mA IBIAS_Sleep (Note 6) Bias Current Sleep mode, VBIAS = 5V 43 105 µA IBIAS_PWM Bias Current PWM mode, VBIAS = 5V 0.5 0.70 mA VFB Feedback Voltage 5V < Vin < 38V 1.2155 1.234 1.2525 V IFB FB Bias Current ±200 nA ∆VOUT/∆VIN Vout line regulation 5V < Vin <38V 0.001 %/V ∆VOUT/∆IOUT Vout load regulation 0.8 < VCOMP < 1.15V 0.07 % VDD VDD output voltage 7 < Vin < 35V, IVDD=0m At o 5m A 5.50 5.95 6.50 V ISS_Source Soft-start source current 0.9 2.3 3.6 µA Vbias_th VBIAS switchover threshold 2.50 2.7 3.05 V Switching R DS(ON) Switch on Resistance Isw = 1A 0.12 0.2 0.42 Ω Isw_off Switch off state leakage current Vin = 38V, VSW = 0V 0.002 5.0 µA fsw Switching Frequency RFREQ = 62k, 124k, 240k ±10 % VFREQ FREQ voltage 1.0 V fSW range Switching Frequency range 150 500 kHz VSYNC Sync pin threshold SYNC rising 1.2 1.6 V SYNC falling 0.8 1.1 Sync pin hysteresis 114 mV ISYNC SYNC leakage current 6 nA FSYNC_UP Upper frequency synchronization range As compared to nominal fSW +30 % FSYNC_DN Lower frequency synchronization range As compared to nominal fSW -20 % LM26001 www.national.com3
Electrical CharacteristicsSpecifications in standard type are for TJ = 25˚C only, and limits in boldface type apply over the junction temperature (TJ) range of -40˚C to +125˚C. Unless otherwise stated, Vin=12V. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T J = 25˚C, and are provided for reference purposes only. (Note 5) (Continued) Symbol Parameter Conditions Min Typ Max Unit TOFFMIN Minimum Off-time 365 ns TONMIN Minimum On-time 155 ns THSLEEP_HYS Sleep mode threshold hysteresis VFB rising, % of TH WAKE 101.2 % THWAKE Wake up threshold Measured at falling FB, COMP = 0.6V 1.234 V IBOOT BOOT pin leakage current BOOT = 16V, SW = 10V 0.0006 5.0 µA Protection I LIMPK Peak Current Limit 1.85 2.5 3.2 A VFB_SC Short circuit frequency foldback threshold Measured at FB falling 0.87 V F_min_sc Min Frequency in foldback VFB < 0.3V 71 kHz VTH_PGOOD Power Good Threshold Measured at FB, PGOOD rising 89 92 95 % PGOOD hysteresis 2 7 8 % IPGOOD_HI PGOOD leakage current PGOOD = 5V 0.2 nA RDS_PGOOD PGOOD on resistance PGOOD sink current = 500 µA 64 Ω VUVLO Under-voltage Lock-Out Threshold Vin falling , shutdown, VDD = VIN 2.60 2.9 3.20 V Vin rising, soft-start, VDD = VIN 3.60 3.9 4.20 TSD Thermal Shutdown Threshold 160 ˚C θ JA Thermal resistance Power dissipation = 1W, 0 lfpm air flow 38 ˚C/W Logic VthEN Enable Threshold voltage 0.8 1.1 1.4 V Enable hysteresis 164 mV IEN_Source EN source current EN = 0V 4.5 µA VTH_FPWM FPWM threshold 0.8 1.2 1.6 V IFPWM FPWM leakage current FPWM = 5V 66 nA EA gm Error amp trans-conductance 400 670 1000 µmho I COMP COMP source current VCOMP = 0.9V 56 µA COMP sink current VCOMP = 0.9V 39 µA V COMP COMP pin voltage range 0.64 1.27 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the ElectricalCharacteristics. Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance,θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX =( TJ_MAX -T A)/ θJA. The maximum power dissipation of 2.6W is determined using TA = 25˚C,θJA = 38˚C/W, and TJ_MAX = 125˚C. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. The charged device model is per JESD22-C101-C. Note 4: Below 4.0V input, power dissipation may increase due to increased RDS(ON). Therefore, a minimum input voltage of 4.0V is required to operate continuously within specification. A minimum of 3.9V (typical) is also required for startup. Note 5: All room temperature limits are 100% production tested. All limits at temperature extremes are guaranteed through correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 6: Iq and ISD specify the current into the VIN pin. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3V. All quiescent current specifications apply to non-switching operation. Note 7: The absolute maximum specification applies to DC voltage. An extended negative voltage limit of -2V applies for a pulse of up to 1µs, and -1V for a pulse of up to 20µs. LM26001 www.national.com 4
Typical Performance Characteristics Unless otherwise specified the following conditions apply: Vin = 12V, TJ = 25˚C. VFB vs Temperature VFB vs Vin (IDC = 300 mA) 20179403 20179405 IQ and IVBIAS vs Temperature (Sleep Mode) IQ and IVBIAS vs Temperature (PWM Mode) 20179404 20179406 Normalized Switching Frequency vs Temperature (300kHz) UVLO Threshold vs Temperature (VDD = VIN) 20179416 20179417 LM26001 www.national.com5
Typical Performance CharacteristicsUnless otherwise specified the following conditions apply: Vin = 12V, TJ = 25˚C. (Continued) Peak Current Limit vs Temperature Short Circuit Foldback Frequency vs VFB (325 kHz nominal) 20179415 20179412 Efficiency vs Load Current (330kHz) Efficiency vs Load Current (500kHz) 20179408 20179409 Startup Waveforms Load Transient Response 20179410 20179452 LM26001 www.national.com 6
Typical Performance CharacteristicsUnless otherwise specified the following conditions apply: Vin = 12V, TJ = 25˚C. (Continued) Low Input Voltage Dropout Nominal VOUT = 5V 20179453 LM26001 www.national.com7
PWM waveforms are shown in Figure 1. FIGURE 1. PWM Waveforms
minimum 1µF ceramic capacitor placed directly at the pin. duty cycle corresponds to a reduction in output voltage. current can rise very high during the minimum on-time. back mode is 71 kHz typical. input. When SYNC goes low, the high-side switch turns on. when synchronizing to a frequency higher than nominal. FIGURE 5. Swtiching Frequency vs RFREQ
Where Vfb = 1.234V typically. reduces the effective current limit. threshold as shown in Figure 3. lowered, which increases the current limit margin. equivalent series resistance, or ESR. ESR values result in lower output ripple. FIGURE 7. Example Circuit
Design Information (Continued) Re can also be calculated from the following equation: Where ∆Vt is the allowed voltage excursion during a load transient, and ∆It is the maximum expected load transient. If the total ESR is too high, the load transient requirement cannot be met, no matter how large the output capacitance. If the ESR criteria for ripple voltage and transient excursion cannot be met, more capacitors should be used in parallel. For non-ceramic capacitors, the minimum output capaci- tance is of secondary importance, and is determined only by the load transient requirement. If there is not enough capacitance, the output voltage excur- sion will exceed the maximum allowed value even if the maximum ESR requirement is met. The minimum capaci- tance is calculated as follows: It is assumed the total ESR, Re, is no greater than ReMAX. Also, it is assumed that L has already been selected. Generally speaking, the output capacitance requirement de- creases with Re,∆It, and L. A typical value greater than 100 µF works well for most applications. INPUT CAPACITOR In a switching converter, very fast switching pulse currents are drawn from the input rail. Therefore, input capacitors are required to reduce noise, EMI, and ripple at the input to the LM26001. Capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient tem- perature as well as the maximum input voltage. The equa- tion for calculating the RMS input ripple current is shown below: For noise suppression, a ceramic capacitor in the range of 1.0 µF to 10 µF should be placed as close as possible to the VIN pin. A larger, high ESR input capacitor should also be used. This capacitor is recommended for damping input voltage spikes during power on and for holding up the input voltage during transients. In low input voltage applications, line transients may fall below the UVLO threshold if there is not enough input capacitance. Both tantalum and electrolytic type ca- pacitors are suitable for the bulk capacitor. However, large tantalums may not be available for high input voltages and their working voltage must be derated by at least 2X. BOOTSTRAP The drive voltage for the internal switch is supplied via the BOOT pin. This pin must be connected to a ceramic capaci- tor, Cboot, from the switch node, shown as C4 in the typical application. The LM26001 provides the VDD voltage inter- nally, so no external diode is needed. A minimum value of 0.1 uF is recommended for Cboot. Smaller values may result in insufficient hold up time for the drive voltage and increased power dissipation. During low Vin operation, when the on-time is extended, the bootstrap capacitor is at risk of discharging. If the Cboot capacitor is discharged below approximately 2.5V, the LM26001 enters a high frequency re-charge mode. The Cboot cap is re-charged via the LG synchronous FET shown in the block diagram. Switching returns to normal when the Cboot cap has been recharged. CATCH DIODE When the internal switch is off, output current flows through the catch diode. Alternately, when the switch is on, the diode sees a reverse voltage equal to Vin. Therefore, the important parameters for selecting the catch diode are peak current and peak inverse voltage. The average current through the diode is given by: ID AVE = Iload x (1-D) Where D is the duty cycle, defined as Vout/Vin. The catch diode conducts the largest currents during the lowest duty cycle. Therefore ID AVE should be calculated assuming maxi- mum input voltage. The diode should be rated to handle this current continuously. For over-current or short circuit condi- tions, the catch diode should be rated to handle peak cur- rents equal to the peak current limit. The peak inverse voltage rating of the diode must be greater than maximum input voltage. A Schottky diode must be used. It’s low forward voltage maximizes efficiency and BOOT voltage, while also protect- ing the SW pin against large negative voltage spikes COMPENSATION The purpose of loop compensation is to ensure stable op- eration while maximizing dynamic performance. Stability can be analyzed with loop gain measurements, while dynamic performance is analyzed with both loop gain and load tran- sient response. Loop gain is equal to the product of control- output transfer function (power stage) and the feedback transfer function (the compensation network). For stability purposes, our target is to have a loop gain slope that is -20dB /decade from a very low frequency to beyond the crossover frequency. Also, the crossover frequency should not exceed one-fifth of the switching frequency, i.e. 60 kHz in the case of 300 kHz switching frequency. For dynamic purposes, the higher the bandwidth, the faster the load transient response. A large DC gain means high DC regulation accuracy (i.e. DC voltage changes little with load or line variations). To achieve this loop gain, the compensa- tion components should be set according to the shape of the control-output bode plot. A typical plot is shown in Figure 8 below. LM26001 www.national.com13
- A second pole (fpc1) can also be placed at fz. This pole
quired for stability, C9 is very helpful in suppressing noise. too large, it will have no effect. taken in layout to minimize the effect of this switching noise. somewhat isolated from the rest of the ground plane. possible to the VIN pin and grounded close to the GND pin. are illustrated below in Figure 11. the dashed line in Figure 11. FIGURE 11. Example PCB Layout
Thermal Considerations and TSD (Continued) PswDC = D x Iload2 x (0.2 + 0.00065 x (Tj - 25)) PQG =V i nx4 . 6x1 0-9 x fsw PIq =V i nxI q PVBIAS = Vbias x IVBIAS Given this total power dissipation, junction temperature can be calculated as follows: Tj = Ta + (PDTOTAL x θJA) Where θJA=38˚C/W (typically) when using a multi-layer board with a large copper plane area.θJA varies with board type and metallization area. To calculate the maximum allowable power dissipation, as- sume Tj = 125˚C. To ensure that junction temperature does not exceed the maximum operating rating of 125˚C, power dissipation should be verified at the maximum expected operating frequency, ambient temperature, and input volt- age. The calculated maximum load current is based on continuous operation and may be exceeded during transient conditions. If the power dissipation remains above the maximum allow- able level, device temperature will continue to rise. When the junction temperature exceeds its maximum, the LM26001 engages Thermal Shut Down (TSD). In TSD, the part re- mains in a shutdown state until the junction temperature falls to within normal operating limits. At this point, the device restarts in soft-start mode. LM26001 www.national.com 16
Physical Dimensions inches (millimeters) unless otherwise noted eTSSOP-16 Package 16-Lead Exposed Pad TSSOP Package National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LM26001 1.5A Switching Regulator with High Efficiency Sleep Mode