LM2501

LM2501 NSC | Alldatasheet

Document overview

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Technical content

Features

n MPL-0 Meets MPL Physical Layer Specification n Configurable as a Serializer or Deserializer n Complete LVCMOS to MPL Translation n Serializes 8-bit Camera Interface — 8-bit color data — plus VSYNC and HSYNC bits n Link power down mode reduces quiescent power under ∼ 10 µA (actual TBD) n 1.7V–3.1V and 2.9-3.1V Supply Voltage n Interfaces to 1.8V–3.0V Logic n Offered in a small 24L UCSP Package — 3.5 mm X 4.5 mm — 0.6 mm Max Height System Benefits n Reduced Wire Interface n Low Power n Low EMI n Extra Clock Transport n Intrinsic Level Translation Typical Application Diagram 20091601

Ordering Information

LM2501SL 24-Lead Ultra Thin CSP 3.5 X 4.5 X 0.6 mm SLE24A I2C® is a registered trademark of Phillips Corporation. ADVANCE INFORMATION June 2004 LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer © 2004 National Semiconductor Corporation DS200916 www.national.com

General Block Diagrams: Serializer and Deserializer 20091613 LM2501 www.national.com 2

Pin Name No. of Pins I/O, Type Description MPL SERIAL BUS PINS MD 1 IO, MPL MPL Data line. Serializer is a Line Driver. Deserializer is a Receiver. Configured by the Mode[1:0] pins. MC 1 IO, MPL MPL Clock line. Serializer is a Line Driver. Deserializer is a Receiver. Configured by the Mode[1:0] pins. MG 1 Ground See VSSA below. CONFIGURATION/PARALLEL BUS PINS Mode[1:0] 2 I, LVCMOS Mode Configuration Input pins: Mode[1:0], NOTE - Applies to REV F/G Samples only. 00 : Deserializer 01 : Serializer with PD* input 10 : Reserved 11 : Reserved PD* 1 I, LVCMOS Power_Down. Input pin. Active Low. When PD* is Low the device is in the sleep state. D0–D7 8 IO, LVCMOS 8-bit Bi-directional Data Bus – Serializer Input, Deserializer Output VS 1 IO, LVCMOS VSYNC – Serializer Input, Deserializer Output HS 1 IO, LVCMOS HSYNC – Serializer Input, Deserializer Output PCLK 1 IO, LVCMOS Pixel Clock. Serializer Input, Deserializer Output WHISPER CLOCK WCLKIO 1 IO, LVCMOS Extra Clock Input for WhisperClock Link – Deserializer Input. Serializer Output. WC 1 IO, MPL Extra WhisperClock MPL signal – Serializer is an MPL input signal, Deserializer is an MPL output signal. POWER/GROUND PINS V DDA 1 Power Power Supply Pin for the MPL Interface. 3.0V ± 3% VSSA 1 Ground Ground Pin for the MPL Interface, also known as MG (MPL Ground) VDD 1 Power Power Supply Pin for the digital core and Serializer PLL. 3.0V ± 3% VSS 1 Ground Ground Pin for the digital core and Serializer PLL. VDDIO 1 Power Power Supply Pin for the parallel interface. 1.7V to 3.1V VSSIO 1 Ground Ground Pin for the parallel interface. Notes: I = Input, O = Output, IO = Input/Output Do NOT float unused inputs. Rev D/E Sampled on MPL200EVK Use prior datasheet edition Rev F S/D* and TM pins changed to Mode[1:0] Use this datasheet edition Rev G MPL RX enhancements LM2501 www.national.com3

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DDA) −0.3V to +TBDV Supply Voltage (VDD) −0.3V to +TBDV Supply Voltage (VDDIO) −0.3V to +TBDV LVCMOS Input/Output Voltage −0.3V to (V DDIO +0.3V) MPL Input/Output Voltage TBD Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature Soldering,

4 Seconds +260˚C

ESD Ratings: HBM, 1.5 kΩ, 100pF ≥ ±2k V EIAJ, 0Ω, 200 pF ≥±200V Maximum Package Power Dissipation Capacity at 25˚C Derate TBD Package above 25˚C TBD mW/˚C Recommended Operating Conditions Min Typ Max Units Supply Voltage VDDA to VSSA and VDD to VSS 2.9 3.0 3.1 V VDDIO to VSSIO 1.7 3.1 V PLK Clock Frequency 4 16 MHz WC Clock Frequency 4 28 MHz Ambient Temperature 0 25 70 ˚C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units MPL I OLL Logic Low Current 4.8 I B 5.0 IB 5.3 IB µA IOMS Mid Scale Current 3.0 I B µA IOHL Logic High Current 0.8 I B 1.0 IB 1.2 IB µA IB Current Bias 150 µA LVCMOS (1.7V to 3.1V) V IH Input Voltage High Level 0.7 VDDIO VDDIO +0.3 V VIL Input Voltage Low Level −0.3 0.3 V DDIO V IIN Input Current (includes I OZ) −5 0 +5 µA IIH Input Current High Level −1 0 +1 µA IIL Input Current Low Level −1 0 +1 µA VOH Output Voltage High Level I OH =− 2m A 0 . 8V DDIO V VOL Output Voltage Low Level I OL = 2 mA 0.2 V DDIO V IOS Output Short Circuit Current VOUT =0 V TBD mA SUPPLY CURRENT ICC Total Supply Current — Enabled PCLK = 16MHz WC = 28MHz MD = 0101-1010 pattern C L =1 5p F Serializer TBD TBD µA Deserializer TBD TBD µA ICCZ Supply Current — Disable Power_Down Mode PD* = L 1 10 µA P D *=L 1 1 0 µ A LM2501 www.national.com 4

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units PARALLEL BUS TIMING t SET Set Time - Data to Clock Inputs Figure 2 TBD ns tHOLD Hold Time - Clock to Data TBD ns tRISE Rise Time Outputs, CL =1 5p F ns tFALL Fall Time ns PCLOW PCLK Low 50 % PCHIGH PCLK High 50 % tDVBC Data Valid before Clock Figure 2 TBD ns tDVAC Data Valid after Clock TBD ns SERIAL BUS TIMING t DVBC Figure 1 tDVAC POWER UP TIMING (seeFigures 5, 6) t1 WC Start Up Delay Figure 5 Planned Rev G ES test Chip will double WC cyc counts on T 1 to T4 (SER) parameters to support higher WC rates. 100 WC CYC t2 WC Low Initialization Low State 11 12 13 WC CYC t3 WC Pulse Width High 11 12 13 WC CYC t4 WC Low State 11 12 13 WC CYC t5 WCIN to WCOUT Latency (SER) 678 W C CYC t6 TBD 9W C CYC t7 SER PLL Lock Time Figure 6 4,096 MC CYC t8 MC Low Initialization Low State 11 12 13 MC CYC t9 MC Pulse Width High 11 12 13 MC CYC t10 MC Low State 11 12 13 MC CYC t11 SER Latency TBD MC CYC t12 DES Latency TBD MC CYC POWER OFF TIMING tPAZ Disable Time to Power Off µs tPZA Enable Time from Power Off µs LM2501 www.national.com5

Application Information

Typical application connections for the LM2501 are shown below. The application shown in Figure 3illustrates a connection between an Image sensor and a host utilizing an MPL-0 link. . 20091614 FIGURE 3. Camera Application

the requirements of the MPL-0 Standard (PHY Layer only). Data valid is relative to both edges as shown in Figure 4. Valid after Clock, (Note relative to both edges). TABLE 1. MPL Bus Phases FIGURE 4. Master-to-Slave Timing (MC, MDm)

or frequency relationship between WC and MC. FIGURE 5. Bus Power Up Timing — WC

will power down the entire device. TABLE 2. Power Down Output States ate logic states to set up the desired operating modes. VDDA. Do not power up with VDDIO before VDD and VDDA. and its PLL is powered down. cycle is requested to generate a RESET event. (4 MHz to 28 MHz) up to the Camera device from the host. the WCLKIO(ser-out) has been active. FIGURE 10. Sleep to Active

begin to lock if PCLK is present. FIGURE 11. Active to Sleep

Physical Dimensions inches (millimeters) unless otherwise noted Order Number LM2501SL LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.