LM124A STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
/uni25A0WIDE GAIN BANDWIDTH : 1.3MHz /uni25A0LARGE VOLTAGE GAIN : 100dB /uni25A0VERY LOW SUPPLY CURRENT/AMPLI : 375µA /uni25A0LOW INPUT BIAS CURRENT : 20nA /uni25A0LOW INPUT OFFSET VOLTAGE : 3mV max. /uni25A0LOW INPUT OFFSET CURRENT : 2nA /uni25A0WIDE POWER SUPPLY RANGE : SINGLE SUPPLY : +3V TO +30V DUAL SUPPLIES : ±1.5V TO ±15V /uni25A0INPUT COMMON-MODE VOLTAGE RANGE INCLUDES GROUND /uni25A0ESD INTERNAL PROTECTION : 2kV
DESCRIPTION
These circuits consist of four independent, high gain, internally frequency compensated operation- al amplifiers. They operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. All the pins are protected against electrostatic dis- charges up to 2000V (as a consequence, the input voltages must not exceed the magnitude of VCC or VCC -.) ORDER CODE N = Dual in Line Package (DIP) D = Small Outline Package (SO) - also available in Tape & Reel (DT) P = Thin Shrink Small Outline Package (TSSOP) - only available in Tape &Reel (PT) PIN CONNECTIONS (top view) Part Number Temperature Range Package N D P Example : LM224AN N DIP14 (Plastic Package) D SO14 (Plastic Micropackage) N DIP14 (Plastic Package) P TSSOP14 (Thin Shrink Small Outline Package) /C73/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C50 /C78/C111/C110/C45/C105/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C50 /C78/C111/C110/C45/C105/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C49 /C67/C67/C86/C32/C32/C32/C32/C32 /C45/C67/C67/C86 /C49 /C50 /C51 /C52 /C56 /C53 /C54 /C55 /C57 /C49/C48 /C49/C49 /C49/C50 /C49/C51 /C49/C52 /C43 /C79/C117/C116/C112/C117/C116/C32/C51 /C79/C117/C116/C112/C117/C116/C32/C52 /C78/C111/C110/C45/C105/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C52 /C73/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C52 /C78/C111/C110/C45/C105/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C51 /C73/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C51 /C45 /C43 /C45 /C43 /C45 /C43 /C45 /C43 /C79/C117/C116/C112/C117/C116/C32/C49 /C73/C110/C118/C101/C114/C116/C105/C110/C103/C32/C73/C110/C112/C117/C116/C32/C49 /C79/C117/C116/C112/C117/C116/C32/C50 LM124A LM224A - LM324A LOW POWER QUAD OPERATIONAL AMPLIFIERS March 2001
SCHEMATIC DIAGRAM (1/4 LM124A) ABSOLUTE MAXIMUM RATINGS Symbol Parameter LM124A LM224A LM324A Unit VCC Supply voltage ±16 or 32 V Vi Input Voltage -0.3 to +32 V Vid Differential Input Voltage 1) 1. Either or both input voltages must not exceed the magnitude of VCC + or VCC +32 +32 +32 V Ptot Power Dissipation N Suffix D Suffix 500 500 400 500 400 mW mW Output Short-circuit Duration 2. Short-circuits from the output to VCC can cause excessive heating if VCC > 15V. The maximum output current is approximately 40mA independent of the magnitude of VCC . Destructive dissipation can result from simultaneous short-circuit on all amplifiers. Infinite Iin Input Current 3) 3. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistor becoming forward biased and thereby acting as input diodes clamps. In addition to this diode action, there is also NPN parasitic action on the IC chip. this transistor action can cause the output voltages of the Op-amps to go to the VCC voltage level (or to ground for a large overdrive) for the time duration than an input is driven negative. This is not destructive and normal output will set up again for input voltage higher than -0.3V. 50 50 50 mA Toper Opearting Free-air Temperature Range -55 to +125 -40 to +105 0 to +70 ° C Tstg Storage Temperature Range -65 to +150 -65 to +150 -65 to +150 ° C
ELECTRICAL CHARACTERISTICS
+ = +5V, VCC -= Ground, Vo = 1.4V, Tamb = +25° C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Vio Input Offset Voltage - note 1) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 2 3 mV Iio Input Offset Current Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 2 20 nA Iib Input Bias Current - note 2) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 20 100 200 nA Avd Large Signal Voltage Gain VCC + = +15V, RL = 2kΩ, Vo = 1.4V to 11.4V Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 100 V/mV SVR Supply Voltage Rejection Ratio (R s ≤ 10kΩ ) VCC + = 5V to 30V Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 110 dB I CC Supply Current, all Amp, no load Tamb = +25° C VCC = +5V VCC = +30V Tmin ≤ Tamb ≤ Tmax VCC = +5V VCC = +30V 0.7 1.5 0.8 1.5 1.2 1.2 mA V icm Input Common Mode Voltage Range VCC = +30V - note 3) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax V CC -1.5 VCC -2 V CMR Common Mode Rejection Ratio (Rs ≤ 10kΩ ) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax dB I source Output Current Source (Vid = +1V) VCC = +15V, Vo = +2V 20 40 70 mA Isink Output Sink Current (Vid = -1V) VCC = +15V, Vo = +2V VCC = +15V, Vo = +0.2V mA µA V OH High Level Output Voltage VCC = +30V Tamb = +25° C RL = 2kΩ Tmin ≤ Tamb ≤ Tmax Tamb = +25° C RL = 10kΩ Tmin ≤ Tamb ≤ Tmax VCC = +5V, RL = 2kΩ Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 3.5 V VOL Low Level Output Voltage (R L = 10kΩ ) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 5 20 mV
V CC = 15V, Vi = 0.5 to 3V, RL = 2kΩ , CL = 100pF, unity Gain 0.4 V/µs GBP Gain Bandwidth Product VCC = 30V, f =100kHz,Vin = 10mV, RL = 2kΩ , CL = 100pF 1.3 MHz THD Total Harmonic Distortion f = 1kHz, Av = 20dB, RL = 2kΩ, Vo = 2Vpp, C L = 100pF, VCC = 30V 0.015 en Equivalent Input Noise Voltage f = 1kHz, Rs = 100Ω, VCC = 30V 40 DV io Input Offset Voltage Drift 7 30 µV/° C DIIio Input Offset Current Drift 10 200 pA/° C Vo1/Vo2 Channel Separation - note 4) 1kHz ≤ f≤ 20kHZ 120 dB 1. The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output so no loading change exists on the input lines. 2. V o = 1.4V, Rs = 0Ω , 5V < VCC + < 30V, 0 < Vic < VCC + - 1.5V 3. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range is VCC + - 1.5V, but either or both inputs can go to +32V without damage. 4. Due to the proximity of external components insure that coupling is not originating via stray capacitance between these external parts. This typically can be detected as this type of capacitance increases at higher frequences. Symbol Parameter Min. Typ. Max. Unit nV Hz
/C32/C32/C45/C53/C53/C45/C51/C53/C45/C49/C53/C32/C32/C53/C32/C32/C32/C50/C53/C32/C52/C53/C32/C54/C53/C32/C56/C53/C32/C49/C48/C53/C32/C49/C50/C53 /C65/C77/C66/C73/C69/C78/C84/C32/C84/C69/C77/C80/C69/C82/C65/C84/C85/C82/C69/C32/C40/C176/C67/C41 /C50/C52 /C50/C49 /C49/C56 /C49/C53 /C57 /C49/C50 /C54 /C51 /C48 /C73/C78/C80/C85/C84/C32/C66/C73/C65/C83/C32/C67/C85/C82/C82/C69/C78/C84 /C118/C101/C114/C115/C117/C115/C32/C65/C77/C66/C73/C69/C78/C84/C32/C84/C69/C77/C80/C69/C82/C65/C84/C85/C82/C69 /C73/C66/C32/C40/C110/C65/C41 /C83/C85/C80/C80/C76/C89/C32/C67/C85/C82/C82/C69/C78/C84/C32/C40/C109/C65/C41 /C83/C85/C80/C80/C76/C89/C32/C67/C85/C82/C82/C69/C78/C84 /C48 /C49/C48 /C50/C48 /C51/C48 /C84/C97/C109/C98/C32/C61/C32/C45/C53/C53/C176/C67 /C86/C67/C67 /C109/C65 /C73/C68 /C45 /C43 /C84/C97/C109/C98/C32/C61/C32/C48/C176/C67/C32/C116/C111/C32/C43/C49/C50/C53/C176/C67 /C80/C79/C83/C73/C84/C73/C86/C69/C32/C83/C85/C80/C80/C76/C89/C32/C86/C79/C76/C84/C65/C71/C69/C32/C40/C86/C41 /C52 /C51 /C50 /C49
TYPICAL SINGLE - SUPPLY APPLICATIONS AC COUPLED INVERTING AMPLIFIER AC COUPLED NON INVERTING AMPLIFIER
TYPICAL SINGLE - SUPPLY APPLICATIONS NON-INVERTING DC GAIN HIGH INPUT Z ADJUSTABLE GAIN DC INSTRUMENTATION AMPLIFIER DC SUMMING AMPLIFIER LOW DRIFT PEAK DETECTOR if R1 = R5 and R3 = R4 = R6 = R7 e0 = (e 2 -e1) As shown e0 = 101 (e2 - e1). 2R 1 R 2 e0 = e1 +e2 -e3 -e4 Where (e1 +e2)≥ (e3 +e4) to keep e0 ≥ 0V
TYPICAL SINGLE - SUPPLY APPLICATIONS ACTIVER BANDPASS FILTER HIGH INPUT Z, DC DIFFERENTIAL AMPLIFIER USING SYMETRICAL AMPLIFIERS TO REDUCE INPUT CURRENT (GENERAL CONCEPT) Fo = 1kHz Q = 50 Av = 100 (40dB) For (CMRR depends on this resistor ratio match) R 1 R 2 - - - - - - - R 4 R 3 - - - - - - - = e0 (e2 - e1) As shown e0 = (e2 - e1) R 4 R 3 - - - - - - - +
Standard Linear Ics Macromodels, 1993. CONNECTIONS : * 1 INVERTING INPUT * 2 NON-INVERTING INPUT * 3 OUTPUT * 4 POSITIVE POWER SUPPLY * 5 NEGATIVE POWER SUPPLY .SUBCKT LM124 1 3 2 4 5 (analog) .MODEL MDTH D IS=1E-8 KF=3.104131E-15 CJO=10F * INPUT STAGE CIP 2 5 1.000000E-12 CIN 1 5 1.000000E-12 EIP 10 5 2 5 1 EIN 16 5 1 5 1 RIP 10 11 2.600000E+01 RIN 15 16 2.600000E+01 RIS 11 15 2.003862E+02 DIP 11 12 MDTH 400E-12 DIN 15 14 MDTH 400E-12 VOFP 12 13 DC 0 VOFN 13 14 DC 0 IPOL 13 5 1.000000E-05 CPS 11 15 3.783376E-09 DINN 17 13 MDTH 400E-12 VIN 17 5 0.000000e+00 DINR 15 18 MDTH 400E-12 VIP 4 18 2.000000E+00 FCP 4 5 VOFP 3.400000E+01 FCN 5 4 VOFN 3.400000E+01 FIBP 2 5 VOFN 2.000000E-03 FIBN 5 1 VOFP 2.000000E-03 * AMPLIFYING STAGE FIP 5 19 VOFP 3.600000E+02 FIN 5 19 VOFN 3.600000E+02 RG1 19 5 3.652997E+06 RG2 19 4 3.652997E+06 CC 19 5 6.000000E-09 DOPM 19 22 MDTH 400E-12 DONM 21 19 MDTH 400E-12 HOPM 22 28 VOUT 7.500000E+03 VIPM 28 4 1.500000E+02 HONM 21 27 VOUT 7.500000E+03 VINM 5 27 1.500000E+02 EOUT 26 23 19 5 1 VOUT 23 5 0 ROUT 26 3 20 COUT 3 5 1.000000E-12 DOP 19 25 MDTH 400E-12 VOP 4 25 2.242230E+00 DON 24 19 MDTH 400E-12 VON 24 5 7.922301E-01 .ENDS + = +15V, Vcc -= 0V, Tamb = 25° C (unless otherwise specified) Symbol Conditions Value Unit Vio 0 mV Avd R L = 2kΩ 100 V/mV Icc No load, per amplifier 350 µA Vicm -15 to +13.5 V VOH R L = 2kΩ (VCC +=15V) +13.5 V VOL R L = 10kΩ 5 mV Ios Vo = +2V, VCC = +15V +40 mA GBP R L = 2kΩ, C L = 100pF 1.3 MHz SR R L = 2kΩ, C L = 100pF 0.4 V/ µs
14 PINS - PLASTIC DIP
Dim. Millimeters Inches a1 0.51 0.020 B 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 i 5.1 0.201 L 3.3 0.130 Z 1.27 2.54 0.050 0.100
14 PINS - PLASTIC MICROPACKAGE (SO)
Dim. Millimeters Inches A 1.75 0.069 a1 0.1 0.2 0.004 0.008 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D (1) 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F (1) 3.8 4.0 0.150 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.020 0.050 M 0.68 0.027 S 8° (max.) Note : (1) D and F do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.066 inc) ONLY FOR DATA BOOK. D M F 1 7 b e E L G C c1 A b1s
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com PACKAGE MECHANICAL DATA
14 PINS - THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Dim. Millimeters Inches A 1.20 0.05 A1 0.05 0.15 0.01 0.006 b 0.19 0.30 0.007 0.15 c 0.09 0.20 0.003 0.012 E 6.40 0.252 e 0.65 0.025 k 0° 8° 0° 8° c k L E e b D PIN 1 IDENTIFICATION SEATING PLANE C aaa C 0,25 mm .010 inch GAGE PLANE A