LM21212-1 TI | Alldatasheet
Document overview
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Technical content
208,9,10 5,6,7 R F SS/ TRK C SS 2optional HTSSOP-20 optional Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM21212-1 SNVS671F –FEBRUARY 2011–REVISED MAY 2019 LM21212-12.95-VTo5.5-V,12-A,Voltage-ModeSynchronousBuckRegulatorWith FrequencySynchronization
1 Features
1• Integrated 7-mΩ high-side and 4.3-mΩ low-side FET switches
- 300-kHz to 1.5-MHz frequency SYNC pin
- Adjustable output voltage from 0.6 V to VIN (100% duty cycle capable), ±1% reference
- Input voltage range 2.95 V to 5.5 V
- Start-up Into prebiased loads
- Output voltage tracking capability
- Wide bandwidth voltage loop error amplifier
- Adjustable soft-start with external capacitor
- Precision enable (EN) pin with hysteresis
- Integrated OVP, OCP, OTP, UVLO and power- good
- Thermally enhanced HTSSOP-20 exposed pad package
- Create a custom design using the LM21212-1 with the WEBENCH® Power Designer
2 Applications
- Broadband, networking and wireless communications
- High-performance FPGAs, ASICs and microprocessors
- Simple to design, high efficiency point-of-load regulation from a 5-V or 3.3-V bus
3 Description
The LM21212-1 is a monolithic synchronous point-of- load buck regulator that is capable of delivering up to
12 A of continuous output current while producing an
output voltage down to 0.6 V with outstanding efficiency. The device is optimized to work over an input voltage range of 2.95 V to 5.5 V, making it suited for a wide variety of low voltage systems. The voltage mode control loop provides high noise immunity, narrow duty-cycle capability and can be compensated to be stable with any type of output capacitance, providing maximum flexibility and ease of use. The LM21212-1 features internal overvoltage protection (OVP) and overcurrent protection (OCP) for increased system reliability. A precision enable pin and integrated UVLO allow turnon of the device to be tightly controlled and sequenced. Start-up inrush currents are limited by both an internally fixed and externally adjustable soft-start circuit. Fault detection and supply sequencing are possible with the integrated power good circuit. The LM21212-1 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track an external voltage rail using the SS/TRK pin. The switching frequency can be synchronized to the falling edge of a clock between frequencies of 300 kHz to 1.5 MHz. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM21212-1 HTSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Circuit
SNVS671F –FEBRUARY 2011–REVISED MAY 2019 www.ti.com Product Folder Links: LM21212-1 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Table of Contents
11.2 Receiving Notification Of Documentation
12 Mechanical, Packaging, And Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2013) to Revision F Page Changes from Revision D (March 2013) to Revision E Page
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5 Description
If the output is prebiased at start-up, it does not sink current, allowing the output to smoothly rise past the prebiased voltage. The regulator is offered in a 20-pin HTSSOP package with an exposed pad that can be soldered to the PCB, eliminating the need for bulky heat sinks.
6 Pin Configuration and Functions
DESCRIPTION
NO. NAME 1 SYNC Frequency synchronization input pin. Applying a clock signal to this pin will force the device to switch at the clock frequency. If left unconnected, the frequency will default to 1 MHz.
2 SS/TRK
Soft-start control pin. An internal 2-µA current source charges an external capacitor connected between this pin and AGND to set the output voltage ramp rate during startup. This pin can also be used to configure the tracking feature. 3 EN Active high enable input for the device. If not used, the EN pin can be left open, which goes high due to an internal current source.
4 AVIN
Analog input voltage supply that generates the internal bias. It is recommended to connect PVIN to AVIN through a low pass RC filter to minimize the influence of input rail ripple and noise on the analog control circuitry. 5,6,7 PVIN Input voltage to the power switches inside the device. These pins should be connected together at the device. Place a low ESR input capacitance as close as possible to these pins. 8,9,10 PGND Power ground pins for the internal power switches. 11-16 SW Switch node pins. These pins should be tied together locally and connected to the filter inductor. 17 PGOOD Open-drain power good indicator. 18 COMP Compensation pin is connected to the output of the voltage loop error amplifier. 19 FB Feedback pin is connected to the inverting input of the voltage loop error amplifier. 20 AGND Quiet analog ground for the internal reference and bias circuitry. EP Exposed Pad Exposed metal pad on the underside of the package with an electrical and thermal connection to PGND. TI recommends connecting this pad to the PC board ground plane in order to improve thermal dissipation.
SNVS671F –FEBRUARY 2011–REVISED MAY 2019 www.ti.com Product Folder Links: LM21212-1 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) The PVIN pin can tolerate transient voltages up to 6.5 V for a period of up to 6 ns. These transients can occur during the normal operation of the device. (4) The SW pin can tolerate transient voltages up to 9 V for a period of up to 6 ns, and –1 V for a duration of 4 ns. These transients can occur during the normal operation of the device.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(1)(2) MIN MAX UNIT PVIN(3), AVIN to GND −0.3 6 V SW(4), EN, FB, COMP, PGOOD, SS/TRK to GND −0.3 V Lead temperature (soldering, 10 sec.) 260 °C Storage temperature, Tstg −65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor to each pin.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVIN, AVIN to GND 2.95 5.5 V Junction temperature −40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. (2) Thermal measurements were performed on a 2 × 2 inch, 4 layer, 2 oz. copper outer layer, 1 oz .copper inner layer board with twelve 8 mil. vias underneith the EP of the device and an additional sixteen 8 mil. vias under the unexposed package.
7.4 Thermal Information
THERMAL METRIC(1) LM21212-1 UNITPWP (HTSSOP)
20 PINS
RθJA Junction-to-ambient thermal resistance (2) 24 °C/W
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7.5 Electrical Characteristics
Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5 V. Minimum and maximum limits are specified through test, design, or statistical correlation, and, unless otherwise specified, apply over the junction temperature (TJ) range of −40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB Feedback pin voltage VIN = 2.95 V to 5.5 V –1% 0.6 1% V ΔVOUT/ΔIOUT Load Regulation 0.02 %VOUT/ A ΔVOUT/ΔVIN Line Regulation 0.1 %VOUT/ V RDSON HS High Side Switch On Resistance ISW = 12 A 7 9 mΩ RDSON LS Low Side Switch On Resistance ISW = 12A 4.3 6 mΩ ICLR HS Rising Switch Current Limit 15 17 19 A ICLF LS Falling Switch Current Limit 12 A VZX Zero Cross Voltage TJ = 25°C –8 3 12 mV IQ Operating Quiescent Current 1.5 3 mA ISD Shutdown Quiescent Current VEN = 0V 50 70 µA VUVLO AVIN Under Voltage Lockout AVIN Rising 2.45 2.70 2.95 V VUVLOHYS AVIN Under Voltage Lockout Hysteresis 140 200 280 mV VTRACKOS SS/TRACK PIN accuracy (VSS - VFB) 0 < VTRACK < 0.55 V – 10 6 20 mV ISS Soft-Start Pin Source Current 1.3 1.9 2.5 µA tINTSS Internal Soft-Start Ramp to Vref CSS = 0 350 500 675 µs tRESETSS Device Reset to Soft-Start Ramp 50 110 200 µs OSCILLATOR fSYNCR SYNC Frequency Range 300 1500 kHz fDEFAULT Default (no SYNC signal) Frequency 950 1000 1050 kHz tSY_SW Time from SYNC falling to VSW Rising 200 ns tSY_MIN Minimum SYNC pin pulse width, high or low 100 ns tHSBLANK HS OCP Blanking Time Rising edge of SW to ICLR comparison 55 ns tLSBLANK LS OCP Blanking Time Falling edge of SW to ICLF comparison 400 ns tZXBLANK Zero Cross Blanking Time Falling edge of SW to VZX comparison 120 ns tMINON Minimum HS on-time 140 ns ΔVramp PWM Ramp p-p Voltage 0.8 V
SNVS671F –FEBRUARY 2011–REVISED MAY 2019 www.ti.com Product Folder Links: LM21212-1 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Electrical Characteristics (continued) Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5 V. Minimum and maximum limits are specified through test, design, or statistical correlation, and, unless otherwise specified, apply over the junction temperature (TJ) range of −40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER VOL Error Amplifier Open Loop Voltage Gain ICOMP = –65 µA to 1 mA 95 dBV/V GBW Error Amplifier Gain- Bandwidth Product
11 MHz
VFB = 0.6 V 1 nA ICOMPSRC COMP Output Source Current 1 mA ICOMPSINK COMP Output Sink Current 65 µA POWERGOOD VOVP Overvoltage Protection Rising Threshold VFB Rising 105 112.5 120 %VFB VOVPHYS Overvoltage Protection Hysteresis VFB Falling 2 %VFB VUVP Undervoltage Protection Rising Threshold VFB Rising 82 90 97 %VFB VUVPHYS Undervoltage Protection Hysteresis VFB Falling 2.5 %VFB tPGDGL PGOOD Deglitch Low (OVP/UVP Condition Duration to PGOOD Falling) 15 µs tPGDGH PGOOD Deglitch High (minimum low pulse) 12 µs RPGOOD PGOOD Pull-down Resistance 10 20 40 Ω IPGOODLEAK PGOOD Leakage Current VPGOOD = 5V 1 nA LOGIC VIHSYNC SYNC Pin Logic High TJ = 25°C 2 V VILSYNC SYNC Pin Logic Low TJ = 25°C 0.8 V VIHENR EN Pin Rising Threshold VEN Rising 1.2 1.35 1.45 V VENHYS EN Pin Hysteresis 50 110 180 mV IEN EN Pin Pullup Current VEN = 0 V 2 µA THERMAL SHUTDOWN TTHERMSD Thermal Shutdown 165 °C TTHERMSDHYS Thermal Shutdown Hysteresis 10 °C
7.6 Typical Performance Characteristics
efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Figure 1. Efficiency Figure 2. Efficiency Figure 3. Efficiency Figure 4. Load Regulation Figure 5. Line Regulation Figure 6. Non-Switching IQTOTAL vs VIN
0.68V 0.54V PLL AVIN AVIN PVIN PVIN OR OR OR EA Driver 2.7V 1.35V 0.6V LM21212-1 www.ti.com SNVS671F –FEBRUARY 2011–REVISED MAY 2019 Product Folder Links: LM21212-1 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The LM21212-1 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 12A of continuous output current. The regulator utilizes voltage mode control with trailing edge modulation to optimize stability and transient response over the entire output voltage range. The device can operate at high switching frequency allowing use of a small inductor while still achieving high efficiency. The precision internal voltage reference allows the output to be set as low as 0.6V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the HTSSOP-20 package featuring an exposed pad to aid thermal dissipation. The LM21212-1 can be used in numerous applications to efficiently step-down from a 5V or 3.3V bus.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Frequency Synchronization
signal can be present on the SYNC pin before the device is powered on with no loading on the clock signal. of time necessary for the synchronization depends on the clock frequency. Figure 22. Frequency Synchronization
8.3.2 Precision Enable
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. to configure the device to turn-on at a precise input voltage.
8.3.3 UVLO
from responding to power-on glitches during start up. If desired the turnon in the design guide.
8.3.4 Current Limit
point, the device will resume normal switching.
8.3.5 Short-Circuit Protection
a highly inefficient manner, potentially causing thermal damage to the device or the bus supply. Figure 23. Current Limit Conditions
8.3.6 Thermal Protection
thermal limit will not stop the die from operating above the specified maximum operating temperature,125°C. Keep the die under 125°C to ensure correct operation.
8.3.7 Power-Good Flag
brought below the enable threshold 3) The device enters a pre-biased output condition (VFB>VSS). Figure 24 shows the conditions that will cause PGOOD to fall. Figure 24. Pgood Conditions
8.3.8 Light Load Operation
conduction mode (DCM), and the boundary condition. reducing the switching frequency and further improving light-load efficiency. Figure 25. Modes of Operation for LM21212-1
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 26. LM21212-1 Typical Application
9.2.1 Detailed Design Procedure
9.2.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM21212-1 device with the WEBENCH® Power Designer.
- Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
- Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
- Compare the generated design with other possible solutions from Texas Instruments.
pricing and component availability.
- Run electrical simulations to see important waveforms and circuit performance
- Run thermal simulations to understand board thermal performance
- Export customized schematic and layout into popular CAD formats
- Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2 Output Voltage
state conditions, the LM21212-1 will force VOUT such that VFB is driven to 0.6 V.
Figure 27. Setting VOUT
9.2.1.3 Precision Enable
external resistor divider from AVIN to EN and EN to AGND as shown below in Figure 28. Figure 28. Enable Startup Through Vin for RB range from 10kΩ to 100kΩ.
9.2.1.4 Soft Start
Figure 29. Soft Start Timing startup process. This also happens when the device enters short circuit mode from an over-current event.
9.2.1.5 Inductor Selection
device to operate in discontinuous conduction mode at a higher average output current. Figure 30. Switch And Inductor Current Waveforms
IIN-RMS = IOUT D(1 - D) VDROOP = 'IOUTSTEP x RESR + L x 'IOUTSTEP C OUT x (VIN - VOUT ) 'VOUT 'IL x 1 8 x fSW x COUT R ESR + L = (VIN ± VOUT ) D üIL fSW LM21212-1 www.ti.com SNVS671F –FEBRUARY 2011–REVISED MAY 2019 Product Folder Links: LM21212-1 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated Typical Application (continued) Once the ripple current has been determined, the appropriate inductor size can be calculated using the following equation: (5)
9.2.1.6 Output Capacitor Selection
The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM21212-1 that provide various advantages. The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting the value for the output capacitor, the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using the following formula: (6) where ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output, RESR (Ω) is the series resistance of the output capacitor, fSW (Hz) is the switching frequency, and COUT (F) is the output capacitance used in the design. The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using the following equation: (7) where, COUT (F) is the minimum required output capacitance, L (H) is the value of the inductor, VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations, ΔIOUTSTEP (A) is the load step change, RESR (Ω) is the output capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is the set regulator output voltage. Both the tolerance and voltage coefficient of the capacitor should be examined when designing for a specific output ripple or transient droop target.
9.2.1.7 Input Capacitor Selection
Quality input capacitors are necessary to limit the ripple voltage at the PVIN pin while supplying most of the switch current during the on-time. Additionally, they help minimize input voltage droop in an output current transient condition. In general, it is recommended to use a ceramic capacitor for the input as it provides both a low impedance and small footprint. Use of a high grade dielectric for the ceramic capacitor, such as X5R or X7R, will provide improved over-temperature performance and also minimize the DC voltage derating that occurs with Y5V capacitors. The input capacitors CIN1 and CIN2 should be placed as close as possible to the PVIN and PGND pins. Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the relationship: (8) As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device.
the input voltage supply and the LM21212-1, as well as the magnitude and slew rate of the output transient. inherent noise on PVIN from the sensitive analog circuitry connected to AVIN.
9.2.1.8 Control Loop Compensation
obtaining the open loop transfer function. loop diagram is shown in Figure 31. Figure 31. Loop Diagram transfer function; COMP to SW (Modulator) , SW to VOUT (Power Train), and VOUT to COMP (Error Amplifier). The COMP to SW transfer function is simply the gain of the PWM modulator.
A Bode plot showing the power train response can be seen below. Figure 32. Power Train Bode Plot an illustration of what the Error Amplifier Compensation transfer function will look like.
Figure 33. Type 3 Compensation Network Bode Plot pole and zero locations on the compensation components is described below.
C C3 = = 898 pF fLC fESR - fLC R C2 = R FB1 = 166: C C2 = C C1 SfSW R C1 C C1 -1 = 71 pF 1C C1 = SfLC R C1 = 1.99 nF R C1 = fcrossover fLC 'VRAMP VIN R FB1 = 100 kHz 17.4 kHz 10 k:0.8 V 5.0 V = 9.2 k: LM21212-1 www.ti.com SNVS671F –FEBRUARY 2011–REVISED MAY 2019 Product Folder Links: LM21212-1 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated where ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8V), and fCROSSOVER is the frequency at which the open-loop gain is a magnitude of 1. It is recommended that the fcrossover not exceed one-fifth of the switching frequency. The output capacitance, CO, depends on capacitor chemistry and bias voltage. For Multi- Layer Ceramic Capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased. Measuring the actual capacitance value for the output capacitors at the output voltage is recommended to accurately calculate the compensation network. The example given here is the total output capacitance using the three MLCC output capacitors biased at 1.2V, as seen in the typical application schematic, Figure 38. Note that it is more conservative, from a stability standpoint, to err on the side of a smaller output capacitance value in the compensation calculations rather than a larger, as this will result in a lower bandwidth but increased phase margin. First, a the value of RFB1 should be chosen. A typical value is 10kΩ. From this, the value of RC1 can be calculated to set the mid-band gain so that the desired crossover frequency is achieved: (14) Next, the value of CC1 can be calculated by placing a zero at half of the LC double pole frequency (fLC): (15) Now the value of CC2 can be calculated to place a pole at half of the switching frequency (fSW): (16) RC2 can then be calculated to set the second zero at the LC double pole frequency: (17) Last, CC3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor ESR: (18) An illustration of the total loop response can be seen in Figure 34.
Figure 34. Loop Response recalculating the compensation components may help but usually at the expense of phase margin.
9.2.2 Application Curves
Figure 35. Load Transient Response Figure 36. Output Voltage Ripple
10 Layout
10.1 Pcb Layout Considerations
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.
- Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
minimize both loop areas, the input capacitor should be placed as close as possible to the VIN pin. should be placed as close as possible to the SW pin and output capacitor.
- Minimize the copper area of the switch node. The six SW pins should be routed on a single top plane to the
inductor into the sensitive feedback or compensation traces.
- Have a solid ground plane between PGND, the EP and the input and output cap. ground connections. The
- Carefully route the connection from the VOUT signal to the compensation network. This node is high
inductor to avoid contaminating the feedback signal with switch noise.
- Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
- Provide adequate device heatsinking. For most 12A designs a four layer board is recommended. Use as
Figure 37. Schematic Of Lm21212-1 Highlighting Layout Sensitive Nodes
Figure 38. Typical Application Schematic 1 Table 1. Bill Of Materials (VIN = 3.3 - 5.5v, VOUT = 1.2v, IOUT = 12a, FSW = 500khz)
Figure 39. Typical Application Schematic 2 Table 2. Bill Of Materials (VIN = 4 V - 5.5 V, VOUT = 0.9v, IOUT = 8a, FSW = 1mhz)
10.2 Thermal Considerations
used to approximate the operating junction temperature of the device.
2 RDCR
thermal resistance for the LM21212-1, TA is the ambient temperature in °C, and IOUT is the output load current. occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. Figure 40. Thermal Resistance vs PCB Area (4 Layer Board) shown in Figure 38, assuming a θJA value of 24°C/W. Figure 41. Maximum Ambient Temperature vs Output Current (0 LFM)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With Webench® Tools
Click here to create a custom design using the LM21212-1 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:
- Run electrical simulations to see important waveforms and circuit performance
- Run thermal simulations to understand board thermal performance
- Export customized schematic and layout into popular CAD formats
- Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification Of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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11.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM21212MH-1/NOPB Active Production HTSSOP (PWP) | 20 73 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-1 LM21212MH-1/NOPB.A Active Production HTSSOP (PWP) | 20 73 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-1 LM21212MH-1/NOPBG4.A Active Production HTSSOP (PWP) | 20 73 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-1 LM21212MHE-1/NOPB Active Production HTSSOP (PWP) | 20 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM - LM21212 MH-1 LM21212MHE-1/NOPB.A Active Production HTSSOP (PWP) | 20 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-1 LM21212MHX-1/NOPB Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-1 LM21212MHX-1/NOPB.A Active Production HTSSOP (PWP) | 20 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LM21212 MH-1 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1
www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM21212MHE-1/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 LM21212MHX-1/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM21212MH-1/NOPB PWP HTSSOP 20 73 495 8 2514.6 4.06 LM21212MH-1/NOPB.A PWP HTSSOP 20 73 495 8 2514.6 4.06 LM21212MH-1/NOPBG4.A PWP HTSSOP 20 73 495 8 2514.6 4.06 Pack Materials-Page 3
www.ti.com MYB20XX (REV E) 4214875/A 02/2013 A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. C. Reference JEDEC Registration MO-153, Variation ACT. NOTES:
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