LM20133/LM20133Q 3A, Synchronous Buck Regulator with Input Synchronization (Rev. F)

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  • Manufacturer or author: Texas Instruments, Incorporated [SNVS526,F]
  • PDF pages: 29

Technical content

(optional) SYNC LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 3A,PowerWise® SynchronousBuckRegulatorwithInputSynchronization Check forSamples: LM20133 ,LM20133Q 1FEATURES DESCRIPTION The LM20133 is a fullfeaturedsynchronousbuck 2• LM20133Q isAEC-Q100 Qualifiedand regulatorcapableofdeliveringup to3A ofcontinuousManufactured on an Automotive Grade Flow outputcurrent.The currentmode controlloopcan be• InputVoltageRange 2.95Vto5.5V compensated to be stablewithvirtuallyany type of

  • AccurateCurrentLimitMinimizesInductor outputcapacitor.For most cases,compensatingthe device only requirestwo externalcomponents,Size providingmaximum flexibilityand ease of use. The• 97% Peak Efficiency deviceis optimizedto work over the inputvoltage• Frequency SynchronizationPin range of 2.95V to 5.5V making itsuitedfora wide
  • 32 m Ω IntegratedFET Switches varietyoflowvoltagesystems.
  • Startsup intoPre-BiasedLoads The devicefeaturesinternalover voltageprotection (OVP) and over currentprotection(OCP) circuitsfor• Output VoltageTracking increasedsystem reliability.A precisionenable pin• Peak CurrentMode Control and integratedUVLO allowstheturnon ofthedevice• AdjustableSoft-StartwithExternalCapacitor to be tightlycontrolledand sequenced. Start-up
  • PrecisionEnable Pin withHysteresis inrushcurrentsare limitedby bothan internallyfixed and externallyadjustableSoft-Startcircuit.Fault• IntegratedOVP, UVLO, Power Good and detectionand supplysequencingispossiblewiththeThermal Shutdown integratedpower good circuit.• HTSSOP 16-PinExposed Pad Package The switchingfrequencyof the LM20133 can be synchronizedto an externalclock by use of theAPPLICATIONS SYNC pin.The SYNC piniscapableofsynchronizing
  • Simple toDesign,High EfficiencyPointof toinputsignalsrangingfrom500 kHz to1.5MHz. Load Regulationfrom a 5V or 3.3Vbus The LM20133 isdesignedto work wellin multi-rail• High Performance DSPs, FPGAs, ASICs and power supplyarchitectures.The outputvoltageofthe Microprocessors devicecan be configuredtotracka highervoltagerail usingtheSS/TRK pin.IftheoutputoftheLM20133 is• Broadband, Networking and Optical pre-biasedatstartupitwillnotsinkcurrenttopulltheCommunications Infrastructure outputlow untilthe internalsoft-startramp exceeds thevoltageatthefeedbackpin. TypicalApplicationCircuit Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. DESCRIPTION CONTINUED The LM20133 isofferedina 16-pinHTSSOP package withan exposed pad thatcan be solderedtothePCB, eliminatingtheneed forbulkyheatsinks. Connection Diagram Top View See Package Number PWP0016A PIN DESCRIPTIONS Pin # Name Description 1 SS/TRK Soft-StartorTrackingcontrolinput.An internal5 µA currentsourcechargesan externalcapacitortosetthe Soft-Startramp rate.Ifdrivenby a externalsourcelessthan800 mV, thispinoverridestheinternalreference thatsetstheoutputvoltage.Ifleftopen,an internal1ms Soft-Startramp isactivated. 2 FB Feedback inputtotheerroramplifierfromtheregulatedoutput.Thispinisconnectedtotheinvertinginputof theinternaltransconductanceerroramplifier.An 800mV referenceconnectedtothenon-invertinginputofthe erroramplifiersetstheclosedloopregulationvoltageattheFB pin. 3 PGOOD Power good outputsignal.Open drainoutputindicatingtheoutputvoltageisregulatingwithintolerance.A pull-upresistorof10 to100 kΩ isrecommend formost applications. 4 COMP Externalcompensationpin.Connecta resistorand capacitortothispintocompensate thedevice. 5 NC These pinsmust be connectedtoGND toensureproperoperation. 6,7 PVIN Inputvoltagetothepower switchesinsidethedevice.These pinsshouldbe connectedtogetheratthedevice. A lowESR capacitorshouldbe placednearthesepinstostabilizetheinputvoltage. 8,9 SW Switchpin.The PWM outputoftheinternalpower switches. 10,11 PGND Power groundpinfortheinternalpower switches. 12 EN Precisionenableinputforthedevice.An externalvoltagedividercan be used tosetthedeviceturn-on threshold.Ifnotused theEN pinshouldbe connectedtoPVIN. 13 VCC Internal2.7Vsub-regulator.Thispinshouldbe bypassedwitha 1 µF ceramiccapacitor. 14 AVIN Analoginputsupplythatgeneratestheinternalbias.Must be connectedtoVIN througha lowpass RC filter. 15 AGND Quietanaloggroundfortheinternalbiascircuitry. 16 SYNC Frequencysynchronizationpin.An externalclockconnectedtothispinwillsettheswitchingfrequency.Ifleft open thedevicewillswitchatapproximately410 kHz. EP Exposed Pad Exposed metalpad on theundersideofthepackage witha weak electricalconnectiontoground.Itis recommended toconnectthispad tothePC boardgroundplaneinordertoimproveheatdissipation.

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LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) VoltagesfromtheindicatedpinstoGND AVIN,PVIN,EN, PGOOD, SS/TRK, COMP, FB, SW, SYNC -0.3Vto+6V StorageTemperature -65°C to150°C JunctionTemperature 150°C Power Dissipation(2) 2.6W Lead Temperature(Soldering,10 sec) 260°C Minimum ESD Rating ±2kV (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notspecificperformancelimits.Forspecificationsand testconditions,see the ElectricalCharacteristics. (2) The maximum allowablepower dissipationisa functionofthemaximum junctiontemperature,TJ_MAX ,thejunctions-to-ambientthermal resistance,θJA,and theambienttemperature,TA.The maximum allowablepower dissipationatany ambienttemperatureiscalculated using:PD_MAX = (TJ_MAX – TA)/θJA.The maximum power dissipationsof2.6W isdeterminedusingTA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. OPERATING RATINGS PVIN,AVIN toGND 2.95Vto5.5V JunctionTemperature −40°C to+ 125°C Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM20133 LM20133Q

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ELECTRICAL CHARACTERISTICS

Unlessotherwisestated,thefollowingconditionsapply:AVIN = PVIN = VIN = 5V.LimitsinstandardtypeareforTJ = 25°C only,limitsinboldfacetypeapplyoverthejunctiontemperature(TJ)rangeof-40°C to+125°C. Minimum and Maximum limits arespecifiedby test,design,orstatisticalcorrelation.Typicalvaluesrepresentthemost likelyparametricnorm atTJ = 25°C, and areprovidedforreferencepurposesonly. Symbol Parameter Conditions Min Typ Max Unit ΔVOUT /ΔIOUT Load Regulation IOUT = 100 mA to3A 0.08 %/A ICL SwitchCurrentLimitThreshold VIN = 3.3V 4.7 5.2 5.7 A R DS_ON High-SideSwitchOn Resistance ISW = 3.5A 36 55 m Ω R DS_ON Low-SideSwitchOn Resistance ISW = 3.5A 32 52 m Ω IQ OperatingQuiescentCurrent Non-switching,VFB = VCOMP 3.5 6 mA ISD Shutdown Quiescentcurrent VEN = 0V 90 180 µA VUVLO VIN Under VoltageLockout RisingVIN 2.45 2.7 2.95 V VUVLO_HYS VIN Under VoltageLockoutHysteresis FallingVIN 45 100 mV VVCC VCC Voltage IVCC = 0 µA 2.45 2.7 2.95 V ISS Soft-StartPinSourceCurrent VSS/TRK = 0V 2 4.5 7 µA VTRACK SS/TRK Accuracy,VSS -VFB VSS/TRK = 0.4V -10 3 15 mV Oscillator FOSC OscillatorFrequency No ExternalSYNC Signal 360 410 460 kHz FOSCH Maximum ExternalSYNC Frequency 1500 kHz FOSCL Minimum ExternalSYNC Frequency 460 kHz VIH_SYNC SYNC pinLogicHigh 2 V VIL_SYNC SYNC pinLogicLow 0.8 V ISYNC SYNC pininputleakage VSYNC = 5V 10 nA DC MAX Maximum DutyCycle ILOAD = 0A 85 % TON_TIME Minimum On Time 100 ns TCL_BLANK CurrentSense BlankingTime AfterRisingVSW 80 ns ErrorAmplifierand Modulator IFB Feedback pinbiascurrent VFB = 0.8V 1 100 nA ICOMP_SRC COMP OutputSourceCurrent VFB = VCOMP = 0.6V 80 100 µA ICOMP_SNK COMP OutputSinkCurrent VFB = 1.0V,VCOMP = 0.6V 80 100 µA gm ErrorAmplifierTransconductance ICOMP = ± 50 µA 450 510 600 µmho AVOL ErrorAmplifierVoltageGain 2000 V/V Power Good VOVP Over VoltageProtectionRisingThreshold WithrespecttoVFB 105 108 111 % VOVP_HYS Over VoltageProtectionHysteresis 2 3 % VPGTH PGOOD RisingThreshold WithrespecttoVFB 92 94 96 % VPGHYS PGOOD FallingHysteresis 2 3 % TPGOOD PGOOD deglitchtime 16 µs IOL PGOOD Low SinkCurrent VPGOOD = 0.4V 0.6 1 mA IOH PGOOD HighLeakage Current VPGOOD = 5V 5 100 nA Enable VIH_EN EN PinTurnon Threshold VEN Rising 1.08 1.18 1.28 V VEN_HYS EN PinHysteresis 66 mV Thermal Shutdown TSD ThermalShutdown 160 °C TSD_HYS ThermalShutdown Hysteresis 10 °C Thermal Resistance θJA JunctiontoAmbient 38 °C/W

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LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,fSW = 1 MHz, TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. Efficiencyvs. Efficiencyvs. Load Current(VIN = 5V,fSW = 1.5MHz) Load Current(VIN = 3.3V,fSW = 1.5MHz) Figure1. Figure2. Efficiencyvs. Efficiencyvs. Load Current(VIN = 5V,fSW = 1 MHz) Load Current(VIN = 3.3V,fSW = 1 MHz) Figure3. Figure4. Efficiencyvs. Efficiencyvs. Load Current(VIN = 5V,fSW = 500 kHz) Load Current(VIN = 3.3V,fSW = 500 kHz) Figure5. Figure6. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM20133 LM20133Q

LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,fSW = 1 MHz, TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. High-SideFET resistance Low-Side FET resistance vs.Temperature vs.Temperature Figure7. Figure8. ErrorAmplifierGain vs.Frequency LineRegulation Figure9. Figure10. Feedback Voltage Load Regulation vs.Temperature Figure11. Figure12.

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LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,fSW = 1 MHz, TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. SwitchingFrequency vs.Temperature Switch Synchronization Figure13. Figure14. QuiescentCurrentvs. Shutdown Currentvs. VIN (NotSwitching) Temperature Figure15. Figure16. Enable Thresholdvs. UVLO Thresholdvs. Temperature Temperature Figure17. Figure18. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM20133 LM20133Q

LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,fSW = 1 MHz, TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. Peak CurrentLimitvs. Temperature Peak CurrentLimitvs.VOUT Figure19. Figure20. Peak CurrentLimitvs.VIN Load TransientResponse Figure21. Figure22. LineTransientResponse Start-Up(Soft-Start) Figure23. Figure24.

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LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,fSW = 1 MHz, TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. Start-Up(Tracking) Power Down Figure25. Figure26. ShortCircuitInputCurrentvs.VIN PGOOD vs.IPGOOD Figure27. Figure28. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM20133 LM20133Q

5.2A COMP CONTROL LOGIC CURRENT LIMIT OVERVOLTAGE UNDERVOLTAGE ERROR AMP PWM COMPARATOR SS/TRK PGOOD +2.7V REGULATOR PVIN PVIN THERMAL PROTECTION PGND SW AVIN CURRENT SENSE VCC 1.18V UVLO 2.7V AGND OSCILLATOR 752 mV 864 mV PG-L PG-L 2.7V 5 PA gm = 510 Pmho 800 mV DISCHARGE DISCHARGE SLOPE COMP DIODE EMULATION VREF+ FB EN (50 Ps) SYNC PVIN LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM OPERATION DESCRIPTION GENERAL The LM20133 switchingregulatorfeaturesallof the functionsnecessaryto implementan efficientlow voltage buck regulatorusing a minimum number of externalcomponents. This easy to use regulatorfeaturestwo integratedswitchesand iscapableofsupplyingup to3A ofcontinuousoutputcurrent.The regulatorutilizespeak currentmode controlwithnonlinearslopecompensationto optimizestabilityand transientresponseover the entireoutputvoltagerange.Peak currentmode controlalsoprovidesinherentlinefeed-forward,cycle-by-cycle currentlimitingand easy loopcompensation.The internaloscillatorcan synchronizeup to1.5MHz minimizing theinductorsizewhilestillachievingefficienciesup to96%. The precisioninternalvoltagereferenceallowsthe outputtobe setas lowas 0.8V.Faultprotectionfeaturesinclude:currentlimiting,thermalshutdown,overvoltage protection,and shutdown capability.The deviceis availablein the HTSSOP 16-pinpackage featuringan exposed pad toaidthermaldissipation.The LM20133 can be used innumerous applicationstoefficientlystep- down froma 5V or3.3Vbus.The typicalapplicationcircuitfortheLM20133 isshown inFigure30.

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LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 PRECISION ENABLE The enable(EN) pinallowstheoutputofthedevicetobe enabledor disabledwithan externalcontrolsignal. Thispinisa precisionanaloginputthatenablesthedevicewhen thevoltageexceeds1.18V(typical).The EN pin has 66 mV ofhysteresisand willdisabletheoutputwhen theenablevoltagefallsbelow 1.11V (typical).IftheEN pinisnotused,itshouldbe connectedtoVIN.Sincetheenablepinhas a preciseturnon thresholditcan be used alongwithan externalresistordividernetworkfromVIN toconfigurethedevicetoturnon ata preciseinput voltage.The precisionenablecircuitrywillremainactiveeven when thedeviceisdisabled. FREQUENCY SYNCHRONIZATION The frequencysynchronizationpin(SYNC) allowstheswitchingfrequencyofthedevicetobe controlledwithan externalclocksignal.This featureallowsthe user to synchronizemultipleconverters,avoidingundesirable frequencybands of operation.When used with the SYNCOUT of the LM20154, multipledevicescan be configuredtoswitchoutofphase reducinginputcapacitorrequirementsand EMI ofthepower supplysystem. The turnon ofthehighsideswitchwilllock-ontotherisingedge oftheSYNC pininput.The logiclow levelfor theinputclockmust be below 0.8V and thelogichighlevelmust exceed 2.0V forproperoperation.The device willsynchronizetofrequenciesfrom500 kHz to1.5MHz. Ifthesynchronizationclockisremoved ornotpresent duringstartup,theoscillatorofthedevicewillrunatapproximately410 kHz.IftheSYNC pinisnotused itshould be connectedtoground. PEAK CURRENT MODE CONTROL In most cases,the peak currentmode controlarchitectureused in the LM20133 onlyrequirestwo external components toachievea stabledesign.The compensationcan be selectedtoaccommodate any capacitortype or value.The externalcompensationalsoallowsthe user to set the crossoverfrequencyand optimizethe transientperformanceofthedevice. For dutycyclesabove 50% allcurrentmode controlbuck convertersrequiretheadditionofan artificialramp to avoidsub-harmonicoscillation.Thisartificiallinearramp iscommonly referredtoas slopecompensation.What makes theLM20133 uniqueistheamount ofslopecompensationwillchange dependingon theoutputvoltage. When operatingathighoutputvoltagesthedevicewillhave more slopecompensationthanwhen operatingat loweroutputvoltages.ThisisaccomplishedintheLM20133 by usinga non-linearparabolicramp fortheslope compensation.The parabolicslopecompensationoftheLM20133 ismuch betterthanthetraditionallinearslope compensationbecause itoptimizesthestabilityofthedeviceovertheentireoutputvoltagerange. CURRENT LIMIT The precisecurrentlimitof the LM20133 is set at the factoryto be within10% over the entireoperating temperaturerange.Thisenablesthedevicetooperatewithsmallerinductorsthathave lowersaturationcurrents. When thepeak inductorcurrentreachesthecurrentlimitthreshold,an overcurrenteventistriggeredand the internalhigh-sideFET turnsoffand thelow-sideFET turnson allowingtheinductorcurrenttoramp down until thenextswitchingcycle.Foreach sequentialover-currentevent,thereferencevoltageisdecrementedand PWM pulsesare skippedresultingina currentlimitthatdoes notaggressivelyfoldback forbriefover-currentevents, whileatthesame timeprovidingfrequencyand voltagefoldbackprotectionduringhardshortcircuitconditions. SOFT-START AND VOLTAGE TRACKING The SS/TRK pinisa dualfunctionpinthatcan be used to setthe startup timeor trackan externalvoltage source.The startup orSoft-Starttimecan be adjustedby connectinga capacitorfromtheSS/TRK pintoground. The Soft-Startfeatureallowsthe regulatoroutputto graduallyreach the steady stateoperatingpoint,thus reducingstresseson theinputsupplyand controllingstartup current.Ifno Soft-Startcapacitorisused thedevice defaultstotheinternalSoft-Startcircuitryresultingina startup timeofapproximately1 ms. For applicationsthat requirea monotonicstartup or utilizethe PGOOD pin,an externalSoft-Startcapacitorisrecommended. The SS/TRK pincan alsobe settotrackan externalvoltagesource.The trackingbehaviorcan be adjustedby two externalresistorsconnectedtotheSS/TRK pinas shown inFigure35 inthedesignguide. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM20133 LM20133Q

IBOUNDARY = (VIN ± VOUT ) x D 2 x L x fSW LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com PRE-BIAS START UP CAPABILITY The LM20133 isina pre-biasedstatewhen thedevicestartsup withan outputvoltagegreaterthanzero.This oftenoccurs in many multi-railapplicationssuch as when powering an FPGA, ASIC, or DSP. In these applicationsthe outputcan be pre-biasedthroughparasiticconductionpathsfrom one supplyrailto another. Even thoughtheLM20133 isa synchronousconverteritwillnotpulltheoutputlow when a pre-biascondition exists.Duringstartup theLM20133 willnotsinkcurrentuntiltheSoft-Startvoltageexceeds thevoltageon the FB pin.Since the devicecan not sinkcurrentitprotectsthe loadfrom damage thatmightotherwiseoccurif currentisconductedthroughtheparasiticpathsoftheload. POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20133 has builtinunderand overvoltagecomparatorsthatcontrolthepower switches.Whenever there isan excursioninoutputvoltageabove thesetOVP threshold,thepartwillterminatethepresenton-pulse,turn- on thelow sideFET, and pullthePGOOD pinlow.The low sideFET willremainon untileithertheFB voltage fallsback intoregulationor thezerocrossdetectionistriggeredwhich inturntri-statestheFETs. Iftheoutput reachesthe UVP thresholdthe partwillcontinueswitchingand the PGOOD pinwillbe assertedand go low. TypicalvaluesforthePGOOD resistorareon theorderof100 kΩ orless.To avoidfalsetrippingduringtransient glitchesthePGOOD pinhas 16 µs ofbuiltindeglitchtimetobothrisingand fallingedges. UVLO The LM20133 has a built-inunder-voltagelockoutprotectioncircuitthatkeeps thedevicefromswitchinguntilthe inputvoltagereaches2.7V (typical).The UVLO thresholdhas 45 mV ofhysteresisthatkeeps thedevicefrom respondingto power-on glitchesduringstartup. Ifdesiredthe turn-onpointof the supplycan be changed by usingthe precisionenablepinand a resistordividernetworkconnectedto VIN as shown inFigure34 inthe designguide. THERMAL PROTECTION Internalthermalshutdown circuitryisprovidedto protectthe integratedcircuitinthe eventthatthe maximum junctiontemperatureisexceeded.When activated,typicallyat 160°C, the LM20133 tri-statesthe power FETs and resetssoftstart.Afterthejunctioncoolstoapproximately150°C, thepartstartsup usingthenormalstartup routine.Thisfeatureisprovidedtopreventcatastrophicfailuresfromaccidentaldeviceoverheating. LIGHT LOAD OPERATION The LM20133 offersincreasedefficiencywhen operatingatlightloads.Whenever theloadcurrentisreducedto a pointwhere theinductorripplecurrentisgreaterthantwo timestheloadcurrent,thepartwillenterthediode emulationmode preventingsignificantnegativeinductorcurrent.The pointat which thisoccursisthe critical conductionboundaryand can be calculatedby thefollowingequation: (1) Several diagrams are shown in Figure 29 illustratingcontinuousconductionmode (CCM), discontinuous conductionmode, and theboundarycondition. Itcan be seen thatindiodeemulationmode, whenever the inductorcurrentreacheszero the SW node will become highimpedance.Ringingwilloccuron thispinas a resultoftheLC tankcircuitformedby theinductor and theparasiticcapacitanceatthenode.Ifthisringingisofconcernan additionalRC snubbercircuitcan be added fromtheswitchnode toground. Atverylightloads,usuallybelow100 mA, severalpulsesmay be skippedinbetween switchingcycles,effectively reducingtheswitchingfrequencyand furtherimprovinglight-loadefficiency.

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Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Time (s) Time (s) Time (s) Discontinuous Conduction Mode (DCM) DCM - CCM Boundary Continuous Conduction Mode (CCM) Continuous Conduction Mode (CCM) Switchnode Voltage Switchnode VoltageInductor CurrentInductor CurrentInductor Current VIN IAVERAGE IAVERAGE VIN LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 Figure29. Modes ofOperationforLM20133 Design Guide Thissectionwalksthedesignerthroughthestepsnecessarytoselecttheexternalcomponents tobuilda fully functionalpower supply.As withany DC-DC converternumerous trade-offsare possibletooptimizethedesign forefficiency,size,orperformance.These willbe takenintoaccountand highlightedthroughoutthisdiscussion. To facilitatecomponent selectiondiscussionsthecircuitshown inFigure30 below may be used as a reference. Unlessotherwiseindicatedallformulasassume unitsofamps (A)forcurrent,farads(F)forcapacitance,henries (H)forinductanceand volts(V)forvoltages. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM20133 LM20133Q

IL AVG = IOUT 'IL Time Time IL VSW LMIN = (VIN - VOUT ) x D 'iL x fSW D = VOUT VIN C IN PVIN SW GND FB PGOOD R FB1 R FB2 C OUT EN C SS SS/TRK AVIN C F C C1 COMP R C1 VIN LM20133 L R F VCC C VCC VOUT PGND VIN R PG VPGSYNC LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com Figure30. TypicalApplicationCircuit The firstequationtocalculateforany buck converterisduty-cycle.Ignoringconductionlossesassociatedwith theFETs and parasiticresistancesitcan be approximatedby: (2) INDUCTOR SELECTION (L) The inductorvalueisdeterminedbased on theoperatingfrequency,loadcurrent,ripplecurrent,and dutycycle. The inductorselectedshouldhave a saturationcurrentratinggreaterthanthepeak currentlimitofthedevice. Keep inmind thespecifiedcurrentlimitdoes notaccountfordelayofthecurrentlimitcomparator,thereforethe currentlimitintheapplicationmay be higherthanthespecifiedvalue.To optimizetheperformanceand prevent thedevicefrom enteringcurrentlimitatmaximum load,theinductanceistypicallyselectedsuch thattheripple current,ΔiL, islessthan 30% of the ratedoutputcurrent.Figure31, shown below illustratesthe switchand inductorripplecurrentwaveforms.Once theinputvoltage,outputvoltage,operatingfrequency,and desiredripple currentareknown,theminimum valuefortheinductorcan be calculatedby theformulashown below: (3) Figure31. Switch and InductorCurrentWaveforms Ifneeded,slightlysmallervalueinductorscan be used,however,thepeak inductorcurrent,IOUT + ΔiL/2,should be keptbelow thepeak currentlimitofthedevice.Ingeneral,theinductorripplecurrent,ΔiL,shouldbe greater than10% oftheratedoutputcurrenttoprovideadequatecurrentsense informationforthecurrentmode control loop.Ifthe ripplecurrentin the inductoris too low,the controlloop willnot have sufficientcurrentsense informationand can be pronetoinstability.

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IIN-RMS = IOUT D(1 - D) VDROOP = 'IOUTSTEP x RESR + L x 'IOUTSTEP C OUT x (VIN - VOUT ) 'VOUT = 'iL x 1 8 x fSW x COUT R ESR + LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 OUTPUT CAPACITOR SELECTION (COUT ) The outputcapacitor,C OUT ,filterstheinductorripplecurrentand providesa sourceofchargefortransientload conditions.A widerangeofoutputcapacitorsmay be used withtheLM20123 thatprovideexcellentperformance. The bestperformanceistypicallyobtainedusingceramic,SP, orOSCON typechemistries.Typicaltrade-offsare thatthe ceramiccapacitorprovidesextremelylow ESR to reduce the outputripplevoltageand noisespikes, whilethe SP and OSCON capacitorsprovidea largebulkcapacitanceina smallvolume fortransientloading conditions. When selectingthevaluefortheoutputcapacitorthetwo performancecharacteristicstoconsideraretheoutput voltagerippleand transientresponse.The outputvoltageripplecan be approximatedby usingtheformulashown below. where

  • ΔVOUT (V)istheamount ofpeak topeak voltagerippleatthepower supplyoutput
  • R ESR (Ω)istheseriesresistanceoftheoutputcapacitor
  • fSW (Hz)istheswitchingfrequency
  • C OUT (F)istheoutputcapacitanceused inthedesign (4) The amount ofoutputripplethatcan be toleratedisapplicationspecific;however a generalrecommendationisto keep theoutputripplelessthan1% oftheratedoutputvoltage.Keep inmind ceramiccapacitorsaresometimes preferredbecause theyhave verylow ESR; however,dependingon package and voltageratingofthecapacitor thevalueofthecapacitancecan drop significantlywithappliedvoltage.The outputcapacitorselectionwillalso affectthe outputvoltagedroop duringa loadtransient.The peak droop on the outputvoltageduringa load transientisdependenton many factors;however,a bestcase approximationofthetransientdroopignoringloop bandwidthcan be obtainedusingthefollowingequation. where
  • C OUT (F)istheminimum requiredoutputcapacitance
  • L (H)isthevalueoftheinductor
  • VDROOP (V)istheoutputvoltagedropignoringloopbandwidthconsiderations
  • ΔIOUTSTEP (A)istheloadstepchange
  • R ESR (Ω)istheoutputcapacitorESR
  • VIN (V)istheinputvoltage
  • VOUT (V)isthesetregulatoroutputvoltage (5) Both thetoleranceand voltagecoefficientofthecapacitorneeds tobe examined when designingfora specific outputrippleortransientdroptarget. INPUT CAPACITOR SELECTION (CIN) Good qualityinputcapacitorsarenecessarytolimittheripplevoltageattheVIN pinwhilesupplyingmost ofthe switchcurrentduringtheon-time.Ingeneralitisrecommended touse a ceramiccapacitorfortheinputas they providebotha low impedance and smallfootprint.One importantnoteistouse a good dielectricfortheceramic capacitorsuch as X5R orX7R. These providebetterovertemperatureperformanceand minimizetheDC voltage deratingthatoccurson Y5V capacitors.For most applications,a 22 µF, X5R, 6.3V inputcapacitorissufficient; however,additionalcapacitancemay be requirediftheconnectiontotheinputsupplyisfarfromthePVIN pins. The inputcapacitorshouldbe placedas closeas possiblePVIN and PGND pinsofthedevice. Non-ceramicinputcapacitorsshouldbe selectedforRMS currentratingand minimum ripplevoltage.A good approximationfortherequiredripplecurrentratingisgivenby therelationship: (6) Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM20133 LM20133Q

R FB1 = - 1 VOUT 0.8 x RFB2 LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com As indicatedby theRMS ripplecurrentequation,highestrequirementforRMS currentratingoccursat50% duty cycle.For thiscase,theRMS ripplecurrentratingoftheinputcapacitorshouldbe greaterthanhalftheoutput current.For bestperformance,low ESR ceramiccapacitorsshouldbe placedinparallelwithhighercapacitance capacitorstoprovidethebestinputfilteringforthedevice. SETTING THE OUTPUT VOLTAGE (RFB1 ,R FB2 ) The resistorsR FB1 and R FB2 areselectedtosettheoutputvoltageforthedevice.Table1 providessuggestions forR FB1 and R FB2 forcommon outputvoltages. Table1.Suggested Values forR FB1 and R FB2 R FB1 (kΩ) R FB2 (kΩ) VOUT short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 Ifdifferentoutputvoltagesarerequired,R FB2 shouldbe selectedtobe between 4.99kΩ to49.9kΩ and R FB1 can be calculatedusingtheequationbelow. (7) LOOP COMPENSATION (RC1 ,C C1 ) The purposeofloopcompensationistomeet staticand dynamic performancerequirementswhilemaintaining adequatestability.Optimalloopcompensationdepends on theoutputcapacitor,inductor,load,and thedevice itself.Table2 below givesvaluesforthecompensationnetworkthatwillresultina stablesystem when usinga 100 µF,6.3VceramicX5R outputcapacitorand 1 µH inductor. Table2.Recommended Compensation forC OUT = 100 µF,L = 1 µH & fSW = 1 MHz VIN VOUT C C1 (nF) R C1 (kΩ) 5.00 3.30 4.7 16.2 5.00 2.50 4.7 11.3 5.00 1.80 4.7 8.45 5.00 1.50 4.7 5.23 5.00 1.20 4.7 3.32 5.00 0.80 4.7 1.62 3.30 1.80 4.7 9.53 3.30 1.50 4.7 4.87 3.30 1.20 4.7 3.24 3.30 0.80 4.7 1.62 Ifthedesiredsolutiondiffersfromthetableabove thelooptransferfunctionshouldbe analyzedtooptimizethe loopcompensation.The overalllooptransferfunctionistheproductofthepower stageand thefeedbacknetwork transferfunctions.For stabilitypurposes,theobjectiveistohave a loopgainslopethatis-20db/decadefroma verylow frequencytobeyond thecrossoverfrequency.Figure32,shown below,shows thetransferfunctionsfor power stage,feedback/compensationnetwork,and theresultingclosedloopsystemfortheLM20133.

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R C1 = xC C1 C OUT IOUT VOUT + 15 x D VIN +1-D fSW x L COMP C C1 R C1 C C2 LM20133 (optional) AM fSW /2 0 dB FREQUENCY (Hz) GAIN (dB) Error Amp Zero, fZ(EA) Complex Double Pole, fP(MOD) Optional Error Amp Pole, fP2(EA) 0 dB 0 dB AEA + AM Error Amplifier Transfer Function Modulator and Output Filter Transfer Function Compensated Closed Loop Transfer Function AEA Error Amp Pole, fP1(EA) Complex Double Pole, fP(MOD) Output Filter Zero, fZ(FIL) Output Filter Pole, fP(FIL) fC Error Amp Pole, fP(EA) LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 Figure32. LM20133 Loop Compensation The power stagetransferfunctionisdictatedby the modulator,outputLC filter,and load;whilethe feedback transferfunctionissetby thefeedbackresistorratio,erroramp gain,and externalcompensationnetwork. To achievea -20dB/decadeslope,the erroramplifierzero,locatedat fZ(EA), shouldpositionedto cancelthe outputfilterpole(fP(FIL)).An additionalerroramp pole,locatedatfP2(EA),can be added tocanceltheoutputfilter zeroatfZ(FIL).Cancellationoftheoutputfilterzeroisrecommended iflargervalue,non-ceramicoutputcapacitors areused. CompensationoftheLM20133 isachievedby addingan RC networkas shown inFigure33 below. Figure33. Compensation Network forLM20133 A good startingvalueforC C1 formost applictionsis4.7nF. Once thevalueofC C1 ischosen thevalueofRC shouldbe calculatedusingtheequationbelowtocanceltheoutputfilterpole(fP(FIL))as shown inFigure32. (8) A highercrossoverfrequencycan be obtained,usuallyattheexpense ofphase margin,by loweringthevalueof C C1 and recalculatingthe valueof R C1 . Likewise,increasingC C1 and recalculatingR C1 willprovideadditional phase marginata lowercrossoverfrequency.As withany attempttocompensate theLM20133 thestabilityof thesystemshouldbe verifiedfordesiredtransientdroopand settlingtime. Iftheoutputfilterzero,fZ(FIL)approachesthecrossoverfrequency(FC ),an additionalcapacitor(CC2 ) shouldbe placedat the COMP pin to ground.This capacitoradds a pole to cancelthe outputfilterzero assuringthe crossoverfrequencywilloccurbeforethedoublepoleatfSW /2degradesthephase margin.The outputfilterzero issetby theoutputcapacitorvalueand ESR as shown intheequationbelow. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM20133 LM20133Q

tSS = 0.8V x CSS ISS C C2 = C OUT x RESR R C1 fZ(FIL) = 1 2 x S x COUT x RESR LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com (9) Ifneeded,thevalueforC C2 shouldbe calculatedusingtheequationshown below. where

  • R ESR istheoutputcapacitorseriesresistance
  • R C1 isthecalculatedcompensationresistance (10) AVIN FILTERING COMPONENTS (CF and R F) To preventhighfrequencynoisespikesfromdisturbingthesensitiveanalogcircuitryconnectedtotheAVIN and AGND pins,a highfrequencyRC filterisrequiredbetween PVIN and AVIN. These components are shown in The filtercapacitor,C F shouldbe placedas closetotheIC as possiblewitha directconnectionfrom AVIN to AGND. A good qualityX5R orX7R ceramiccapacitorshouldbe used forC F. SUB-REGULATOR BYPASS CAPACITOR (CVCC ) The capacitorat the VCC pin providesnoise filteringand stabilityfor the internalsub-regulator.The recommended valueofC VCC shouldbe no smallerthan1 µF and no greaterthan10 µF.The capacitorshouldbe a good qualityceramicX5R or X7R capacitor.Ingeneral,a 1 µF ceramiccapacitorisrecommended formost applications. SETTING THE START UP TIME (CSS ) The additionofa capacitorconnectedfrom theSS pintoground setsthetimeatwhich theoutputvoltagewill reachthefinalregulatedvalue.LargervaluesforC SS willresultinlongerstartup times.Table3,shown below providesa listofsoftstartcapacitorsand thecorrespondingtypicalstartup times. Table3.StartUp Times forDifferentSoft-StartCapacitors StartUp Time (ms) C SS (nF) 1 none 5 33 10 68 15 100 20 120 Ifdifferentstartup timesareneeded theequationshown belowcan be used tocalculatethestartup time. (11) As shown above,thestartup timeisinfluencedby thevalueoftheSoft-StartcapacitorC SS (F)and the5 µA Soft- StartpincurrentISS (A).thatmay be foundintheelectricalcharacteristicstable. WhiletheSoft-Startcapacitorcan be sizedtomeet many startup requirements,therearelimitationstoitssize. The Soft-Starttimecan neverbe fasterthan1 ms due totheinternaldefault1 ms startup time.When thedevice isenabledthereisan approximatetimeintervalof50 µs when theSoft-Startcapacitorwillbe dischargedjust priortotheSoft-Startramp.IftheenablepinisrapidlypulsedortheSoft-Startcapacitorislargetheremay notbe enough timeforC SS tocompletelydischargeresultinginstartup timeslessthanpredicted.To aidindischarging ofSoft-Startcapacitorduringlongdisableperiodsan external1 M Ω resistorfromSS/TRK togroundcan be used withoutgreatlyaffectingthestart-uptime. USING PRECISION ENABLE AND POWER GOOD The precisionenable (EN) and power good (PGOOD) pinsof the LM20133 can be used to address many sequencingrequirements.The turn-onoftheLM20133 can be controlledwiththeprecisionenablepinby using two externalresistorsas shown inFigure34.

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R A = - 1VTO VIH_EN x RB EN VOUT1 R A R B LM20133 External Power Supply VOUT2 LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 Figure34. Sequencing LM20133 withPrecisionEnable The valueforresistorR B can be selectedby the user to controlthe currentthroughthe divider.Typicallythis resistorwillbe selectedtobe between 10 kΩ and 1 M Ω.Once thevalueforR B ischosen theresistorR A can be solvedusingtheequationbelowtosetthedesiredturn-onvoltage. (12) When designingfora specificturn-onthreshold(VTO ) the toleranceon the inputsupply,enable threshold (VIH_EN ),and externalresistorsneeds tobe consideredtoinsureproperturn-onofthedevice. The LM20133 featuresan open drainpower good (PGOOD) pintosequence externalsuppliesor loadsand to providefaultdetection.Thispinrequiresan externalresistor(RPG )topullPGOOD highwhilewhen theoutputis withinthePGOOD tolerancewindow.Typicalvaluesforthisresistorrangefrom10 kΩ to100 kΩ. TRACKING AN EXTERNAL SUPPLY By usinga properlychosen resistordividernetworkconnectedtotheSS/TRK pin,as shown inFigure35,the outputof the LM20133 can be configuredto trackan externalvoltagesource to obtaina simultaneousor ratiometricstartup. Figure35. Trackingan ExternalSupply SincetheSoft-StartchargingcurrentISS isalwayspresenton theSS/TRK pin,thesizeofR2 shouldbe lessthan 10 kΩ to minimizethe errorsinthe trackingoutput.Once a valueforR2 isselectedthe valueforR1 can be calculatedusingappropriateequationinFigure36,togivethedesiredstartup.Figure36 shows two common startup sequences;thetopwaveform shows a simultaneousstartup whilethewaveform atthebottomillustrates a ratiometricstartup. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM20133 LM20133Q

= 1 R VOUT1 VOUT2 VEN OUT12OUT V x 8 . 0 <V ( ) x-1= 1 R 2 RV 1OUT

2 Rx-1V 2OUT

V 8 . 0 LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com Figure36. Common StartUp Sequences A simultaneousstartup ispreferredwhen poweringmost FPGAs, DSPs, or othermicroprocessors.In these systems the highervoltage,VOUT1 , usuallypowers the I/O,and the lowervoltage,VOUT2 , powers the core.A simultaneousstartup providesa more robustpower up fortheseapplicationssinceitavoidsturningon any parasiticconductionpathsthatmay existbetween thecoreand theI/Opinsoftheprocessor. The second most common power on behaviorisknown as a ratiometricstartup. Thisstartup ispreferredin applicationswhere bothsuppliesneed tobe atthefinalvalueatthesame time. SimilartotheSoft-Startfunction,thefasteststartup possibleis1 ms regardlessoftherisetimeofthetracking voltage.When usingthetrackfeaturethefinalvoltageseen by theSS/TRACK pinshouldexceed 1V toprovide sufficientoverdriveand transientimmunity.

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LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 THERMAL CONSIDERATIONS The thermalcharacteristicsof the LM20133 are specifiedusingthe parameterθJA, which relatesthe junction temperaturetotheambienttemperature.AlthoughthevalueofθJA isdependanton many variables,itstillcan be used toapproximatetheoperatingjunctiontemperatureofthedevice. To obtainan estimateofthedevicejunctiontemperature,one may use thefollowingrelationship: TJ = PD θJA + TA (13) and PD = PIN x (1-Efficiency)-1.1x IOUT 2 x DCR where

  • TJ isthejunctiontemperaturein°C
  • PIN istheinputpower inWatts(PIN = VIN x IIN)
  • θJA isthejunctiontoambientthermalresistancefortheLM20133
  • TA istheambienttemperaturein°C
  • IOUT istheoutputloadcurrent
  • DCR istheinductorseriesresistance (14) Itisimportanttoalwayskeep theoperatingjunctiontemperature(TJ) below 125°C forreliableoperation.Ifthe junctiontemperatureexceeds 160°C thedevicewillcycleinand outofthermalshutdown.Ifthermalshutdown occursitisa signofinadequateheatsinkingorexcessivepower dissipationinthedevice. Figure37, shown below,providesa betterapproximationof the θJA fora givenPCB copper area.The PCB heatsinkarea consistsof 2oz. copper locatedon the bottom layerof the PCB directlyunder the HTSSOP exposed pad.The bottomcopperareaisconnectedtotheHTSSOP exposed pad by means ofa 4 x 4 arrayof 12 milthermalvias. Figure37. Thermal Resistancevs PCB Area Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM20133 LM20133Q

L VOUT LM20133 C IN C OUT LOOP1 LOOP2 LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com PCB LAYOUT CONSIDERATIONS PC boardlayoutisan importantpartofDC-DC converterdesign.Poor boardlayoutcan disrupttheperformance ofa DC-DC converterand surroundingcircuitryby contributingtoEMI, groundbounce,and resistivevoltageloss inthetraces.These can send erroneoussignalstotheDC-DC converterresultinginpoorregulationorinstability. Good layoutcan be implementedby followinga few simpledesignrules. 1. Minimizeareaofswitchedcurrentloops.Ina buck regulatortherearetwo loopswhere currentsareswitched veryfast.The firstloopstartsfrom theinputcapacitor,totheregulatorVIN pin,totheregulatorSW pin,to the inductorthen out to the outputcapacitorand load.The second loopstartsfrom the outputcapacitor ground,totheregulatorPGND pins,totheinductorand thenouttotheload(seeFigure38).To minimize bothloopareastheinputcapacitorshouldbe placedas closeas possibletothePVIN pin.Groundingfor boththeinputand outputcapacitorshouldconsistofa smalllocalizedtopsideplanethatconnectstoPGND and thedieattachpad (DAP).The inductorshouldbe placedas closeas possibletotheSW pinand output capacitor. 2. Minimizethecopperareaoftheswitchnode.SincetheLM20133 has theSW pinson oppositesidesofthe package itisrecommended toviathesepinsdown tothebottomor internallayerwith2 to4 viason each SW pin.The SW pinsshouldbe directlyconnectedwitha tracethatrunsacrossthebottomofthepackage. To minimizeIR lossesthistraceshouldbe no smallerthat50 milswide,butno largerthan100 milswide to keep thecopperareatoa minimum. IngeneraltheSW pinsshouldnotbe connectedon thetoplayersinceit couldblockthegroundreturnpathforthepower ground.The inductorshouldbe placedas closeas possible toone oftheSW pinstofurtherminimizethecopperareaoftheswitchnode. 3. Have a singlepointgroundforalldeviceanaloggroundslocatedundertheDAP. The groundconnectionsfor the compensation,feedback,and Soft-Startcomponents shouldbe connectedtogetherthen routedto the AGND pin of the device.The AGND pin should connect to PGND under the DAP. This preventsany switchedor loadcurrentsfrom flowingintheanalogground plane.Ifnotproperlyhandledpoor grounding can resultindegradedloadregulationorerraticswitchingbehavior. 4. Minimizetracelengthto the FB pin.Since the feedbacknode can be highimpedance the tracefrom the outputresistordividerto FB pinshouldbe as shortas possible.Thisismost importantwhen highvalue resistorsareused tosettheoutputvoltage.The feedbacktraceshouldbe routedaway fromtheSW pinand inductortoavoidcontaminatingthefeedbacksignalwithswitchnoise. 5. Make inputand outputbus connectionsas wide as possible.Thisreducesany voltagedropson theinputor outputoftheconverterand can improveefficiency.Ifvoltageaccuracyattheloadisimportantmake sure feedbackvoltagesense ismade attheload.Doing so willcorrectforvoltagedropsattheloadand provide thebestoutputaccuracy. 6. Provideadequate deviceheatsinking.Use as many viasas ispossibleto connectthe DAP to the power planeheatsink.Forbestresultsuse a 4x4 viaarraywitha minimum viadiameterof12 mils.See theThermal Considerationssectiontoinsureenough copperheatsinkingarea isused tokeep thejunctiontemperature below125°C. Figure38. Schematic ofLM20133 HighlightingLayout SensitiveNodes

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(optional) SYNC LM20133,LM20133Q www.ti.com SNVS526F –OCTOBER 2007–REVISED MARCH 2013 TypicalApplicationCircuits Thissectionprovidesseveralapplicationsolutionswitha billofmaterials.Allbillofmaterialsreferencethebelow figure.The compensationforthesesolutionswere optimizedto work over a wide range of inputand output voltages;ifa fastertransientresponseisneeded reducethevalueofC C1 and calculatethenew valueforR C1 as outlineinthedesignguide. BillofMaterials(VIN = 5V,VOUT = 3.3V,IOUTMAX = 3A, FSYNC = 750kHz) Designator Description PartNumber Manufacturer Qty U1 SynchronousBuck Regulator LM20133 Texas Instruments 1 C IN 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 C OUT 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 L 2.5µH, 10m Ω MSS1038-252NL Coilcraft 1 R F 1Ω,0603 CRCW06031R0J-e3 Vishay-Dale 1 C F 100 nF,0603,X7R, 16V GRM188R71C104KA01 Murata 1 C VCC 1 µF,0603,X5R, 6.3V GRM188R60J105KA01 Murata 1 R C1 4.99kΩ,0603 CRCW06034991F-e3 Vishay-Dale 1 C C1 3.3nF,0603,X7R, 25V VJ0603Y332KXXA Vishay-Vitramon 1 C SS 33 nF,0603,X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 R FB1 31.6kΩ,0603 CRCW06033162F-e3 Vishay-Dale 1 R FB2 10.2kΩ,0603 CRCW06031022F-e3 Vishay-Dale 1 BillofMaterials(VIN = 3.3Vor 5V,VOUT = 1.2V,IOUTMAX = 3A, FSYNC = 750kHz) Designator Description PartNumber Manufacturer Qty U1 SynchronousBuck Regulator LM20133 Texas Instruments 1 C IN 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 C OUT 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 L 2.5µH, 10m Ω MSS1038-252NL Coilcraft 1 R F 1Ω,0603 CRCW06031R0J-e3 Vishay-Dale 1 C F 100 nF,0603,X7R, 16V GRM188R71C104KA01 Murata 1 C VCC 1 µF,0603,X5R, 6.3V GRM188R60J105KA01 Murata 1 R C1 2 kΩ,0603 CRCW06032001F-e3 Vishay-Dale 1 C C1 4.7nF,0603,X7R, 25V VJ0603Y472KXXA Vishay-Vitramon 1 C SS 33 nF,0603,X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 R FB1 4.99kΩ,0603 CRCW06034991F-e3 Vishay-Dale 1 R FB2 10 kΩ,0603 CRCW06031002F-e3 Vishay-Dale 1 Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM20133 LM20133Q

LM20133,LM20133Q SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com

REVISION HISTORY

Changes from RevisionE (March 2013)toRevisionF Page

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www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LM20133MH/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20133 MH LM20133MHE/NOPB ACTIVE HTSSOP PWP 16 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20133 MH LM20133MHX/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20133 MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20133MHE/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 LM20133MHX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 Pack Materials-Page 2

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