Power Management

LM20123Q

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LM20123/LM20123Q 3A, 1.5MHz PowerWise® Synchronous Buck Regulator REVISED MARCH 2013

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(optional) LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 LM20123/LM20123Q3A,1.5MHzPowerWise® SynchronousBuckRegulator Check forSamples: LM20123 1FEATURES DESCRIPTION The LM20123 isa fullfeatured1.5MHz synchronous 2• LM20123Q isAEC-Q100 Qualifiedand buck regulatorcapable of deliveringup to 3A ofManufactured on an Automotive Grade Flow continuousoutputcurrent.The currentmode control• InputVoltageRange 2.95Vto5.5V loopcan be compensated to be stablewithvirtually

AccurateCurrentLimitMinimizesInductor any type of output capacitor.For most cases, compensatingthe deviceonlyrequirestwo externalSize components,providingmaximum flexibilityand ease• 96% Efficiencywith1.5MHz Switching ofuse.The deviceisoptimizedtowork overtheinputFrequency voltagerange of2.95V to5.5V making itsuitedfora
32 m Ω IntegratedFET Switches widevarietyoflowvoltagesystems.
Startsup intoPre-BiasedLoads The devicefeaturesinternalover voltageprotection
Output VoltageTracking (OVP) and over currentprotection(OCP) circuitsfor increasedsystem reliability.A precisionenable pin• Peak CurrentMode Control and integratedUVLO allowstheturnon ofthedevice• AdjustableOutput VoltageDown to0.8V to be tightlycontrolledand sequenced. Start-up
AdjustableSoft-StartwithExternalCapacitor inrushcurrentsare limitedby bothan internallyfixed and externallyadjustableSoft-Startcircuit.Fault• PrecisionEnable Pin withHysteresis detectionand supplysequencingispossiblewiththe• IntegratedOVP, UVLO, Power Good and integratedpower good circuit.Thermal Shutdown The LM20123 isdesignedto work wellin multi-rail• HTSSOP (16-Pins)Exposed Pad Package power supplyarchitectures.The outputvoltageofthe devicecan be configuredtotracka highervoltagerailAPPLICATIONS usingtheSS/TRK pin.IftheoutputoftheLM20123 is
Simple toDesign,High EfficiencyPointof pre-biasedatstartupitwillnotsinkcurrenttopullthe Load Regulationfrom a 5V or 3.3VBus outputlow untilthe internalsoft-startramp exceeds thevoltageatthefeedbackpin.• High Performance DSPs, FPGAs, ASICs and Microprocessors The LM20123 is offeredin a 16-pin HTSSOP package withan exposed pad thatcan be solderedto• Broadband, Networking and Optical thePCB, eliminatingtheneed forbulkyheatsinks.Communications Infrastructure TypicalApplicationCircuit Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. Connection Diagram Top View See Package Number PWP0016A PIN DESCRIPTIONS Pin # Name Description 1 SS/TRK Soft-StartorTrackingcontrolinput.An internal5 µA currentsourcechargesan externalcapacitortosetthe Soft-Startramp rate.Ifdrivenby a externalsourcelessthan800 mV, thispinoverridestheinternalreference thatsetstheoutputvoltage.Ifleftopen,an internal1ms Soft-Startramp isactivated. 2 FB Feedback inputtotheerroramplifierfromtheregulatedoutput.Thispinisconnectedtotheinvertinginputof theinternaltransconductanceerroramplifier.An 800 mV referenceconnectedtothenon-invertinginputofthe erroramplifiersetstheclosedloopregulationvoltageattheFB pin. 3 PGOOD Power good outputsignal.Open drainoutputindicatingtheoutputvoltageisregulatingwithintolerance.A pull- up resistorof10 kΩ to100 kΩ isrecommend formost applications. 4 COMP Externalcompensationpin.Connecta resistorand capacitortothispintocompensate thedevice. 5,16 NC These pinsmust be connectedtoGND toensureproperoperation. 6,7 PVIN Inputvoltagetothepower switchesinsidethedevice.These pinsshouldbe connectedtogetheratthedevice. A lowESR capacitorshouldbe placednearthesepinstostabilizetheinputvoltage. 8,9 SW Switchpin.The PWM outputoftheinternalpower switches. 10,11 PGND Power groundpinfortheinternalpower switches. 12 EN Precisionenableinputforthedevice.An externalvoltagedividercan be used tosetthedeviceturn-on threshold.Ifnotused theEN pinshouldbe connectedtoPVIN. 13 VCC Internal2.7Vsub-regulator.Thispinshouldbe bypassedwitha 1 µF ceramiccapacitor. 14 AVIN Analoginputsupplythatgeneratestheinternalbias.Must be connectedtoVIN througha lowpass RC filter. 15 AGND Quietanaloggroundfortheinternalbiascircuitry. EP Exposed Pad Exposed metalpad on theundersideofthepackage witha weak electricalconnectiontoground.Itis recommended toconnectthispad tothePC boardgroundplaneinordertoimproveheatdissipation.

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www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) VoltagesfromtheindicatedpinstoGND AVIN,PVIN,EN, PGOOD, SS/TRK, COMP, FB, SW -0.3Vto+6V StorageTemperature -65°C to150°C JunctionTemperature 150°C Power Dissipation(2) 2.6W Lead Temperature(Soldering,10 sec) 260°C Minimum ESD Rating(3) ±2kV (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notspecificperformancelimits.Forspecificationsand testconditions,see the ElectricalCharacteristics. (2) The maximum allowablepower dissipationisa functionofthemaximum junctiontemperature,TJ_MAX ,thejunctions-to-ambientthermal resistance,θJA,and theambienttemperature,TA.The maximum allowablepower dissipationatany ambienttemperatureiscalculated using:PD_MAX = (TJ_MAX – TA)/θJA.The maximum power dissipationsof2.6W isdeterminedusingTA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. (3) The human body model isa 100 pF capacitordischargedthrougha 1.5kΩ resistortoeach pin. OPERATING RATINGS PVIN,AVIN toGND 2.95Vto5.5V JunctionTemperature −40°C to+ 125°C Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM20123

SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com

ELECTRICAL CHARACTERISTICS

Unlessotherwisestated,thefollowingconditionsapply:AVIN = PVIN = VIN = 5V.LimitsinstandardtypeareforTJ = 25°C only,limitsinboldfacetypeapplyoverthejunctiontemperature(TJ)rangeof-40°C to+125°C. Minimum and Maximum limits arespecifedby test,design,orstatisticalcorrelation.Typicalvaluesrepresentthemost likelyparametricnorm atTJ = 25°C, and areprovidedforreferencepurposesonly. Symbol Parameter Conditions Min Typ Max Unit ΔVOUT /ΔIOUT Load Regulation IOUT = 100 mA to3A 0.08 %/A ICL SwitchCurrentLimitThreshold VIN = 3.3V 4.3 4.8 5.3 A R DS_ON High-SideSwitchOn Resistance ISW = 3.5A 36 55 m Ω R DS_ON Low-SideSwitchOn Resistance ISW = 3.5A 32 52 m Ω IQ OperatingQuiescentCurrent Non-switching,VFB = VCOMP 3.5 6 mA ISD Shutdown Quiescentcurrent VEN = 0V 90 180 µA VUVLO VIN Under VoltageLockout RisingVIN 2.45 2.7 2.95 V VUVLO_HYS VIN Under VoltageLockoutHysteresis FallingVIN 45 100 mV VVCC VCC Voltage IVCC = 0 µA 2.45 2.7 2.95 V ISS Soft-StartPinSourceCurrent VSS/TRK = 0V 2 4.5 7 µA VTRACK SS/TRK Accuracy,VSS -VFB VSS/TRK = 0.4V -10 3 15 mV Oscillator FOSC OscillatorFrequency 1350 1500 1650 kHz DC MAX Maximum DutyCycle ILOAD = 0A 85 % TON_TIME Minimum On Time 100 ns TCL_BLANK CurrentSense BlankingTime AfterRisingVSW 80 ns ErrorAmplifierand Modulator IFB Feedback pinbiascurrent VFB = 0.8V 1 100 nA ICOMP_SRC COMP OutputSourceCurrent VFB = VCOMP = 0.6V 80 100 µA ICOMP_SNK COMP OutputSinkCurrent VFB = 1.0V,VCOMP = 0.6V 80 100 µA gm ErrorAmplifierTransconductance ICOMP = ± 50 µA 450 510 600 µmho AVOL ErrorAmplifierVoltageGain 2000 V/V Power Good VOVP Over VoltageProtectionRisingThreshold WithrespecttoVFB 105 108 111 % VOVP_HYS Over VoltageProtectionHysteresis 2 3 % VPGTH PGOOD RisingThreshold WithrespecttoVFB 92 94 96 % VPGHYS PGOOD FallingHysteresis 2 3 % TPGOOD PGOOD deglitchtime 16 µs IOL PGOOD Low SinkCurrent VPGOOD = 0.4V 0.6 1 mA IOH PGOOD HighLeakage Current VPGOOD = 5V 5 100 nA Logic VIH_EN EN PinTurnon Threshold VEN Rising 1.08 1.18 1.28 V VEN_HYS EN PinHysteresis 66 mV Thermal Shutdown TSD ThermalShutdown 160 °C TSD_HYS ThermalShutdown Hysteresis 10 °C Thermal Resistance θJA JunctiontoAmbient 38 °C/W

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www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. Efficiencyvs. Efficiencyvs. Load Current(VIN = 5V) Load Current(VIN = 3.3V) Figure1. Figure2. High-SideFET resistance Low-Side FET resistance vs.Temperature vs.Temperature Figure3. Figure4. ErrorAmplifierGain vs.Frequency LineRegulation Figure5. Figure6. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM20123

SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. Feedback Pin Voltage Load Regulation vs.Temperature Figure7. Figure8. SwitchingFrequency QuiescentCurrentvs. vs.Temperature VIN (NotSwitching) Figure9. Figure10. Shutdown Current Enable Threshold vs.Temperature vs.Temperature Figure11. Figure12.

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www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. UVLO Threshold Peak CurrentLimit vs.Temperature vs.Temperature Figure13. Figure14. Peak CurrentLimitvs.VOUT Peak CurrentLimitvs.VIN Figure15. Figure16. Load TransientResponse LineTransientResponse Figure17. Figure18. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM20123

SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified:C IN = C OUT = 100 µF,L = 1.0µH (CoilcraftMSS1038), VIN = 5V,VOUT = 1.2V,R LOAD = 1.2Ω,TA = 25°C forefficiencycurves,loopgainplotsand waveforms,and TJ = 25°C forallothers. Start-Up(Soft-Start) Start-Up(Tracking) Figure19. Figure20. Power Down ShortCircuitInputCurrentvs VIN Figure21. Figure22. VPGOOD vs.IPGOOD Figure23.

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4.8A COMP CONTROL LOGIC CURRENT LIMIT OVERVOLTAGE UNDERVOLTAGE ERROR AMP PWM COMPARATOR SS/TRK PGOOD +2.7V REGULATOR PVIN PVIN THERMAL PROTECTION PGND SW AVIN CURRENT SENSE VCC 1.18V UVLO 2.7V AGND OSCILLATOR 752 mV 864 mV PG-L PG-L 2.7V 5 PA gm = 510 Pmho 800 mV DISCHARGE DISCHARGE SLOPE COMP DIODE EMULATION VREF+ FB EN (50 Ps) PVIN LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 BLOCK DIAGRAM Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM20123

SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com OPERATION DESCRIPTION GENERAL The LM20123 switchingregulatorfeaturesallof the functionsnecessaryto implementan efficientlow voltage buck regulatorusing a minimum number of externalcomponents. This easy to use regulatorfeaturestwo integratedswitchesand iscapableofsupplyingup to3A ofcontinuousoutputcurrent.The regulatorutilizespeak currentmode controlwithnonlinearslopecompensationto optimizestabilityand transientresponseover the entireoutputvoltagerange.Peak currentmode controlalsoprovidesinherentlinefeed-forward,cycle-by-cycle currentlimitingand easy loopcompensation.The fixed1.5MHz operatingfrequencyminimizestheinductorsize whilestillachievingefficienciesup to96%. The precisioninternalvoltagereferenceallowstheoutputtobe setas low as 0.8V.Faultprotectionfeaturesinclude:currentlimiting,thermalshutdown,over voltageprotection,and shutdown capability.The deviceisavailableinthe HTSSOP 16-Pinpackage featuringan exposed pad to aid thermaldissipation.The LM20123 can be used innumerous applicationstoefficientlystep-downfrom a 5V or 3.3Vbus.The typicalapplicationcircuitfortheLM20123 isshown inFigure25 inthedesignguide. PRECISION ENABLE The enable(EN) pinallowstheoutputofthedevicetobe enabledor disabledwithan externalcontrolsignal. Thispinisa precisionanaloginputthatenablesthedevicewhen thevoltageexceeds1.18V(typical).The EN pin has 66 mV ofhysteresisand willdisabletheoutputwhen theenablevoltagefallsbelow 1.11V (typical).IftheEN pinisnotused,itshouldbe connectedtoVIN.Sincetheenablepinhas a preciseturnon thresholditcan be used alongwithan externalresistordividernetworkfromVIN toconfigurethedevicetoturnon ata preciseinput voltage.The precisionenablecircuitrywillremainactiveeven when thedeviceisdisabled. PEAK CURRENT MODE CONTROL In most cases,the peak currentmode controlarchitectureused in the LM20123 onlyrequirestwo external components toachievea stabledesign.The compensationcan be selectedtoaccommodate any capacitortype or value.The externalcompensationalsoallowsthe user to set the crossoverfrequencyand optimizethe transientperformanceofthedevice. For dutycyclesabove 50% allcurrentmode controlbuck convertersrequiretheadditionofan artificialramp to avoidsub-harmonicoscillation.Thisartificiallinearramp iscommonly referredtoas slopecompensation.What makes theLM20123 uniqueistheamount ofslopecompensationwillchange dependingon theoutputvoltage. When operatingathighoutputvoltagesthedevicewillhave more slopecompensationthanwhen operatingat loweroutputvoltages.ThisisaccomplishedintheLM20123 by usinga non-linearparabolicramp fortheslope compensation.The parabolicslopecompensationoftheLM20123 ismuch betterthanthetraditionallinearslope compensationbecause itoptimizesthestabilityofthedeviceovertheentireoutputvoltagerange. CURRENT LIMIT The precisecurrentlimitof the LM20123 is set at the factoryto be within10% over the entireoperating temperaturerange.Thisenablesthedevicetooperatewithsmallerinductorsthathave lowersaturationcurrents. When thepeak inductorcurrentreachesthecurrentlimitthreshold,an overcurrenteventistriggeredand the internalhigh-sideFET turnsoffand thelow-sideFET turnson allowinginductorcurrenttoramp down untilthe nextswitchingcycle.For each sequentialover-currentevent,the referencevoltageisdecremented and PWM pulsesare skippedresultingina currentlimitthatdoes notaggressivelyfoldback forbriefover-currentevents, whileatthesame timeprovidingfrequencyand voltagefoldbackprotectionduringhardshortcircuitconditions. SOFT-START AND VOLTAGE TRACKING The SS/TRK pinisa dualfunctionpinthatcan be used to setthe startup timeor trackan externalvoltage source.The startup orSoft-Starttimecan be adjustedby connectinga capacitorfromtheSS/TRK pintoground. The Soft-Startfeatureallowsthe regulatoroutputto graduallyreach the steady stateoperatingpoint,thus reducingstresseson theinputsupplyand controllingstartup current.Ifno Soft-Startcapacitorisused thedevice defaultstotheinternalSoft-Startcircuitryresultingina startup timeofapproximately1 ms. For applicationsthat requirea monotonicstartup or utilizethe PGOOD pin,an externalSoft-Startcapacitorisrecommended. The SS/TRK pincan alsobe settotrackan externalvoltagesource.The trackingbehaviorcan be adjustedby two externalresistorsconnectedtotheSS/TRK pinas shown inFigure30 inthedesignguide.

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IBOUNDARY = (VIN ± VOUT ) x D 2 x L x fSW LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 PRE-BIAS START UP CAPABILITY The LM20123 isina pre-biasedstatewhen thedevicestartsup withan outputvoltagegreaterthanzero.This oftenoccurs in many multi-railapplicationssuch as when powering an FPGA, ASIC, or DSP. In these applicationsthe outputcan be pre-biasedthroughparasiticconductionpathsfrom one supplyrailto another. Even though the LM20123 isa synchronousconverteritwillnot pullthe outputlow when a prebiascondition exists.DuringstartuptheLM20123 willnotsinkcurrentuntiltheSoft-Startvoltageexceedsthevoltageon theFB pin.Sincethedevicecan notsinkcurrentitprotectstheloadfromdamage thatmightotherwiseoccurifcurrent isconductedthroughtheparasiticpathsoftheload. POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20123 has builtinunderand overvoltagecomparatorsthatcontrolthepower switches.Whenever there isan excursioninoutputvoltageabove thesetOVP threshold,thepartwillterminatethepresenton-pulse,turn on thelow sideFET, and pullthePGOOD pinlow.The low sideFET willremainon untileithertheFB voltage fallsback intoregulationor thezerocrossdetectionistriggeredwhich inturntri-statestheFETs. Iftheoutput reachesthe UVP thresholdthe partwillcontinueswitchingand the PGOOD pinwillbe assertedand go low. TypicalvaluesforthePGOOD resistorareon theorderof100 kΩ orless.To avoidfalsetrippingduringtransient glitchesthePGOOD pinhas 16 µs ofbuiltindeglitchtimetobothrisingand fallingedges. UVLO The LM20123 has a built-inunder-voltagelockoutprotectioncircuitthatkeeps thedevicefromswitchinguntilthe inputvoltagereaches2.7V (typical).The UVLO thresholdhas 45 mV ofhysteresisthatkeeps thedevicefrom respondingtopower-onglitchesduringstartup.Ifdesired,theturn-onpointofthesupplycan be changed by usingthe precisionenablepinand a resistordividernetworkconnectedto VIN as shown inFigure29 inthe designguide. THERMAL PROTECTION Internalthermalshutdown circuitryisprovidedto protectthe integratedcircuitinthe eventthatthe maximum junctiontemperatureisexceeded.When activated,typicallyat 160°C, the LM20123 tri-statesthe power FETs and resetssoftstart.Afterthejunctioncoolstoapproximately150°C, thepartstartsup usingthenormalstartup routine.Thisfeatureisprovidedtopreventcatastrophicfailuresfromaccidentaldeviceoverheating. LIGHT LOAD OPERATION The LM20123 offersincreasedefficiencywhen operatingatlightloads.Whenever theloadcurrentisreducedto a pointwhere thepeak topeak inductorripplecurrentisgreaterthantwo timestheloadcurrent,thepartwill enterthediodeemulationmode preventingsignificantnegativeinductorcurrent.The pointatwhichthisoccursis thecriticalconductionboundaryand can be calculatedby thefollowingequation: (1) Several diagrams are shown in Figure 24 illustratingcontinuousconductionmode (CCM), discontinuous conductionmode, and theboundarycondition. Itcan be seen thatindiodeemulationmode, whenever the inductorcurrentreacheszero the SW node will become highimpedance.Ringingwilloccuron thispinas a resultoftheLC tankcircuitformedby theinductor and theparasiticcapacitanceatthenode.Ifthisringingisofconcernan additionalRC snubbercircuitcan be added fromtheswitchnode toground. Atverylightloads,usuallybelow100 mA, severalpulsesmay be skippedinbetween switchingcycles,effectively reducingtheswitchingfrequencyand furtherimprovinglight-loadefficiency. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM20123

Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Time (s) Time (s) Time (s) Discontinuous Conduction Mode (DCM) DCM - CCM Boundary Continuous Conduction Mode (CCM) Continuous Conduction Mode (CCM) Switchnode Voltage Switchnode VoltageInductor CurrentInductor CurrentInductor Current VIN IAVERAGE IAVERAGE VIN LM20123 SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com Figure24. Modes ofOperationforLM20123 Design Guide Thissectionwalksthedesignerthroughthestepsnecessarytoselecttheexternalcomponents tobuilda fully functionalpower supply.As withany DC-DC converternumerous trade-offsare possibletooptimizethedesign forefficiency,size,orperformance.These willbe takenintoaccountand highlightedthroughoutthisdiscussion. To facilitatecomponent selectiondiscussionsthecircuitshown inFigure25 below may be used as a reference. Unlessotherwiseindicatedallformulasassume unitsofamps (A)forcurrent,farads(F)forcapacitance,henries (H)forinductanceand volts(V)forvoltages.

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IL AVG = IOUT 'IL Time Time IL VSW LMIN = (VIN - VOUT ) x D 'iL x fSW D = VOUT VIN C IN PVIN SW GND FB PGOOD R FB1 R FB2 C OUT EN C SS SS/TRK AVIN C F C C1 COMP R C1 VIN LM20123 L R F VCC C VCC VOUT PGND VIN R PG VPG LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 Figure25. TypicalApplicationCircuit The firstequationtocalculateforany buck converterisduty-cycle.Ignoringconductionlossesassociatedwith theFETs and parasiticresistancesitcan be approximatedby: (2) INDUCTOR SELECTION (L) The inductorvalueisdeterminedbased on theoperatingfrequency,loadcurrent,ripplecurrent,and dutycycle. The inductorselectedshouldhave a saturationcurrentratinggreaterthanthepeak currentlimitofthedevice. Keep inmind thespecifiedcurrentlimitdoes notaccountfordelayofthecurrentlimitcomparator,thereforethe currentlimitintheapplicationmay be higherthanthespecifiedvalue.To optimizetheperformanceand prevent thedevicefrom enteringcurrentlimitatmaximum load,theinductanceistypicallyselectedsuch thattheripple current,ΔiL, islessthan 30% of the ratedoutputcurrent.Figure26, shown below illustratesthe switchand inductorripplecurrentwaveforms.Once theinputvoltage,outputvoltage,operatingfrequency,and desiredripple currentareknown,theminimum valuefortheinductorcan be calculatedby theformulashown below: (3) Figure26. Switch and InductorCurrentWaveforms Ifneeded,slightlysmallervalueinductorscan be used,however,thepeak inductorcurrent,IOUT + ΔiL/2,should be keptbelow thepeak currentlimitofthedevice.Ingeneral,theinductorripplecurrent,ΔiL,shouldbe greater than10% oftheratedoutputcurrenttoprovideadequatecurrentsense informationforthecurrentmode control loop.Ifthe ripplecurrentin the inductoris too low,the controlloop willnot have sufficientcurrentsense informationand can be pronetoinstability. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM20123

IIN-RMS = IOUT D(1 - D) VDROOP = 'IOUTSTEP x RESR + L x 'IOUTSTEP C OUT x (VIN - VOUT ) 'VOUT = 'iL x 1 8 x fSW x COUT R ESR + LM20123 SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com OUTPUT CAPACITOR SELECTION (COUT ) The outputcapacitor,C OUT ,filterstheinductorripplecurrentand providesa sourceofchargefortransientload conditions.A widerangeofoutputcapacitorsmay be used withtheLM20123 thatprovideexcellentperformance. The bestperformanceistypicallyobtainedusingceramic,SP, orOSCON typechemistries.Typicaltrade-offsare thatthe ceramiccapacitorprovidesextremelylow ESR to reduce the outputripplevoltageand noisespikes, whilethe SP and OSCON capacitorsprovidea largebulkcapacitanceina smallvolume fortransientloading conditions. When selectingthevaluefortheoutputcapacitorthetwo performancecharacteristicstoconsideraretheoutput voltagerippleand transientresponse.The outputvoltageripplecan be approximatedby usingtheformulashown below. where

ΔVOUT (V)istheamount ofpeak topeak voltagerippleatthepower supplyoutput
R ESR (Ω)istheseriesresistanceoftheoutputcapacitor
fSW (Hz)istheswitchingfrequency
C OUT (F)istheoutputcapacitanceused inthedesign (4) The amount ofoutputripplethatcan be toleratedisapplicationspecific;however a generalrecommendationisto keep theoutputripplelessthan1% oftheratedoutputvoltage.Keep inmind ceramiccapacitorsaresometimes preferredbecause theyhave verylow ESR; however,dependingon package and voltageratingofthecapacitor thevalueofthecapacitancecan drop significantlywithappliedvoltage.The outputcapacitorselectionwillalso affectthe outputvoltagedroop duringa loadtransient.The peak droop on the outputvoltageduringa load transientis dependent on many factors;however, an approximationof the transientdroop ignoringloop bandwidthcan be obtainedusingthefollowingequation. where
C OUT (F)istheminimum requiredoutputcapacitance
L (H)isthevalueoftheinductor
VDROOP (V)istheoutputvoltagedropignoringloopbandwidthconsiderations
ΔIOUTSTEP (A)istheloadstepchange
R ESR (Ω)istheoutputcapacitorESR
VIN (V)istheinputvoltage
VOUT (V)isthesetregulatoroutputvoltage (5) Both thetoleranceand voltagecoefficientofthecapacitorneeds tobe examined when designingfora specific outputrippleortransientdroptarget. INPUT CAPACITOR SELECTION (CIN) Good qualityinputcapacitorsarenecessarytolimittheripplevoltageattheVIN pinwhilesupplyingmost ofthe switchcurrentduringtheon-time.Ingeneralitisrecommended touse a ceramiccapacitorfortheinputas they providebotha low impedance and smallfootprint.One importantnoteistouse a good dielectricfortheceramic capacitorsuch as X5R orX7R. These providebetterovertemperatureperformanceand minimizetheDC voltage deratingthatoccurson Y5V capacitors.For many applications,a 22 µF,X5R, 6.3V inputcapacitorissufficient; however,additionalcapacitancemay be requirediftheconnectiontotheinputsupplybulkisfarfromthePVIN pins.The inputcapacitorshouldbe placedas closeas possiblePVIN and PGND pinsofthedevice. Non-ceramicinputcapacitorsshouldbe selectedforRMS currentratingand minimum ripplevoltage.A good approximationfortherequiredripplecurrentratingisgivenby therelationship: (6)

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R FB1 = - 1 VOUT 0.8 x RFB2 LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 As indicatedby theRMS ripplecurrentequation,highestrequirementforRMS currentratingoccursat50% duty cycle.For thiscase,theRMS ripplecurrentratingoftheinputcapacitorshouldbe greaterthanhalftheoutput current.For bestperformance,low ESR ceramiccapacitorsshouldbe placedinparallelwithhighercapacitance capacitorstoprovidethebestinputfilteringforthedevice. SETTING THE OUTPUT VOLTAGE (RFB1 ,R FB2 ) The resistorsR FB1 and R FB2 areselectedtosettheoutputvoltageforthedevice.Table1,shown below,provides suggestionsforR FB1 and R FB2 forcommon outputvoltages. Table1.Suggested Values forR FB1 and R FB2 R FB1 (kΩ) R FB2 (kΩ) VOUT short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 Ifdifferentoutputvoltagesarerequired,R FB2 shouldbe selectedtobe between 4.99kΩ to49.9kΩ and R FB1 can be calculatedusingtheequationbelow. (7) LOOP COMPENSATION (RC1 ,C C1 ) The purposeofloopcompensationistomeet staticand dynamic performancerequirementswhilemaintaining adequatestability.Optimalloopcompensationdepends on theoutputcapacitor,inductor,load,and thedevice itself.Table2 below givesvaluesforthecompensationnetworkthatwillresultina stablesystem when usinga 100 µF,6.3VceramicX5R outputcapacitorand 1 µH inductor. Table2.Recommended Compensation for C OUT = 100 µF and L = 1 µH VIN VOUT C C1 (nF) R C1 (kΩ) 5.00 3.30 4.7 17.86 5.00 2.50 4.7 12.93 5.00 1.80 4.7 8.81 5.00 1.50 4.7 7 5.00 1.20 4.7 3.96 5.00 0.80 4.7 1.79 3.30 2.50 4.7 12.24 3.30 1.80 4.7 11.24 3.30 1.50 4.7 7.94 3.30 1.20 4.7 6.03 3.30 0.80 4.7 1.793 Ifthedesiredsolutiondiffersfromthetableabove thelooptransferfunctionshouldbe analyzedtooptimizethe loopcompensation.The overalllooptransferfunctionistheproductofthepower stageand thefeedbacknetwork transferfunctions.For stabilitypurposes,theobjectiveistohave a loopgainslopethatis-20db/decadefroma verylow frequencytobeyond thecrossoverfrequency.Figure27,shown below,shows thetransferfunctionsfor power stage,feedback/compensationnetwork,and theresultingclosedloopsystemfortheLM20123. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM20123

R C1 = xC C1 C OUT IOUT VOUT + 22 x D VIN +1-D fSW x L COMP C C1 R C1 C C2 LM20123 (optional) AM fSW /2 0 dB FREQUENCY (Hz) GAIN (dB) Error Amp Zero, fZ(EA) Complex Double Pole, fP(MOD) Optional Error Amp Pole, fP2(EA) 0 dB 0 dB AEA + AM Error Amplifier Transfer Function Modulator and Output Filter Transfer Function Compensated Closed Loop Transfer Function AEA Error Amp Pole, fP1(EA) Complex Double Pole, fP(MOD) Output Filter Zero, fZ(FIL) Output Filter Pole, fP(FIL) fC Error Amp Pole, fP(EA) LM20123 SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com Figure27. LM20123 Loop Compensation The power stagetransferfunctionisdictatedby the modulator,outputLC filter,and load;whilethe feedback transferfunctionissetby thefeedbackresistorratio,erroramp gain,and externalcompensationnetwork. To achievea -20dB/decadeslope,the erroramplifierzero,locatedat fZ(EA), shouldpositionedto cancelthe outputfilterpole(fP(FIL)).An additionalerroramp pole,locatedatfP2(EA),can be added tocanceltheoutputfilter zeroatfZ(FIL).Cancellationoftheoutputfilterzeroisrecommended iflargervalue,non-ceramicoutputcapacitors areused. CompensationoftheLM20123 isachievedby addingan RC networkas shown inFigure28 below. Figure28. Compensation Network forLM20123 A good startingvalueforC C1 formost applicationsis4.7nF.Once thevalueofC C1 ischosen thevalueofR C1 shouldbe calculatedusingtheequationbelowtocanceltheoutputfilterpole(fP(FIL))as shown inFigure27. (8)

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tSS = 0.8V x CSS ISS C C2 = C OUT x RESR R C1 fZ(FIL) = 1 2 x S x COUT x RESR LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 A highercrossoverfrequencycan be obtained,usuallyattheexpense ofphase margin,by loweringthevalueof C C1 and recalculatingthe valueof R C1 . Likewise,increasingC C1 and recalculatingR C1 willprovideadditional phase marginata lowercrossoverfrequency.As withany attempttocompensate theLM20123 thestabilityof thesystemshouldbe verifiedfordesiredtransientdroopand settlingtime. Iftheoutputfilterzero,fZ(FIL)approachesthecrossoverfrequency(fC ),an additionalcapacitor(CC2 ) shouldbe placedat the COMP pin to ground.This capacitoradds a pole to cancelthe outputfilterzero assuringthe crossoverfrequencywilloccurbeforethedoublepoleatfSW /2degradesthephase margin.The outputfilterzero issetby theoutputcapacitorvalueand ESR as shown intheequationbelow. (9) Ifneeded,thevalueforC C2 shouldbe calculatedusingtheequationshown below. where

R ESR istheoutputcapacitorseriesresistance
R C1 isthecalculatedcompensationresistance (10) AVIN FILTERING COMPONENTS (CF and R F) To preventhighfrequencynoisespikesfromdisturbingthesensitiveanalogcircuitryconnectedtotheAVIN and AGND pins,a highfrequencyRC filterisrequiredbetween PVIN and AVIN. These components are shown in µF.The filtercapacitor,C F shouldbe placedas closetotheIC as possiblewitha directconnectionfromAVIN to AGND. A good qualityX5R orX7R ceramiccapacitorshouldbe used forC F. SUB-REGULATOR BYPASS CAPACITOR (CVCC ) The capacitorat the VCC pin providesnoise filteringand stabilityfor the internalsub-regulator.The recommended valueofC VCC shouldbe no smallerthan1 µF and no greaterthan10 µF.The capacitorshouldbe a good qualityceramicX5R or X7R capacitor.Ingeneral,a 1 µF ceramiccapacitorisrecommended formost applications. SETTING THE START UP TIME (CSS ) The additionofa capacitorconnectedfrom theSS pintoground setsthetimeatwhich theoutputvoltagewill reachthefinalregulatedvalue.LargervaluesforC SS willresultinlongerstartup times.Table3,shown below providesa listofsoftstartcapacitorsand thecorrespondingtypicalstartup times. Table3.StartUp Times forDifferentSoft-StartCapacitors StartUp Time (ms) C SS (nF) 1 none 5 33 10 68 15 100 20 120 Ifdifferentstartup timesareneeded theequationshown belowcan be used tocalculatethestartup time. (11) As shown above,thestartup timeisinfluencedby thevalueoftheSoft-StartcapacitorC SS (F)and the5 µA Soft- StartpincurrentISS (A).thatmay be foundintheelectricalcharacteristicstable. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM20123

R A = - 1VTO VIH_EN x RB EN VOUT1 R A R B LM20123 External Power Supply VOUT2 LM20123 SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com WhiletheSoft-Startcapacitorcan be sizedtomeet many startup requirements,therearelimitationstoitssize. The Soft-Starttimecan neverbe fasterthan1 ms due totheinternaldefault1 ms startup time.When thedevice isenabledthereisan approximatetimeintervalof50 µs when theSoft-Startcapacitorwillbe dischargedjust priortotheSoft-Startramp.IftheenablepinisrapidlypulsedortheSoft-Startcapacitorislargetheremay notbe enough timeforC SS tocompletelydischargeresultinginstartup timeslessthanpredicted.To aidindischarging the Soft-Startcapacitorduringlongdisableperiodsan external1 M Ω resistorfrom SS/TRK to ground can be used withoutgreatlyaffectingthestart-uptime. USING PRECISION ENABLE AND POWER GOOD The precisionenable (EN) and power good (PGOOD) pinsof the LM20123 can be used to address many sequencingrequirements.The turn-onoftheLM20123 can be controlledwiththeprecisionenablepinby using two externalresistorsas shown inFigure29. Figure29. Sequencing LM20123 withPrecisionEnable The valueforresistorR B can be selectedby the user to controlthe currentthroughthe divider.Typicallythis resistorwillbe selectedtobe between 10 kΩ and 1 M Ω.Once thevalueforR B ischosen theresistorR A can be solvedusingtheequationbelowtosetthedesiredturn-onvoltage. (12) When designingfora specificturn-onthreshold(VTO ) the toleranceon the inputsupply,enable threshold (VIH_EN ),and externalresistorsneeds tobe consideredtoinsureproperturn-onofthedevice. The LM20123 featuresan open drainpower good (PGOOD) pintosequence externalsuppliesor loadsand to providefaultdetection.Thispinrequiresan externalresistor(RPG )topullPGOOD highwhilewhen theoutputis withinthePGOOD tolerancewindow.Typicalvaluesforthisresistorrangefrom10 kΩ to100 kΩ. TRACKING AN EXTERNAL SUPPLY By usinga properlychosen resistordividernetworkconnectedtotheSS/TRK pin,as shown inFigure30,the outputof the LM20123 can be configuredto trackan externalvoltagesource to obtaina simultaneousor ratiometricstartup. Figure30. Trackingan ExternalSupply SincetheSoft-StartchargingcurrentISS isalwayspresenton theSS/TRK pin,thesizeofR2 shouldbe lessthan 10 kΩ to minimizethe errorsinthe trackingoutput.Once a valueforR2 isselectedthe valueforR1 can be calculatedusingappropriateequationinFigure31,togivethedesiredstartup.Figure31 shows two common startup sequences;thetopwaveform shows a simultaneousstartup whilethewaveform atthebottomillustrates a ratiometricstartup.

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= 1 R VOUT1 VOUT2 VEN OUT12OUT V x 8 . 0 <V ( ) x-1= 1 R 2 RV 1OUT

2 Rx-1V 2OUT

V 8 . 0 LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 Figure31. Common StartUp Sequences A simultaneousstartup ispreferredwhen poweringmost FPGAs, DSPs, or othermicroprocessors.In these systems the highervoltage,VOUT1 , usuallypowers the I/O,and the lowervoltage,VOUT2 , powers the core.A simultaneousstartup providesa more robustpower up fortheseapplicationssinceitavoidsturningon any parasiticconductionpathsthatmay existbetween thecoreand theI/Opinsoftheprocessor. The second most common power on behaviorisknown as a ratiometricstartup. Thisstartup ispreferredin applicationswhere bothsuppliesneed tobe atthefinalvalueatthesame time. SimilartotheSoft-Startfunction,thefasteststartup possibleis1ms regardlessoftherisetimeofthetracking voltage.When usingthetrackfeaturethefinalvoltageseen by theSS/TRACK pinshouldexceed 1V toprovide sufficientoverdriveand transientimmunity. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM20123

SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com THERMAL CONSIDERATIONS The thermalcharacteristicsof the LM20123 are specifiedusingthe parameterθJA, which relatesthe junction temperaturetotheambienttemperature.AlthoughthevalueofθJA isdependenton many variables,itstillcan be used toapproximatetheoperatingjunctiontemperatureofthedevice. To obtainan estimateofthedevicejunctiontemperature,one may use thefollowingrelationship: TJ = PD θJA + TA (13) and PD = PIN x (1-Efficiency)-1.1x IOUT 2 x DCR where

TJ isthejunctiontemperaturein°C
PIN istheinputpower inWatts(PIN = VIN x IIN)
θJA isthejunctiontoambientthermalresistancefortheLM20123
TA istheambienttemperaturein°C
IOUT istheoutputloadcurrent
DCR istheinductorseriesresistance (14) Itisimportanttoalwayskeep theoperatingjunctiontemperature(TJ) below 125°C forreliableoperation.Ifthe junctiontemperatureexceeds 160°C thedevicewillcycleinand outofthermalshutdown.Ifthermalshutdown occursitisa signofinadequateheatsinkingorexcessivepower dissipationinthedevice. Figure32.,shown below,providesa betterapproximationof the θJA fora givenPCB copper area.The PCB heatsinkarea consistsof 2oz. copper locatedon the bottom layerof the PCB directlyunder the HTSSOP exposed pad.The bottomcopperareaisconnectedtotheHTSSOP exposed pad by means ofa 4 x 4 arrayof 12 milthermalvias. Figure32. Thermal Resistancevs PCB Area

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L VOUT LM20123 C IN C OUT LOOP1 LOOP2 LM20123 www.ti.com SNVS524E –OCTOBER 2007–REVISED MARCH 2013 PCB LAYOUT CONSIDERATIONS PC boardlayoutisan importantpartofDC-DC converterdesign.Poor boardlayoutcan disrupttheperformance ofa DC-DC converterand surroundingcircuitryby contributingtoEMI, groundbounce,and resistivevoltageloss inthetraces.These can send erroneoussignalstotheDC-DC converterresultinginpoorregulationorinstability. Good layoutcan be implementedby followinga few simpledesignrules. 1. Minimizeareaofswitchedcurrentloops.Ina buck regulatortherearetwo loopswhere currentsareswitched veryfast.The firstloopstartsfrom theinputcapacitor,totheregulatorVIN pin,totheregulatorSW pin,to the inductorthen out to the outputcapacitorand load.The second loopstartsfrom the outputcapacitor ground,totheregulatorPGND pins,totheinductorand thenouttotheload(seeFigure33).To minimize bothloopareastheinputcapacitorshouldbe placedas closeas possibletothePVIN pin.Groundingfor boththeinputand outputcapacitorshouldconsistofa smalllocalizedtopsideplanethatconnectstoPGND and thedieattachpad (DAP).The inductorshouldbe placedas closeas possibletotheSW pinand output capacitor 2. Minimizethecopperareaoftheswitchnode.SincetheLM20123 has theSW pinson oppositesidesofthe package itisrecommended toviathesepinsdown tothebottomor internallayerwith2 to4 viason each SW pin.The SW pinsshouldbe directlyconnectedwitha tracethatrunsacrossthebottomofthepackage. To minimizeIR lossesthistraceshouldbe no smallerthat50 milswide,butno largerthan100 milswide to keep thecopperareatoa minimum. IngeneraltheSW pinsshouldnotbe connectedon thetoplayersinceit couldblockthegroundreturnpathforthepower ground.The inductorshouldbe placedas closeas possible toone oftheSW pinstofurtherminimizethecopperareaoftheswitchnode. 3. Have a singlepointgroundforalldeviceanaloggroundslocatedundertheDAP. The groundconnectionsfor the compensation,feedback,and Soft-Startcomponents shouldbe connectedtogetherthen routedto the AGND pin of the device.The AGND pin should connect to PGND under the DAP. This preventsany switchedor loadcurrentsfrom flowingintheanalogground plane.Ifnotproperlyhandledpoor grounding can resultindegradedloadregulationorerraticswitchingbehavior. 4. Minimizetracelengthto the FB pin.Since the feedbacknode can be highimpedance the tracefrom the outputresistordividerto FB pinshouldbe as shortas possible.Thisismost importantwhen highvalue resistorsareused tosettheoutputvoltage.The feedbacktraceshouldbe routedaway fromtheSW pinand inductortoavoidcontaminatingthefeedbacksignalwithswitchnoise. 5. Make inputand outputbus connectionsas wide as possible.Thisreducesany voltagedropson theinputor outputoftheconverterand can improveefficiency.Ifvoltageaccuracyattheloadisimportantmake sure feedbackvoltagesense ismade attheload.Doing so willcorrectforvoltagedropsattheloadand provide thebestoutputaccuracy. 6. Provideadequate deviceheatsinking.Use as many viasas ispossibleto connectthe DAP to the power planeheatsink.Forbestresultsuse a 4x4 viaarraywitha minimum viadiameterof12 mils.See theThermal Considerationssectiontoinsureenough copperheatsinkingarea isused tokeep thejunctiontemperature below125°C. Figure33. Schematic ofLM20123 HighlightingLayout SensitiveNodes Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM20123

(optional) LM20123 SNVS524E –OCTOBER 2007–REVISED MARCH 2013 www.ti.com TypicalApplicationCircuit Thissectionprovidesseveralapplicationsolutionswitha billofmaterials.Allbillofmaterialsreferencethebelow figure.The compensationforthesesolutionswere optimizedto work over a wide range of inputand output voltages;ifa fastertransientresponseisneeded reducethevalueofC C1 and calculatethenew valueforR C1 as outlineinthedesignguide. BillofMaterials(VIN = 5V,VOUT = 3.3V,IOUTMAX = 3A) Designator Description PartNumber Manufacturer Qty U1 SynchronousBuck Regulator LM20123 Texas Instruments 1 C IN 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 C OUT 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 L 1.2µH, 17 m Ω DO1813H-122ML Coilcraft 1 R F 1Ω,0603 CRCW06031R0J-e3 Vishay-Dale 1 C F 100 nF,0603,X7R, 16V GRM188R71C104KA01 Murata 1 C VCC 1 µF,0603,X5R, 6.3V GRM188R60J105KA01 Murata 1 R C1 8.45kΩ,0603 CRCW06038451F-e3 Vishay-Dale 1 C C1 1.5nF,0603,X7R, 25V VJ0603Y152KXXA Vishay-Vitramon 1 C SS 33 nF,0603,X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 R FB1 31.6kΩ,0603 CRCW06033162F-e3 Vishay-Dale 1 R FB2 10.2kΩ,0603 CRCW06031022F-e3 Vishay-Dale 1 BillofMaterials(VIN = 3.3Vto5V,VOUT = 1.2V,IOUTMAX = 3A) Designator Description PartNumber Manufacturer Qty U1 SynchronousBuck Regulator LM20123 Texas Instrumentsn 1 C IN 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 C OUT 47 µF,1210,X5R, 6.3V GRM32ER60J476ME20 Murata 1 L 0.68µH, 5 m Ω IHLP2525CZER0R68M01 Vishay 1 R F 1Ω,0603 CRCW06031R0J-e3 Vishay-Dale 1 C F 100 nF,0603,X7R, 16V GRM188R71C104KA01 Murata 1 C VCC 1 µF,0603,X5R, 6.3V GRM188R60J105KA01 Murata 1 R C1 5.76kΩ,0603 CRCW06035761F-e3 Vishay-Dale 1 C C1 2.2nF,0603,X7R, 25V VJ0603Y222KXXA Vishay-Vitramon 1 C SS 33 nF,0603,X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 R FB1 4.99kΩ,0603 CRCW06034991F-e3 Vishay-Dale 1 R FB2 10 kΩ,0603 CRCW06031002F-e3 Vishay-Dale 1

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REVISION HISTORY

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM20123MH/NOPB Active Production HTSSOP (PWP) | 16 92 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MH/NOPB.A Active Production HTSSOP (PWP) | 16 92 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MH/NOPB.B Active Production HTSSOP (PWP) | 16 92 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MHE/NOPB Active Production HTSSOP (PWP) | 16 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MHE/NOPB.A Active Production HTSSOP (PWP) | 16 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MHE/NOPB.B Active Production HTSSOP (PWP) | 16 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MHX/NOPB Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MHX/NOPB.A Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH LM20123MHX/NOPB.B Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 20123 MH (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1

www.ti.com 23-May-2025 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20123MHE/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 LM20123MHX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM20123MH/NOPB PWP HTSSOP 16 92 495 8 2514.6 4.06 LM20123MH/NOPB.A PWP HTSSOP 16 92 495 8 2514.6 4.06 LM20123MH/NOPB.B PWP HTSSOP 16 92 495 8 2514.6 4.06 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 14X 0.65 16X 0.30 0.19 4.55 (0.15) TYP 0 - 8 0.15 0.05 3.3 2.7 3.3 2.7 2X 1.34 MAX NOTE 5

1.2 MAX

(1) 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 5.1 4.9 B 4.5 4.3 4X 0.166 MAX NOTE 5 4214868/A 02/2017 PowerPAD HTSSOP - 1.2 mm max heightPWP0016A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may not be present. PowerPAD is a trademark of Texas Instruments. TM 1 16

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.400 THERMAL PAD

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (3.4) NOTE 9 (5) NOTE 9 (3.3) (3.3) ( 0.2) TYP VIA (1.1) TYP (1.1) TYP 4214868/A 02/2017 PowerPAD HTSSOP - 1.2 mm max heightPWP0016A PLASTIC SMALL OUTLINE SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:10X 8 9 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. TM METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-16 EXPOSED METAL SOLDER MASK DEFINED SOLDER MASK METAL UNDER SOLDER MASK OPENING EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) (3.3) (3.3) BASED ON

0.125 THICK

14X (0.65) (R0.05) TYP (5.8) 4214868/A 02/2017 PowerPAD HTSSOP - 1.2 mm max heightPWP0016A PLASTIC SMALL OUTLINE 2.79 X 2.790.175 3.01 X 3.010.15 3.3 X 3.3 (SHOWN)0.125 3.69 X 3.690.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. TM SYMM SYMM 8 9 BASED ON METAL COVERED SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information

LM20123Q specifications and overview.

Summary

LM20123/LM20123Q 3A, 1.5MHz PowerWise® Synchronous Buck Regulator REVISED MARCH 2013

Description

LM20123/LM20123Q 3A, 1.5MHz PowerWise® Synchronous Buck Regulator REVISED MARCH 2013

Source title LM20123Q Datasheet(PDF) - Texas Instruments

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