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LM1851 Ground Fault Interrupter Literature Number: SNIS158
LM1851 Ground Fault Interrupter June 1992 LM1851 Ground Fault Interrupter General Description The LM1851 is designed to provide ground fault protection for AC power outlets in consumer and industrial environ- ments. Ground fault currents greater than a presettable threshold value will trigger an external SCR-driven circuit breaker to interrupt the AC line and remove the fault condi- tion. In addition to detection of conventional hot wire to ground faults, the neutral fault condition is also detected. Full advantage of the U.S. UL943 timing specification is tak- en to insure maximum immunity to false triggering due to line noise. Special features include circuitry that rapidly re- sets the timing capacitor in the event that noise pulses intro- duce unwanted charging currents and a memory circuit that allows firing of even a sluggish breaker on either half-cycle of the line voltage when external full-wave rectification is used.
Features
Y Internal power supply shunt regulator Y Externally programmable fault current threshold Y Externally programmable fault current integration time Y Direct interface to SCR Y Operates under line reversal; both load vs line and hot vs neutral Y Detects neutral line faults Block and Connection Diagram TL/H/5177–1 Order Number LM1851M or LM1851N See NS Package Number M08A or N08E C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Office/Distributors for availability and specifications. of 80 §C/W junction to ambient for the DIP and 162 §C/W for the SO Package. Note 2: Average of 10 trials. Note 3: Required UL sensitivity tolerance is such that external trimming of LM1851 sensitivity will be necessary. Note 4: This externally applied current is in addition to the internal ‘‘output drive current’’ source. FIGURE 1. Normal Fault Sensitivity Test Circuit
Internal Schematic Diagram TL/H/5177–3
Typical Performance Characteristics Average Trip Time vs Normal Fault Current Threshold vs R SETFault Current Output Drive Current vs Pin 1 Saturation Voltage vs External Load Current, I LOutput Voltage TL/H/5177–4 Circuit Description (Refer to Block and Connection Diagram) The LM1851 operates from 26V as set by an internal shunt regulator, D3. In the absence of a fault (I fe0) the feedback path status signal (V S) is correspondingly zero. Under these conditions the capacitor discharge current, I 1, sits quies- cently at three times its threshold value, I TH, so that noise induced charge on the timing capacitor will be rapidly re- moved. When a fault current, I f, is induced in the secondary of the external sense transformer, the operational amplifier, A1, uses feedback to force a virtual ground at the input as it extracts I f. The presence of I f during either half-cycle will cause V S to go high, which in turn changes I 1 from 3I TH to ITH. Although I TH discharges the timing capacitor during both half-cycles of the line, I f only charges the capacitor during the half-cycle in which I f exits pin 2. Thus during one half-cycle I f –ITH charges the timing capacitor, while during the other half-cycle I TH discharges it. When the capacitor voltage reaches 17.5V, the latch engages and turns off Q3 permitting I 2 to drive the gate of an SCR.
A typical ground fault interrupter circuit is shown in Figure 2 . It is designed to operate on 120 V AC line voltage with 5 mA normal fault sensitivity. A full-wave rectifier bridge and a 15k/2W resistor are used to supply the DC power required by the IC. A 1 mF capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line voltage is removed from the load. At this time no fault current flows and the IC discharge current increases from I TH to 3I TH (see Circuit Description and Block Diagram). This quickly resets both the timing capacitor and the output latch. At this time the circuit breaker can be reset and the line voltage again sup- plied to the load, assuming the fault has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is basically the difference current between the hot and neutral lines, is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10 mF capacitor. The 0.0033 mF capacitor be- tween pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is determined by the timing capacitor discharging current, I TH.I TH can be calculated by: ITHe 7V RSET d2 (1) At the decision point, the average fault current just equals the threshold current, I TH. ITHeIf(rms) c0.91 (2) where I f(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that I f charges the timing capacitor only during one half-cycle, while I TH dis- charges the capacitor continuously. The factor 0.91 con- verts the rms value to an average value. Combining equa- tions (1) and (2) we have R SETe 7V If(rms)c0.91 (3) For example, to obtain 5 mA(rms) sensitivity for the circuit in Figure 2 we have: RSETe 7V 5m A c0.91 1000 e1.5M X (4) The correct value for R SET can also be determined from the characteristic curve that plots equation (3). Note that this is an approximate calculation; the exact value of R SET de- pends on the specific sense transformer used and LM1851 tolerances. Inasmuch as UL943 specifies a sensitivity ‘‘win- dow’’ of 4 mA–6 mA, provision should be made to adjust R SET on a per-product basis. Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, C t. Due to the large number of variables involved, proper selection of C t is best done empirically. The following design example, then should only be used as a guideline. Assume the goal is to meet UL943 timing requirements. Also assume that worst case timing occurs during GF1 start-up (S1 closure) with both a heavy normal fault and a 2X grounded neutral fault present. This situation is shown dia- gramatically below. TL/H/5177–5 UL943 specifies s25 ms average trip time under these con- ditions. Calculation of C t based upon charging currents due to normal fault only is as follows: s25 ms Specification b3 ms GFI turn-on time (15k and 1 mF) b8 ms Potential loss of one half-cycle due to fault current sense of half-cycles only b4 ms Time required to open a sluggish circuit breaker s10 ms Maximum integration time that could be allowed 8 ms Value of integration time that accommodates com- ponent tolerances and other variables Ct e I c T V (5) where T e integration time V e threshold voltage I e average fault current into C t I e
120 V AC(rms)
c RN RG a RN JX ä YX ä Y heavy fault portion of current generated fault current (swamps I TH) shunted around GFI c 1 turn 1000 turns J c 2 J c (0.91) (6) X ä YX äYX ä Y current C t charging rms to division of on half- average input sense cycles only conversion transformer therefore: Cte Ð# 120 500 J c 0.4 1.6a0.4 J c 1000 J c 2 J c(0.91) c0.0008 17.5 (7) Cte 0.01 mF
rents, thus allowing a larger value of C1. the best compromise between timing and noise. the full fault current, I, to enter the GFI. former during conditions of neutral fault. FIGURE 2. 120 Hz Neutral Transformer Approach
Normal Fault: An unintentional electrical path, R B, between the load terminal of the hot line and the ground, as shown by the dashed lines. TL/H/5177–7 Grounded Neutral Fault: An unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines. TL/H/5177–8 Normal Fault plus Grounded Neutral Fault: The combina- tion of the normal fault and the grounded neutral fault, as shown by the dashed lines. TL/H/5177–9
LM1851 Ground Fault Interrupter Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number LM1851N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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