LM1851

LM1851 UTC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

UTC LM1851 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 1 QW-R122-007,A GROUND FAULT INTERRUPTER

DESCRIPTION

The UTC LM1851 is designed to provide ground fault protection for AC power outlets in consumer and industrial environments. Ground fault currents greater than a presentable threshold value will trigger an external SCR-driven circuit breaker to interrupt the AC line and remove the fault condition. In addition to detection of conventional hot wire to ground faults, the neutral fault condition is also detected. Full advantage of the U.S. UL943 timing specification is taken to insure maximum immunity to false triggering due to line noise. Special features include circuitry that rapidly resets the timing capacitor in the event that noise pulses introduce unwanted charging currents and a memory circuit that allows firing of even a sluggish breaker on either half-cycle of the line voltage when external full-wave rectification is used.

FEATURES

• Internal power supply shunt regulator * Externally programmable fault current threshold * Externally programmable fault current integration time * Direct interface to SCR * Operates under line reversal; both load vs line and hot vs neutral * Detects neutral line faults DIP-8 SOP-8 PIN CONFIGURATION SENSE AMPLIFIER OUTPUT INVERTING INPUT NON-INVERTING INPUT GND Vcc TIMING CAPACITOR SENSE ITIVITY SET RESISTOR SCR Trigger 1

UTC LM1851 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 2 QW-R122-007,A INTERNAL SCHEMATIC DIAGRAM Q36Q32 Q35 R17 100k Q15 50k 390 R13 110 100kD2 10k 40k Q29 6 23 5 8 D10 Q25 R16 20k D21 Q26 D22 Q27 Q28 D23 Q23 Q24 320 Q22 Q21 Q20 D11 R14 1.2k Q1 Q2 R15 Q18 D14 Q19 D13 50k Q11 D12 Q10 Q17 D17 D18 D19 D20 D16 Q14 Q13 Q12 R10 Q16 R12 12k Q31 Q33 Q34 R11 Q30 12k

UTC LM1851 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 3 QW-R122-007,A BLOCK DIAGRAM LATCH Vcc 87 65 TIMING CAPACITOR SENSITIVITY SET RESISTOR SENSE AMPLIFIER OUTPUT 10V+ - D2Q4 D1 Q5Vs - + If Q2I2D3 I1= ITH FOR If > 0 3ITH FOR If = 0 SCR TRIGGER INVERTING INPUT NON-INVERTING INPUT GND 2 34 If ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT Supply Current Icc 19 mA Power Dissipation (Note 1) P D 1250 mW Operating Temperature Topr -40 ~ +70 °C Storage Temperature Tstg -55 ~ +150 °C Lead Soldering Temperature D I P - 8 ( 1 0 s e c . ) SOP-8 Vapor Phase (60 sec.) Infrared (15 sec.) TLED 260 215 220 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, Iss=5mA) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply Shunt Regulator Voltage Pin 8, Average Value 22 26 30 V Latch Trigger Voltage Pin 7 15 17.5 20 V Sensitivity Set Voltage Pin 8 to Pin 6 6 7 8.2 V Output Drive Current Pin 1, With Fault 0.5 1 2.4 mA Output Saturation Voltage Pin 1, Without Fault 100 240 mV Output Saturation Resistance Pin 1, Without Fault 100 Ω Output External Current Sinking Capability Pin 1, Without Fault Vpin 1 Held to 0.3V (Note 4) 2.0 5 mA Noise Integration Sink Current Ratio Pin 7, Ratio of Discharge Currents Between No Fault and Fault Conditions 2.0 2.8 3.6 μA/μA

UTC LM1851 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 5 QW-R122-007,A APPLICATION CIRCUITS A typical ground fault interrupter circuit is shown in Figure 2. It is designed to operate on 120 V AC line voltage with 5 mA normal fault sensitivity. A full-wave rectifier bridge and a 15k/2W resistor are used to supply the DC power required by the IC. A 1 μF capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line voltage is removed from the load. At this time no fault current flows and the IC discharge current increases from I TH to 3ITH ( see Circuit Description and Block Diagram ). This quickly resets both the timing capacitor and the output latch. At this time the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is basically the difference current between the hot and neutral lines, is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10 μF capacitor. The 0.0033 μF capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is determined by the timing capacitor discharging current, I TH. ITH can be calculated by: ITH= 7V RSET (1) At the decision point, the average fault current just equals the threshold current, I TH. ITH= If (rms) 2 × 0.91 ( 2 ) Where I f(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If charges the timing capacitor only during one half-cycle, while I TH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have RSET= If (rms) × 0.91 ( 3 ) For example, to obtain 5mA (rms) sensitivity for the circuit in Figure 2 we have: RSET= 5mA × 0.91 1000 =1.5MΩ ( 4 ) The correct value for R SET can also be determined from the characteristic curve that plots equation (3). Note that this is an approximate calculation; the exact value of R SET depends on the specific sense transformer used and UTC LM1851 tolerances. Inasmuch as UL943 specifies a sensitivity '' window '' of 4mA ~ 6mA, provision should be made to adjust RSET on a per-product basis. Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, C t. Due to the large number of variables involved, proper selection of C t is best done empirically. The following design example, then should only be used as a guideline. Assume the goal is to meet UL943 timing requirements. Al so assume that worst-case timing occurs during GF1 Start-up (S1 closure) with both a heavy normal fault and a 2 Ω grounded neutral fault present. This situation is shown diagrammatically below.

UTC LM1851 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 6 QW-R122-007,A S1 HOT LINE NEUTRAL HOT NEUTRAL RB 500 RN 0.4(0.8) IRG 1.6 (0.2) I I GFI UL943 specifies ≤25 ms average trip time under these conditions. Calculation of Ct based upon charging currents due to normal fault only is as follows: ≤25 ms Specification -3 ms GFI turn-on time (15k and 1μF) -8 ms Potential loss of one half-cycle due to fault current sense of half-cycles only -4 ms Time required to open a sluggish circuit breaker ≤10 ms Maximum integration time that could be allowed 8 ms Value of integration time that accommodates component tolerances and other variables Ct= 1 × T V ( 5 ) Where T=integration time V=threshold voltage I=average fault current into C t I = 120VAC(rms) RB × RN RG + RN heavy fault current generated (swamps ITH) portion of fault current shunted around GFI (6)1 turn 1000 turns 0.91×× current division of input sense transformer Ct charging on half- cycles only rms to average conversion therefore: ×120 500 0.4 1.6+0.4 1000×× 1 2 0.91× × 0.0008 17.5 Ct = Ct = 0.01μF (7)

fault currents, thus allowing a larger value of C1. For UL943 requirements, 0.015μF has been found to be the best compromise between timing and noise. allowing the full fault current, I, to enter the GFI. continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault. FIGURE 2. 120Hz Neutral Transformer Approach

UTC LM1851 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 8 QW-R122-007,A DEFINITION OF TERMS HOT NEUTRAL LINE HOT RLOADGFI RG Normal Fault An unintentional electrical path , RB, between the load terminal of the hot line and the ground, as shown by the dashed lines HOT NEUTRAL LINE HOT RLOADGFI RG RN RB NEUTRAL HOT NEUTRAL LINE HOT NEUTRALGFI RG Normal Fault plus Grounded Neutral fault: The combina- tion of the normal fault and the grounded neutral fault, as shown by the dashed lines. Grounded Neutral Fault: An unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines. NEUTRAL RB RLDAD RN

UTC LM1851 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 9 QW-R122-007,A TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT VOLTAGE@ VPIN1 (V) Average Trip Time vs Fault Current 100 1000 FAULT CURRENT (mA) 0.01 0.1 101.0 TRIP TIME (SECONDS) CIRCUIT OF FIGURE 2 UL943 NORMAL FAULT Normal Fault Current Threshold vs R SET 100FAULT CURRENT ON LINE (mA(rms)) 100k 1M 10M RSET (Ω) RSET= 7V If (rms)*×(0.91) SENSE TRANSF0RMER 1000:1 Output Drive Current vs Output Voltage 600 1200 1400 OUTPUT DRIVE CURRENT@PIN 1 (μA) 0 5 3525 1000 800 400 200 10 15 20 30 A 31V 5mA 1mA 1 VPIN1 Pin 1 Saturation Voltage vs External Load Current, I L 0.1 PIN 1 SATURATION VOLTAGE (V) 0.1 1 10010 EXTERNAL LOAD CURRENT, IL (mA) 0.01 V 31V5mA 1mA 1 IL UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.