LM1823 NSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 7
Technical content
r - = National s . Nn Semiconductor ° LM1823 Video IF Amplifier/PLL Detector System General Description Features The LM1823 is a complete video IF signal processing sys- ™ Low differential gain and phase tem on a chip. It contains a §-stage gain-controlled IF ampli-_m IF and detector pin compatible with LM1822 fier, a PLL synchronous amplitude detector, self-contained — m™ Common-base IF inputs for SAW filters gated AGC, and a switchable AFC detector. The increased ig True synchronous video detector using PLL tlexibilty of the LM1823 makes it suitable for a wide variety Ecallent stability at high systom gains of television applications where high quality video or sound ® Noise-averaged gated AGC system cartier recovery is required. These include home receiver it 9 AG ies : video IFs, cable and subscription TV decoders, and paralle|_-% Uncommitted AGC comparator input Sound IF/intercarrier detector systems. Typical operating 1 Internal AGC gate generator frequencies are 38.9 MHz, 45.75 MHz, 58.75 MHz, and @ Superior small-signal detector linearity 61.25 MHz. AFC detector with adjustable output bias
9 MHz video bandwidth
§ Reverse tuner AGC output eee Test Circuit measure parameters at indicated test points ww DETECTOR INPUT 7%" iF OUTPUT & ic FLL ie . * - Ove = 2 10K Sw wo ° 1 a} fe ly fb oan nee in
3 Gales
= ¥ 2 vavto within = ° _ b Ea ry N in a 01 (7) Wm wit $43 § el Ey => Ea = im vi9.vz0 ta Ove hl TT ° ° B “ wow et eS "= [3 oa w 9 ° 0 \\ 5 in . 1b. ‘ = et CD Se] ct 6 hed } bs 23 7 ag T 1 > T1 - 50M unbal to bal 7 7 Mini-Circuits Lab TMO1-1T ‘TL/H/5222-1 u “oar #22 wire L2-4%4T on %e" form with N M182: Joo NS Peekane Nee L3 - 64T. HF core, shielded All caps in »F unless noted 3-73
8 Absolute Maximum Ratings
= If Military/Aerospace specified devices are required, Detector Input Signal, vpeT 1Vrms: please contact the National Semiconductor Sales Power Dissipation 2w pees nani for availability and specifications. Thermal Resistance, 6), 50° C/W ply Voltage, V2 1sv Junction Temperature 125°C IF Supply Current, Is COmA Operating Temperature Range O°C to 70°C AGC Gate Voltage, V14 +5V Storage Temperature Range 65°C to + 150°C Video Output Current, lig 10mA Lead Temp. (Soldering, 10 seconds) 260°C PLL Filter Current, lig 5mA Ta=25°C, Test Circuit, vip=vpeT=0, VpH=4V, Vcomp=4V, and all switches in position 0 (open) unless noted. Parameter [_conaitions min typ | Max | Unite 12V Supply Curent, I+ [vaso=67V.Voow=ev | a5 | eo | eo | ma IF Regulator Voltage, V5 [vaso=67v,Sw4Posiion’ | se | e4 | 70 | v IF input Voltage, V7, V8 [ vaso=2visw2,3,4Postont | a2 | a7 | a1 | v IF Decouple Otfset, Vé-V9 [vaso=2v.sw2,3,4restont | | o | #a0 | mv IF PeakerVohage (Max Gain V8.6 | Vaco=2v.sW2.%,4Poatoni | 23 | 30 [ a6 |v Measure V1, 1y = (12-V1)/50 IF Peaker Vohage (in Gain, V3,v4 | Vago=v.sW29,4Poattont [ss | 62 | |v Detector Input Voltage, V2B [ vaso=67v,sw1,4Postont | 4a | ao | ss |v Limiter Tank Votage,V24,V25___ | Vago=6.7V,SW1.4Postint | a¢ | 70 | 76 |v AFG Tank Voltage, V23, V26 [vaso=67v.8wi,4Posiont | 4a | ao [ 86 |v VCO Tank Voltage, V18, V20 [vaco=erv.swisPosiont | 47 | se | 67 | v AGC Syne Threshold, V17 [ sw1.2Postion,AdustVooupfortie=0 [ 98 | 40 | 42 |v AGC FiterLeakageCurentig | SWi,2,4Postiont | S| | es | na AGCFiter Charge Currents | SW1.2Posttont,Veoup=asv | 16 | 22 | 28 | ma AGC Filter Discharge Current, ig mA Measure V11, ly 4 = (12-V11)/6000 Measure V11, 114 = (12—V11)/6000 3-74
Detector AC Set-Up Procedure sw 1, 4 position 1, Vago=0V za 1. Apply vpeT= 10 mVrms, 45.75 MHz CW at the detector input. Tune L1 for maximum AC signal at pin 25, measured with a tox | 8S FET probe or through a 1 pF capacitor to prevent loading of the limiter tank. 2. Increase vper to 60 mVrms. Adjust L3 until the PLL locks, as indicated by a DC voltage at the video output pin 16. 3, With the detector locked, adjust L3 for 4.0V at pin 18. 4. Adjust Vex for maximum detector efficiency by monitoring pin 16 for a minimum DC voltage. 5. Adjust L2 for 3.0V at pin 27 (on sensitive slope of AFC curve). Ta = 25°C, Test Circuit, detector set-up as above, f = 45.75 MHz, Vagc = 6.7V, Vcomp = 4V, and all switches in position 0 (open) unless noted. Parameter [|__conaitione Twin [typ [Max | Unite IF Amplifier Gain, voyt/vir (Note 1) | ~Vago=2V, SW2, 3, 4 Position 1, dB vig = 500 Vrms Vaac for 15 dB Gain Reduction SW 2, 3, 4 Position 1, vip=2.8 mVrms, 46 v Adjust Vagc for Same vout as Gain Test Vaac for 45 dB Gain Reduction SW 2, 3, 4 Position 1, vjz=89 mVrms, v Adjust Vagc for Same vout as Gain Test Zero Carrier Level, V16 SW 1, 2, 4 Position 1, vpet=0 [ ee | 74 | os | v Detected Output Level, AV16 SW 1, 2, 4 Position 1, vpet=60 m/Vrms, 43 v i Measure Change in V16 from Zero | Carrier Test _ | Overload Output Voltage, V16 SW1,2,4Position 1, vper=600mvims_ | | 2 | 3 |v : AFC Output Voltage (OFF), V27 SW 1, 2, 4 Position 1, vpet=0 [28 | 30 | a2 | v AFC Minimum Output Voltage, V27 SW 1, 4 Position 1, vpet=60 mVrms, v
46.75 MHz
‘AFC Maximum Output Voltage, V27 SW 14, 4 Position 1, vpet=60 mVrms, 10 v
44.75 MHz
: PLL Pull-in Range, Af SW 1, 4 Position 1, vper=60 mVrms, MHz : Vary Frequency and Measure the Difference between Lock Points Note 1: The IF amplifier gain is specified with the IF output connected to a 509 measurement ‘system which results in @ 252 loaded impedance. The gain in an actual application will typically be 26 dB higher. 3-75
a Nn 2] Design Parameters not TesTED OR GUARANTEED Typical Application Circuit - [Parameter | Tye Unto Maximum System Operating Frequency 70 MHz IF Input Impedance (Differential Pin 7-8), 45 MHz 60 a \\F Output Impedance, 45 MHz 10 ka IF Gain Control Range 55 dB Detector Input Impedance, 45 MHz 2 ko Detector Output Bandwidth, —3 dB 9 MHz Detector Differential Gain (Note 2) 3 % Detector Differential Phase (Note 2) 1 deg Detector Output Harmonic Levels below 3 Vp-p Video —40 dB VCO Temperature Coatticient —150 ppm/°C Note: 2: Differential gain and phase measured with the limiter tank adjusted for minimum differential phase. Typical Application 45.75 Miz (see Application Notes) ww 0.003 ey o AFC
1 EJ OUTPUT
T" f= epookt FI + “hed is x 1 © AFC ! ee | Scee 2 ' ia on |_| + To wo use ™ ‘NETWORK A x td 10k $ verecron Ti NT] t i NPUT®) + w 5 = ™ w 10] woeo iT 3 ™ OUTPUT «70 Fn V 18 ae = sk ou 15 sad “ TL/H/5222-2 ‘SAW Filter - MuRata SAF45MC/MA_ L1-94T) #22 wire L2-4%4T ¢ 0n 3.16" form with L3-6%4T) HF core, shielded All caps in uF unless noted i H 3-76
. = Application Notes Reter to Typical Application Circuit z COMMENTS ON RF Coupling ew 8 The LM1823 is a high gain RF system which is critically S| dependent on the ground plane and positioning of the exter- nal components. For this reason, it is suggested that the J [| printed circuit layout shown in Figure 3 be strictly adhered to. The most sensitive points in the system to unwanted RF = 9 | “1 coupling are the IF input pins 6-9. There are two different signals which can cause different problems when coupling 8 “7 into the IF inputs. If the IF output is coupling to the input, it ° 5.20 can cause bandpass tilting, peaking, and in extreme cases, TUH/S222-9 oscillation. The other signal which can couple to the IF in- FIGURE 1. IF Input Stage puts is the PLL detector VCO. This VCO coupling can cause ; ; ; AFC skewing, non-symmetrical detector pull-in, and failure Both the input network to pins 7 and 8 and decoupling ca- of the detector to acquire lock at weak signal levels. These Pacitor between pin 6 and pin 9 must be as close to the input coupling problems will be most acute at maximum gain device as is physically possible to minimize RF coupling. and will decrease as the IF is gain reduced by AGC action. Pin 10-IF Ground: Pin 10 grounds the IF and AGC circuits The differential IF inputs offer a large amount of inherent in the LM1823, It is separate from the detector and chip rejection to unwanted RF coupling. Therefore, A FULLY substrate grounds to prevent internal coupling. BALANCED INPUT SOURCE IS MANDATORY. The input Pin 11-RF AGC Output: Pin 11 is connected to an open- leads must be routed together and socketless operation is collector NPN device. It begins to conduct current when the | recommended above 50 MHz. However, residual coupling voltage on the AGC filter capacitor at pin 13 exceeds the ! may still dictate the maximum IF amplifier gain which can be voltage set at the takeover pin 12 by approximately 0.6V. { taken (see Pin Descriptions). When connected to a resistor to 12V, this produces a falling PIN DESCRIPTIONS voltage at pin suitable for reverse tuner AGC inputs. Pin 1-IF Amplifier Output: Pin 1 is connected to an open- Pin 12-RF AGC Takeover Adjust: The voltage preset at pin collector NPN device. The load on pin 1 must be raturned to 12 determines when the IF stops gain reducing and the tun the 12V supply as close as possible to pin 2. The IF output er begins gain reducing as the pin 13 AGC filter capacitor ’ ba ‘ a heal voltage increases with signal level. A higher voltage at pin | | (ead mayor the eeeenown in {he [pical Applica 12 delays the RF AGC takeover until more IF gain reduction bandpass characteristic is desired, or in conjunction with a has been taken (higher signal levels), while a lower voltage sound ten " " limits the IF gain reduction before RF takeover. Pin 2-12V Supply: The LM1823 requires a nominal 12V be ene 28 is being used without a tuner, pin 12 may supply but can accept a +10% variation. Pin 2 must be RF Ply. | decoupled to a good ground as close as possible to the IC. Pn peace nee Pin 13 isa push-pull current source out- . Bi put from the comparator. The comparator compares | Pins 3, 4-IF Gain Adjustment: Pins 3 and 4 are connected the negative sync tips of noise-averaged pin 17 video with to the two emitters of the 4th IF differential amplifier such , ° { . : an internal 4V reference. Increases in signal produce a cur- i thee FE ce anes 203 by the lmpodar nee betwoon rent out of pin 13 which charges the filter capacitor, while | a ” ‘ decreases discharge the capacitor. The resulting change in | mum gain when the pins are left open. Adding an external voltage at pin 13 controls the IF and tuner gains to maintain | resistor increases the gain by the ratio of the parallel imped- the pi " i | se < ‘@ pin 17 sync tip level at 4V. An optional capacitor be- i ance to the original 13609. The pin 3 to 4 external resistor tween pin 13 and the takeover pin 12 couples the ripple | cronee yoo aay Ones the ot 2a ore atve gain ine produced by a rapidly varying signal into the takeover pin to * enhance the AGC loop response. shunt regulate Shh foo nets stomping vasistr Pin 14-AGC Gate Generator Time Constant: The AGC . - " . comparator is gated on during sync time by a pulse from an (ere jane otic decoupling from pin & to the pin 10 internal gate generator. The gate pulse which activates the 9 bs ° comparator is derived from the sync pulse in the same video Pins 6-9-IF Input and Decouple Pins: The LM1823 uses a which feeds the comparator input (see pin 17 description). 3 common-base differential input stage as shown in Figure 1. An RC time constant on pin 14 determines the slice level on Pins 7 and 8 connect directly to the emitters of the input the leading edge of the sync pulse at which the comparator devices, while pins 6 and 9 decouple the DC feedback loop is gated on. This level is approximately Veuice = 1/(2RC) in at the bases. millivolts above the sync tip, and should be set at <25% of The gain of a common-base amplifier depends inversely on the sync amplitude. Note that Vi ice only determines when the source impedance. The LM1823 is designed to operate the AGC comparator turns on, and is unrelated to the com- | | from differential impedances in the 5009 to 20002 range, parator reference. | | which is typical for surface acoustic wave (SAW) filters, Al- In the Typical Application, Vgiice= 100 mV, or 10% of a 1V i ternatively, the IF may be used with a transformer input con- sync pulse. Increasing Vs.ice improves the AGC recovery : figuration similar to that shown in the Test Circuit, as long as from step changes in signal level but increases the risk of | the required source impedance is maintained. In all cases a video interaction. When modifying the time constant, | | _ balanced source must be used. change the capacitor value only. 3-77
follower output supplying negative syne video. With no de- 2 MHz. level, representing peak white. As the input signal level in- strate along with all of the AFC and PLL detector grounds. 7 sk tween the VCO and video detector to insure proper phasing. FIGURE 2. Adjustable Recovered Video Level the detector input being fed from tho IF amplifier and the
- An internal low pass filter removes high frequency noise tuned.
when the LM1823 fs being used to recover norma eo. tion maximizes Q to provide a steep AFC output slope. In suppressed sync systems, the recovered video at pin 16 pins as shown in the Test Circuit.
the tank should always be tuned so the output is at the during signal transients to prevent overloading the detector. ‘series equivalent capacitance resonates with the coil. FIGURE 3. Printed Circult Layout (Component Side}.