LM1818

LM1818 NSC | Alldatasheet

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Features

Y Electronic record/play switching Y 85 dB power supply rejection Y Motional peak level meter circuitry Y Low noise preamplifier circuitry Y 3.5V to 18V supply operation Y Provision for external low noise input transistor Typical Applications TL/H/7894–1 FIGURE 1. Stereo Application Circuit (Left Channel Shown), V S e 15V C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 18V Package Dissipation, (Note 1) 1560 mW Storage Temperature b65§Ct o a150§C Operating Temperature 0 §Ct o a70§C Junction Temperature 150 §C Minimum Voltage on Any Pin b0.1 V DC Maximum Voltage on Pins 2 and 5 0.1 V DC Maximum Current Out of Pin 14 5 mA DC Lead Temperature (Soldering, 10 sec.) 260 §C Electrical Characteristics VCC e 6V, T A e 25§C, See Test Circuits (Figures 2 and 3) Parameter Conditions Min Typ Max Units Operating Supply Voltage Range 3.5 18 V DC Supply Current Test Circuit (Figure 2) 51 2 m A Turn-ON Time Externally Programmable 50 400 ms Playback Signal to Noise DIN Eq. (3180 and 120 ms), 20–20 kHz, RS e 0, Unweighted, V REF e 1m V 7 4 d B at 400 Hz Record Signal to Noise Flat Gain, 20–20 kHz, R S e0, ALC OFF, V REF e 1m V 6 9 d B at 1 kHz, Unweighted Fast Turn-ON Charging Current Pins 16 and 17 200 mA Record and Playback Preamplifier f e 100 Hz 100 dBOpen Loop Voltage Gain Preamplifier Input Impedance Pin 16 or Pin 17 50 k X Preamplifier Input Referred PSRR 1 kHz Ð Flat Gain 85 dB Bias Voltage on Pin 18 in Play Mode 0.5 Vor Pin 15 in Record Mode Monitor Amplifier Input Pins 11 and 12 0.5 mABias Current Monitor Amplifier Open Record or Playback, f e 100 Hz 80 dBLoop Voltage Gain Monitor Output Current Capability Pins 9 and 10, Source Current Available 400 750 mA Monitor Amplifier Output Swing R L e 10k, AC Load 1.2 1.65 Vrms THD, All Amplifiers At 1 kHz, 40 dB Closed Loop Gain 0.05 % Record-Playback Switching Time As in Test Circuit 50 ms Input ALC Range DVIN for DVOUT e 8d B 4 0 d B Input Voltage on ALC Pin for 25 mVrmsStart of ALC Action ALC Input Impedance 2k X ALC Attack Time C13 e 10 mF7 m s ALC Decay Time R17 e %, C13 e 10 mF 30 sec Meter Output Gain 100 mVrms at 1 kHz into Pin 4 800 mV DC Meter Output Current Capability 2 mA DC Note 1: For operation in ambient temperatures above 25 §C, the device must be derated based on a 150 §C maximum junction temperature and a thermal resistance of 80 §C/W junction to ambient.

FIGURE 2. General Test Circuit

FIGURE 3. Noise Test Circuit

Equivalent Schematic Diagram TL/H/7894–4 FIGURE 4

FIGURE 5. Preamplifier

FIGURE 7. Auto Level-Meter Circuit equivalent to a 3.3k resistor across the memory capacitor.

Application Hints (Continued) Anti-Pop Circuitry (Figure 8) The capacitor on pin 3 is used in a time delay system in conjunction with C13, the ALC capacitor, to suppress pops when switching between record and playback. Figure 8 illus- trates how this is done. The output amplifier, either record or playback, is shut off prior to switching and carefully rebiased after switching takes place. It is therefore required that a proper ratio is selected between the ALC capacitor and the logic input RC time constant. The ALC capacitor must be discharged to 0.7V within the time it takes the logic input capacitor to: 1) charge from V CC/2 to 0.7 V CC when switch- ing from record to playback, or 2) discharge from V CC/2 to 0.3 V CC when switching from playback to record. These times would normally be similar; however, the ALC capacitor can be charged to a different initial value depending upon the input to the ALC circuit. The maximum value to which the ALC memory capacitor will normally charge is 3.2V, therefore, the maximum time allowed for discharging C13 is given by: e (C13 c DV) e C13 (3.2V b 0.7V) 350 mA e C13 c 7.2 c 104 If C13 e 10 mF, t1 e 72 ms It is now necessary to determine the minimum value for the R/P logic capacitor. This is done by computing the time between the 2 voltage switching points using the exponen- tial equations for a single RC network. e R13 C11 In Ð VCC

0.3 V CC (

b R13 C11 In Ð VCC

0.5 V CC (

e 0.51 R13 C11 To be sure that C13 is completely discharged, let t2 l t1. R13 C11 l t1 0.51 e (72 ms) 0.51 e 141 ms If C11 e 10 mF, R13 e 15 k X R13 should be kept to a value less than 50 k X to insure that bias current existing from pin 3 does not cause an offset voltage above 200 mV. Typically this bias current is less than 3 mA. Record Playback Switch When the voltage on pin 3 of the IC is greater than 0.5 V CC, the internal record-playback switch switches into the play- back mode. During playback the record preamplifier re- mains partially biased but the input signal to this preamp does not appear at the preamplifier output. In addition, dur- ing the playback mode, the record monitor output (pin 9) is disabled and the ALC circuit operates to minimize the signal into the record preamp input. The meter circuit is operation- al in the playback as well as the record mode. Similarly, during the record mode, the playback preamp input is ig- nored and the playback monitor output is disabled. In addi- tion, a pin is available to hold one side of the record head at ground potential while sinking up to 500 mA of AC bias and record current. TL/H/7894–10 FIGURE 8A. Anti-Pop Circuit

Application Hints (Continued) TL/H/7894–11 FIGURE 8B. Waveform for Anti-Pop Circuit External Components (Refer to Figure 9 , Monaural Application Circuit) Component External Component Function Normal Range of Value R1 Used in conjunction with varying impedance of pin 5, forming a resistor divider 500 X –20 k X network to reduce input level in automatic level control circuit. C2 Forms a noise reduction system by varying bandwidth as a function of the 0.01 mF–0.5 mF changing impedance on pin 5. With a small input signal, the bandwidth is reduced by R1 and C2. As the input level increases, so does the bandwidth. C1, C3 Coupling capacitors. Because these are part of the source impedance, it is 0.5 mF–10 mF important to use the larger values to keep low frequency source impedance at a minimum. C4 Radio frequency interference roll-off capacitor 100 pF–300 pF R2 Playback response equalization. C5 and R3 form a pole in the amplifier 50 X –200 X response at 50 Hz. C5 and R4 form a zero in the response at 1.3 kHz forR3 47 k X –3.3 M X 120 ms equalization and 2.3 kHz for 70 ms equalization.R4 2k X –200 k X R5 Microphone preamplifier gain equalization 50 X –200 X R6 5k X –200 k X R7 DC feedback path. Provides a low impedance path to the negative input in 0–2 k X order to sink the 50 mA negative input amplifier current. C6, R9, R7 and C7R8 200X –5 k X provide isolation from the output so that adequate gain can be obtained at 20R9 1k X –30 k X Hz. This 2-pole technique also provides fast turn-ON settling time.C6 200 mF–1000 mF C7 0–100 mF C8 Preamplifier output to monitor amplifier input coupling 0.05 mF–1 mF C9 ALC coupling capacitor. Note that ALC input impedance is 2 k X 0.1 mF–5 mF R10 These components bias the monitor amplifier output to half supply since the 10 k X –100 k X amplifier is unity gain at DC. This allows for maximum output swing on aR11 10 k X –100 k X varying supply.R12 10 k X –100 k X C10 1 mF–100 mF

External Components (Refer to Figure 9 , Monaural Application Circuit) (Continued) Component External Component Function Normal Range of Value C11 Exponentially falling or rising signal on pin 3 determines sequencing, time 0–10 mF delay, and operational mode of the record/play anti-pop circuitry. See anti-R13 0–50 k X pop diagram. R14 R16, R14 and C12 determine monitor amplifier response in the play mode. 1k–100k R15, R14 and C12 determine monitor amplifier response in the record mode.R15 30 k X –3 M X R16 30 k X –3 M X C12 0.1 mF–20 mF C13 Determines decay response on ALC characteristic and reduces amplifier pop 5 mF–20 mF R17 100k– % C14 Determines time constant of meter driving circuitry 0.1 mF–10 mF R18 100k– % R19 Meter sensitivity adjust 10 k X –100 k X C15 Record output DC blocking capacitor 1 mF–10 mF C16 Play output DC blocking capacitor 0.1 mF–10 mF C17 Changes record output response to approximate a constant current output in 500 pF–0.1 mF conjunction with record head impedance resulting in proper recordingR21 5k X –100 k X equalizationR22 5k X –100 k X C18 Preamplifier supply decoupling capacitor. Note that large value capacitor will 0.1 mF–500 mF increase turn-ON time C19 Supply decoupling capacitor 100 mF–1000 mF C20 Decouples bias oscillator supply 10 mF–500 mF R23 Allows bias level adjustment 0–1 k X R24 Adjusts DC erase current in DC erase machines (for AC erase, see ‘‘Stereo Application Circuit,’’ Figure 1 ) L1 Optional bias trap 1 mH–30 mH C21 100 pF–2000 pF C22 Bias Roll-Off 0.001 mF–0.01 mF H1 Record/play head 100 X –500 X; 70 mH–300 mH H2 Erase head (DC type, AC optional) 10 X –300 X

Typical Applications (Continued) TOKO America, Inc.

1250 Feehanville Drive

Mount Prospect, IL 60056 TEL: (312) 297-0070 TL/H/7894–12 FIGURE 9A. Monaural Application Circuit

Typical Applications (Continued) TL/H/7894–13 TL/H/7894–14 FIGURE 9B. Level Diagram for Monaural Application Circuit

LM1818 Electronically Switched Audio Tape System Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number LM1818N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (

a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.