LM10011SD/NOPB.A

LM10011 TI | Alldatasheet

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IDAC_OUT 2 0 - 59.2 µA LM10011 VCORE 2.97V to 5.5V VID Interface R SET SET6 MODE5 DC/DC Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LM10011 SNVS822A –DECEMBER 2012–REVISED NOVEMBER 2014 LM100116/4-BitVIDProgrammableCurrentDACforPointofLoadRegulatorswith AdjustableStart-UpCurrent

1 Features 3 Description

The LM10011 is a precision, digitally programmable 1• 1.0% Output Current Accuracy (0°C to 100°C) device used to control the output voltage of a DC/DC• 1.25% Output Current Accuracy (–40°C to 125°C) converter. The LM10011 outputs a dc current

• Input Voltage Range: 2.97 V to 5.5 V proportional to a 6-bit or 4-bit input word. By connecting the IDAC_OUT pin to the feedback node• Pin Selectable VID Format (6- or 4-bit) of a regulator, the regulator output voltage can be• 16 Selectable Start-Up Currents adjusted to a desired range and resolution set by the• Precision Enable to Support Custom UVLO user. As the input word counts up, the output voltage is adjusted higher based on the values of the• SON-10 3-mm × 3-mm Footprint, 0.5-mm Pitch feedback resistors in the converter.• Footprint Compatible with the LM10010 The current from the IDAC_OUT pin on start-up is

2 Applications programmable by an external resistor to cover the

range of 0 to 56.4 µA with 4 bits of resolution. The• Broadband, Networking, and Wireless MODE pin allows programming of the device throughCommunications a 4-bit parallel VID interface or through a 6-bit

• Notebook Power Solutions interface consisting of upper and lower 3-bit VID codes. The LM10011 is specifically designed to• Portable Instruments program a wide variety of Texas Instruments DC/DC• Battery-Powered Equipment converters for VID (Voltage Identification)• Powering Digital Loads with a 6-bit or 4-bit, 4-Pin applications. VID Interface Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM10011 WSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SNVS822A –DECEMBER 2012–REVISED NOVEMBER 2014 www.ti.com Table of Contents

4 Revision History

Changes from Original (December 2012) to Revision A Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

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IDAC_OUT GND VIDS VIDC VIDB VIDA SET DAP EN MODE LM10011 www.ti.com SNVS822A –DECEMBER 2012–REVISED NOVEMBER 2014

5 Pin Configuration and Functions

GND 1 – Ground IDAC_OUT 2 O Output pin of the current DAC that connects to the feedback node of the regulator. EN 4 I Precision enable input. The LM10011 will operate when the EN pin voltage exceeds 1.34 V. MODE will set the VID operating mode. Connecting MODE to VDD will select a 4-bit parallelMODE 5 – interface. Connecting MODE to GND will select a 4-pin, 6-bit interface. A resistor connected from SET to GND will set the start-up code (current) at the IDAC_OUTSET 6 – pin. There are 16 different start-up codes to select from. VID digital input. In 6-bit mode: Bit 0 when VIDS transitions low; Bit 3 when VIDS transitionsVIDA 7 I high. In 4-bit mode: Bit 0. VID digital input. In 6-bit mode: Bit 1 when VIDS transitions low; Bit 4 when VIDS transitionsVIDB 8 I high. In 4-bit mode: Bit 1. VID digital input. In 6-bit mode: Bit 2 when VIDS transitions low; Bit 5 when VIDS transitionsVIDC 9 I high. In 4-bit mode: Bit 2. VID select line. In 6-bit mode: transition low selects lower 3 bits, transition high selects upper VIDS 10 I 3 bits and updates the IDAC_OUT current to reflect the present VID code. In 4-bit mode: Bit Die Attach Pad. Not electrically connected to device, connect to system ground plane forDAP DAP – reduced thermal resistance.

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD, EN, IDAC_OUT, MODE –0.3 6 V VIDA, VIDB, VIDC, VIDS –0.3 6 V Junction Temperature 150 °C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. (2) If Military- or Aerospace-specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM10011

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6.2 Handling Ratings

Tstg Storage temperature range –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, 2 all pins(1) V(ESD) Electrostatic discharge kV Charged device model (CDM), per JEDEC specification 1 JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD 2.97 5.5 V IDAC_OUT –0.3 VDD – 1.75 V VIDA, VIDB, VIDC, VIDS, EN, MODE –0.3 5.5 V Junction Temperature −40 125 °C Ambient Temperature −40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) DSC UNIT

10 PINS

RθJA Junction-to-ambient thermal resistance(2) 52.1 RθJC(top) Junction-to-case (top) thermal resistance(3) 30.6 RθJB Junction-to-board thermal resistance(4) 26.8 °C/W ψJT Junction-to-top characterization parameter(5) 0.9 ψJB Junction-to-board characterization parameter(6) 26.9 RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 7.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer

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6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range unless otherwise stated.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY, UVLO, AND ENABLE IQ Quiescent current VDD = 5.0 V, VEN = 2.0 V 260 300 µA IQ_FS Quiescent current, IDAC_OUT = IFS_6 VDD = 5.0 V, VEN = 2.0 V, IFS_6 382 µA IQ_DIS Quiescent current disabled VDD = 5.0 V, VEN = 0.0 V 45 65 µA VUVLO_R Undervoltage rising threshold VDD rising 2.65 2.95 V VUVLO_F Undervoltage falling threshold VDD falling 2.2 2.45 V VUVLO_HYS Hysteresis 200 mV VEN Enable rising threshold VEN rising 1.20 1.34 1.45 V VEN_HYS Enable hysteresis 50 100 180 mV IEN Enable pullup current 2 µA IDAC_OUT ACC Accuracy Measured at full scale –1.25 1.25 % ACC Accuracy Measured at full scale, 0°C to 100°C –1.0 1.0 % LSB_6 DAC step size, 6-bit mode 940 nAIFS_6 / (26 – 1) LSB_4 DAC step size, 4-bit mode 3.76 µAIFS_4 / (24 – 1) IFS_6 Full-scale output current (6-bit mode) VID[5:0] = 000000b 59.2 µA IFS_4 Full-scale output current (4-bit mode) VID[3:0] = 0000b 56.4 µA INL Integral non-linearity –1 1 LSB_6 DNL Differential non-linearity –0.25 0.25 LSB_6 OFFSET Offset current VID[5:0] = 111111b (6-bit), VID[3:0] = 1111b (4-bit) 60 nA VOUT_MAX IDAC_OUT compliance voltage VDD = 3 V, VDD-VIDAC_OUT 1.75 V START-UP SET CURRENT VSETFSR SET pin voltage FSR 1.12 1.2 1.23 V SETRES SET ADC resolution 4 bits SETRNG SET ADC current full-scale range 56.4 µA ISET SET Current 4.75 5.1 5.40 µA SET0 Start-up DAC error, code 0 RSET = 0 Ω, IDAC_OUT = 56.4 µA 0 0 LSB SET1 Start-up DAC error, code 1 RSET = 21.0 kΩ(3), IDAC_OUT = 52.7 µA 0 0 LSB SET2 Start-up DAC error, code 2 RSET = 35.7 kΩ(3), IDAC_OUT = 48.9 µA 0 0 LSB SET3 Start-up DAC error, code 3 RSET = 51.1 kΩ(3), IDAC_OUT = 45.2 µA 0 0 LSB SET4 Start-up DAC error, code 4(4) RSET = 71.5 kΩ(3), IDAC_OUT = 41.4 µA 0 1 LSB SET5 Start-up DAC error, code 5(4) RSET = 86.6 kΩ(3), IDAC_OUT = 37.7 µA 0 1 LSB SET6 Start-up DAC error, code 6(4) RSET = 105 kΩ(3), IDAC_OUT = 33.9 µA 0 1 LSB SET7 Start-up DAC error, code 7(4) RSET = 118 kΩ(3), IDAC_OUT = 30.1 µA 0 1 LSB SET8 Start-up DAC error, code 8(4) RSET = 140 kΩ(3), IDAC_OUT =26.4 µA 0 1 LSB SET9 Start-up DAC error, code 9(4) RSET = 154 kΩ(3), IDAC_OUT = 22.6 µA 0 1 LSB SET10 Start-up DAC error, code 10(4) RSET = 169 kΩ(3), IDAC_OUT = 18.8 µA 0 1 LSB SET11 Start-up DAC error, code 11(4) RSET = 182 kΩ(3), IDAC_OUT = 15.1 µA 0 1 LSB SET12 Start-up DAC error, code 12(4) RSET = 200 kΩ(3), IDAC_OUT = 11.3 µA 0 1 LSB SET13 Start-up DAC error, code 13(4) RSET = 215 kΩ(3), IDAC_OUT = 7.59 µA 0 1 LSB SET14 Start-up DAC error, code 14(4) RSET = 237 kΩ(3), IDAC_OUT = 3.80 µA 0 1 LSB SET15 Start-up DAC error, code 15 RSET = 301 kΩ(3), IDAC_OUT = 0.06 µA 0 0 LSB (1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section. (3) RSET is based on 1% E96 standard resistor values. (4) "+1" LSB implies a positive step in CODE. LSB is in reference to LSB_4. Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM10011

6 BIT MODE TIMING

4 BIT MODE TIMING

(5) For VID timing, see Figure 1. Figure 1. Timing Diagram for LM10011 Communications

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6.6 Typical Characteristics

Unless otherwise specified, the following conditions apply: TJ = 25°C, VDD = 5 V. All graphs show junction temperature. Figure 2. Supply Current Figure 3. Supply Current (EN LOW) Figure 4. Output Compliance to Positive Rail Figure 5. Gain Error Figure 6. IDAC_OUT Offset Current Figure 7. UVLO Thresholds

Unless otherwise specified, the following conditions apply: TJ = 25°C, VDD = 5 V. All graphs show junction temperature. Figure 8. Enable (EN) Threshold Figure 9. Integral Non-Linearity Figure 10. Differential Non-Linearity

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VID[3] Bandgap Core IREF 6 bit IDAC IDAC_OUT 0 /cb1 56.4 / 59.2 µA (4-bit / 6-bit) UVLO (VDD > 2.65V) PRECISION ENABLE (1.34V) VDD EN DISABLE GND Slew Limit Logic Receiver Update DAC VIDB VIDC VIDS 3 µs deglitch Logic Receiver 3 µs deglitch Logic Receiver 3 µs deglitch Logic Receiver 6 µs deglitch VID[0] D Q QR UVLO D Q QR UVLO rise fall VID[4] VID[1] D Q QR UVLO D Q QR UVLO rise fall VID[5] VID[2] D Q QR 3 µs deglitch VID Start- Up Current Set 6-BIT MODE=0 Edge- Detector VID[0] VID[1] VID[2] VID[3] 4-BIT MODE=1 MODE R SET 3 µs deglitch LM10011 www.ti.com SNVS822A –DECEMBER 2012–REVISED NOVEMBER 2014

7 Detailed Description

7.1 Overview

The LM10011 is a precision current DAC used for controlling any point of load regulator with an adjustable resistor feedback network. Four VID communication lines (VIDA, VIDB, VIDC, and VIDS) are used to write a 6-bit or 4-bit VID value. The output of the IDAC (IDAC_OUT) is used to inject a precision current into the feedback node of a regulator, thus adjusting the output voltage. With this method, it is possible to precisely control the output voltage of the regulator. An enable pin (EN) is provided to allow for a reduced quiescent current when not in use. Also, the VDD line is monitored so that an undervoltage event will shutdown the LM10011 (IDAC_OUT = 0.0 µA). The device is available in a 10-pad No-Pullback Package (SON-10). The LM10011 can be used in numerous applications with regulators from 2.97-V to 5.5-V supplies.

7.2 Functional Block Diagram

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7.3 Feature Description

current in RFB2 to regulate at the correct feedback (reference) voltage. output whether the MODE equals 0 (connected to GND) or 1 (connected to VDD), respectively. Figure 11. Output Voltage (VOUT) is Controlled Via Current Injection into the Feedback Node

7.3.1 Current DAC

adjustable resistor. This bandgap is trimmed for precision and gives excellent performance over temperature. immunity and effectively adds a small delay from the transition of a VID line to the change in IDAC_OUT current.

7.3.2 Enable Pin and UVLO

configure the device to turn on at a precise input voltage. or from a VDD UVLO event will reset the IDAC_OUT current to its start-up RSET setting.

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7.4 Device Functional Modes

Table 1 lists the functional modes of the LM10011 device. Table 1. Mode Pin Summary

7.5 Programming

7.5.1 VID Programming, 6-Bit Mode

VIDS allows for the setting of all VIDA, VIDB, and VIDC lines to change simultaneously as VIDS rises or falls.

7.5.2 VID Programming, 4-Bit Mode

reflect the value indicated at the VID data inputs. During the hold time, no other data line can be transitioned. voltage microcontroller with a maximum VIL of 0.75 V and a minimum VIH of 1.0 V.

7.5.3 Programming the Start-Up Current

the IDAC_OUT pin will take on 1 of 16 discrete values corresponding to the currents available in the 4-bit mode. start-up currents codes can be found in Table 2. Table 2. Start-Up–4-Bit Mode Currents with Corresponding RSET Values and Output Currents

Table 2. Start-Up–4-Bit Mode Currents with Corresponding RSET Values and Output Currents (continued) that the output voltage of the POL may start-up into the selected output voltage or 1 LSB higher.

7.5.4 IDAC_OUT Current Values

Table 3. IDAC_OUT Currents and Corresponding Table 3. IDAC_OUT Currents and Corresponding VID Codes (continued)

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4 VDD

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

LM10011 is a precision, digitally programmable device used for controlling the dc-dc converter output voltage. external components needed for any given application.

8.2 Typical Application

for this example is shown in Figure 12. Figure 12. 6-Bit Mode Design Example

8.2.1 Design Requirements

Table 4 lists the design parameters. Table 4. Design Parameters

8.2.2 Detailed Design Procedure

8.2.2.1 Setting the VOUT Range and LSB

VOUT, use an IDAC_OUT value of 0 µA. value (LSB = LSB_4 = 3.76 µA) in Equation 2 and full-scale current range (IDAC_OUT = 56.4 µA).

8.2.2.3 Setting the Start-Up Voltage with RSET

required IDAC_OUT value at start-up.

8.2.2.4 Example Solution

maximum VOUT of 1.1 V using Equation 1.

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the LM10011 IDAC_OUT, and the resistor values used in the circuit. output voltage for the previous example. Table 5. 6-Bit VID Codes with IDAC Current and Regulator Voltage for the Example in Figure 12. start-up IDAC_OUT current results in a start-up current of 8.36 µA. 215 kΩ selects a nominal start-up code of 13d yielding a current of 7.59 µA and start-up voltage of 1.054 V. µA and a start-up voltage of 1.081 V.

8.2.3 Application Curves

Figure 13. Output Voltage vs. Code for LM21k with LM10011

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9 Power Supply Recommendations

The LM10011 can be driven from a PWM controller VDD pin or from the VIN supply pin as shown in Figure 12. To ensure reliable operation, the LM10011 VDD input power supply must be limited to 6 V maximum.

10 Layout

10.1 Layout Guidelines

The following guidelines should be followed when designing the PC board for the LM10011:

• Place the LM10011 close to the regulator feedback pin to minimize the FB trace length.
• Place a small capacitor, CVDD, (1 nF) directly adjacent to the VDD and GND pins of the LM10011 to help minimize transients which may occur on the input supply line.
• The high-current path from the board input to the load and the return path should be parallel and close to each other to minimize loop inductance.
• The ground connections for the various components around the LM10011 should be connected directly to each other, and to the LM10011 GND pins, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high-current ground line.
• For additional information about the operation of the regulator, please consult the respective data sheet and application notes on the respective evaluation boards.

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Product Folder Links: LM10011

10.2 Layout Example

Figure 14. Typical Top Layer Layout

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11 Device and Documentation Support

11.1 Trademarks

All trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: LM10011

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM10011SD/NOPB Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L271B LM10011SD/NOPB.A Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L271B LM10011SDX/NOPB Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L271B LM10011SDX/NOPB.A Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L271B (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10011SD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 LM10011SDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0 Pack Materials-Page 2

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