LM10000 TI1 | Alldatasheet
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0.6V - 1.2V, 20A Single or Multi-Phase Controller or Switcher External Controller Slave Regulator VOUT HPM CORE APC 2 AVS PWRGD Enable CNTL_EN FLT_N EN_BIAS CONTROL VPWI VDD ADDR IAVS SPWI SCLK RESET_N AGND AGND
0 PA ± 60 PA, 7 bit
3V ± 5.5V V I/O LM10000 ASIC/FPGA VIN HG LG PGN D FB LM10000 www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 AVSSystemController Check forSamples: LM10000 1FEATURES KEY SPECIFICATIONS 23• FlexibleEnable InputstoAllow Independent • PWI 2.0Interface Enable ControlofExternalControllerand • AVS ControlforOne Output LM10000 • PrecisionEnable
- FaultInputRestoresOutput VoltageSettingto DefaultValue DESCRIPTION
- CNTL_EN Output That Enables/Disables The LM10000 is used to enable AdaptiveVoltage ExternalController Scaling(AVS) to non-AVS regulators.Itincludesa complete Slave Power Controller(SPC 2.0) to• 7-BitCurrentDAC That Can DirectlyConnect communicate to the PowerWise™ Interface(PWItotheFeedback Node ofan ExternalController 2.0),and a programmable currentoutputDAC thatand ProvideSmooth VoltageControl allowsvoltagecontrolto any regulatorutilizinga
- Programmable Slew Rate Control feedbacknode/resistorstosettheoutputvoltage. InadditiontoenablingAVS theLM10000 allowstheAPPLICATIONS system to controlpower statessuch as sleep and
- AVS-Enabled ASICs and FPGAs shutdown,and toconfigurethevoltagestepslewrate fromthePWI. TYPICAL APPLICATION CIRCUIT Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PowerWise isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com CONNECTION DIAGRAM Figure1. 14-Lead PlasticWSON PIN DESCRIPTIONS Pin No. Pad Name Type Pad Description 1 FLT_N Input Externalfaultinput.UsuallyconnectedtoPWGD outputofintegratedregulator.
2 AGND GND
3 VDD Power AnalogBiaspower input.
4 AGND GND
5 ADDR Input PWI addressselection
6 EN_BIAS Input Enableinput. 7 CONTROL Input VOUT controlinputfromsystem.Logiclevel.
8 IAVS Output CurrentDAC outputthatconnectstofeedbacknode ofintegratedregulator
9 IAVS_MIRROR Output CurrentDAC outputthatmirrorsIAVS outputcurrent
10 RESET_N Input Reset,activelow.
11 CNTL_EN Output Enablesignalthatconnectstointegratedregulator
12 VPWI Power PWI IO biaspower
13 SPWI I/O PWI Data
14 SCLK Input PWI Clock
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www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2)(3) VPWI toGND −0.2VtoVDD FLT_N, VDD, ADR, EN_BIAS, CONTROL, IAVS,IAVS_MIRROR, RESET_N, CNTL_EN, −0.2Vto6VVPWI, SPWI, SCLK toGND JunctionTemperature −45°C to+125°C StorageTemperature −45°C to+150°C SolderingInformation:See http://www.ti.com/lit/SNOA549 ESD Ratings(4) Human Body Model 2kV Machine Model 200V (1) Absolutemaximum ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Operatingratingsindicateconditionsfor whichthedeviceoperatescorrectly.OperatingRatingsdo notimplyensuredperformancelimits. (2) The power MOSFETs can runon a separate1V to14V rail(Inputvoltage,VIN).PracticallowerlimitofVIN depends on selectionofthe externalMOSFET. See theMOSFET GATE DRIVERS sectionunderApplicationInformationforfurtherdetails. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) ESD usingthehuman body model whichisa 100 pF capacitordischargedthrougha 1.5kΩ resistorintoeach pin. OPERATING RATINGS (1)(2) VDD 3.0Vto5.5V VPWI (3) 1.6Vto3.6V (1) Absolutemaximum ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Operatingratingsindicateconditionsfor whichthedeviceoperatescorrectly.OperatingRatingsdo notimplyensuredperformancelimits. (2) The power MOSFETs can runon a separate1V to14V rail(Inputvoltage,VIN).PracticallowerlimitofVIN depends on selectionofthe externalMOSFET. See theMOSFET GATE DRIVERS sectionunderApplicationInformationforfurtherdetails. (3) VPWI cannotbe higherthanVDD. THERMAL PROPERTIES Junction-to-Ambientthermalresistance 54.7°C
ELECTRICAL CHARACTERISTICS
LimitsappearinginstandardtypeapplyforTJ = 25°C. Limitsappearinginboldfacetypeapplyoverfulloperatingjunction temperaturerange(−40°C ≤ TJ ≤ +125°C. Unlessotherwisenoted,specificationsapplytotheLM10000 TypicalApplication Circuit(pg.2)with:VDD = 5.0V,C IN = 1µF. Symbol Parameter Conditions Min Typ Max Units EN_BIAS = 0V,CONTROL = 0V 1.5 10 EN_BIAS = VDD, CONTROL = VDD 315 410R0 = 0x7FIq QuiescentCurrent µA EN_BIAS = VDD, PWI SleepCommand 196 300 EN_BIAS = VDD, PWI Shutdown Command 23 75 RisingThreshold 2.65 2.75 V UVLO FallingThreshold 2.27 2.40 Hysteresis 257 mV IADDR Addresspinsourcecurrent 7.5 µA IDAC ACC Accuracy Measured atfullscale −3 3 % LSB DAC StepSize IDAC-MAX /2n (1≤ n ≤ 7) 470 nA Resolution 7 Bits FS FullScale 59.69 µA INL IntegralNon-Linearity −2 2 LSB DNL DifferentialNon-Linearity −0.5 0.5 LSB Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM10000
SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) LimitsappearinginstandardtypeapplyforTJ = 25°C. Limitsappearinginboldfacetypeapplyoverfulloperatingjunction temperaturerange(−40°C ≤ TJ ≤ +125°C. Unlessotherwisenoted,specificationsapplytotheLM10000 TypicalApplication Circuit(pg.2)with:VDD = 5.0V,C IN = 1µF. Symbol Parameter Conditions Min Typ Max Units ZE ZeroCode Error/OffsetError 57 nA LOGIC AND CONTROL INPUTS Rising 1.32 1.4 EN_BIAS TH Precisionenablethreshold V Falling 1.09 1.19 FLT_N, RESET_N −10 IIL InputCurrentLow ENBIAS, CONTROL −1 µA SPWI, SCLK −1 FLT_N, RESET_N 1 IIH InputCurrentHigh ENBIAS, CONTROL 10 µA SPWI, SCLK 5 VIL InputLow Voltage CONTROL, FLT_N, RESET_N 0.5 V VIH InputHighVoltage CONTROL, FLT_N, RESET_N 1.1 V VIL_PWI InputLow Voltage,PWI SPWI, SCLK, 1.6< VPWI < 3.6 30 % ofVPWI VIH_PWI InputHighVoltage,PWI SPWI, SCLK, 1.6< VPWI < 3.6 70 fSCLK PWI2 SCLK **DC usefulfortesting/debug 0 15M Hz LOGIC AND CONTROL OUTPUTS VOL OutputLow Level CNTL_EN, ISINK ≤ 100 µA 0.4 VDD -VOH OutputHighLevel CNTL_EN, ISOURCE ≤ 100 µA 0.4 V VPWI -VOH_PWI OutputHighLevel,PWI SPWI, ISOURCE ≤ 1mA 0.4
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IAVSCNTL_EN CONTROL EN_BIAS FLT_N RESET_N VPWI VDD Slave Power Controller (SPC 2) SPWI SCLK Ready ADDR IAVS_MIRROR UVLO 1.3V Slew Rate Control Precision Enable IDAC IDAC LM10000 www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 BLOCK DIAGRAM Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM10000
50 Ps/DIV
EN_BIAS CNTL_EN 2V/DIV CONTROL CNTL_EN 200 ns/DIV LM10000 SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS EN_BIAS toCNTL_EN Delay CONTROL toCNTL_EN Delay (CONTROL heldHIGH) (EN_BIAS heldHIGH) Figure2. Figure3. VOUT Reset by FLT_N Trigger IAVS Slew Rate Programmability Figure4. Figure5.
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www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 LM10000 PWI REGISTER MAP The PWI 2.0standarddefines32 8-bitbase registers,and up to256 8-bitextendedregisters,on each PWI slave. The tablebelow summarizes theseregistersand shows defaultregisterbitvaluesafterreset,as programmed by thefactory.The followingsub-sectionsprovideadditionaldetailson theuse ofeach individualregister. Table1.SUMMARY (1) Base Registers Register Register RegisterUsage Typ Reset DefaultValue Address Name e 7 6 5 4 3 2 1 0 0x00 R0 IAVS R/W 0* Configuredby R9 0x03 R3 R/O 0 0 0 0 1 1 1 FLT_N 0x04 R4 DeviceCapability R/O 0 0 0 0 0 0 1 0 0x09 R9 IAVS Default R/W IAVS DefaultCode 0x0A R10 Ramp Control R/W 1 0 0 1 1 1 0 0 0x0F R15 RevisionID N/A 0 0 0 0 0 0 0 0 0x1F R31 Reserved R/W - - - - - - - - Do not writeto (1) A bitwithan asterisk(*)denotesa registerbitthatisalwaysreadas a fixedvalue.Writestothesebitswillbe ignored.A bitwitha hyphen (-)denotesa bitinan unimplementedregisterlocation.A writeintounimplementedregister(s)willbe ignored.A readofan unimplementedregister(s)willproducea “No responseframe”.PleaserefertoPWI specificationversion2.0forfurtherinformation. R0 -IAVS AVS FEEDBACK CURRENT INJECTION Address 0x00 Type R/W ResetDefault 8h'7F Bit FieldName Descriptionor Comment 7 Sign Thisbitisfixedto'0'.Readingthisbitwillresultina '0'.Any datawrittenintothisbitposition usingtheRegisterWritecommand isignored. Programmed voltagevalue.Defaultvalueisinbold. CurrentData Code [6:0] Current(µA) 6:0 IAVS SourcingCurrent 7h'00 60 7h'xx LinearScaling 7h'7F 0 (default) R3 -STATUS LM10520 ADDRESS Address 0x03 Type R/O ResetDefault – Bit FieldName Descriptionor Comment 7:4 Not Used Alwaysreadback 0 3:1 Not Used Alwaysreadback 1
0 FLT_N 1:FLT_N ishigh(nofault)
0:FLT_N islow(fault) Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM10000
SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com R4 -DEVICE CAPABILITY REGISTER Address 0x04 Type R/O ResetDefault 8h'02 Bit FieldName Descriptionor Comment 7:3 Alwaysreadback 0 2:0 Alwaysreadback 010,specifyingPWI 2.0 R9 -IAVS DEFAULT REGISTER Address 0x09 Type R/W ResetDefault 8h'7F Bit FieldName Descriptionor Comment 7 Sign Alwaysreadback 0. CurrentData Code [6:0] Current(µA) 7h'00 60 6:0 IAVS Default 7h'xx LinearScaling 7h'7F 0 (Default) R10 -RAMP CONTROL Address 0x0A Type R/W ResetDefault 8h'9C Bit FieldName Descriptionor Comment
7 Ramp ControlEnable 1:Enabled
0:Disabled
6 Not Used Alwaysread0
5:3 Ramp Time StepControl Ramp Time StepControl Ramp Time Step(µs) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 6 1 0 1 8 1 1 0 12 1 1 1 16 2:0 Ramp Code StepControl Ramp Code Step RisingStep FallingStep (LSB) (LSB) 0 0 0 1 1 0 0 1 2 1 0 1 0 3 2 0 1 1 4 3 1 0 0 6 4 1 0 1 8 5 1 1 0 12 6 1 1 1 16 8
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www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 R15 -REVISION ID REGISTER Address 0x0F Type R/O ResetDefault 8h'00 Bit FieldName Descriptionor Comment 7:0 Alwaysreadback 0 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM10000
+- VOUT VFB -IRFB2 IAVS IRFB1 VRFB1 IAVSPWI LM10000 IAVS LM10000 SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com OPERATION DESCRIPTION GENERAL DESCRIPTION The LM10000 providesallthe circuitryneeded to enable most DC/DC regulatorsto work in a PowerWise® AdaptiveVoltageScaling(AVS) system.Itcommunicates viathe PowerWise Interface(PWI),and has analog outputstocontroltheoutputvoltageofa slavepower regulator.The slavepower regulatorcan be any device thatsetsitsoutputvoltagewitha feedbackresistordivider. THEORY OF OPERATION The LM10000 can be thoughtofas a D/A converter,convertingPWI communicationtoanalogoutputs.One of theoutputsisa currentDAC (IAVS),whichisconnectedtothefeedbacknode ofa slaveregulator.Therefore,all PWI Change VoltageCommands (CVC) are decoded intoa 7-bitcurrentDAC output.The impedance of the feedback node at DC appears as the top feedback resistor.This is because the controlloop of the slave regulatoreffectivelymaintainsa constantcurrent/voltageacrossthebottomfeedbackresistor,and createslow impedance attheVOUT node.Therefore,as more currentissourcedintothefeedbacknode,themore theoutput voltageisreduced.See Figure6. Figure6. Output VoltageIsControlledViacurrentInjectionIntoFeedback Node DIGITAL POWER MANAGEMENT In additionto adaptivevoltagescaling,the PWI and LM10000 enhance the slaveregulatorwithbasicdigital power management control.Thisincludescontrolofpower statessuch as SHUTDOWN, SLEEP, and ACTIVE, ON/OFF sequencing,and voltagescalingslew rate.Figure7 shows the LM10000 with availablesystem connectivityoptions.The LM10000 has a flexiblesetoflogicenablepinstoallowthesystem easy interfaceto power statesand sequencing.A logicCNTL_EN outputisprovidedtodrivetheslaveregulatorenableaccording the power stateof the LM10000. For example,ifa PWI SHUTDOWN command isissuedto LM10000, the CNTL_EN outputisimmediatelydrivento0V, whichifconnectedtotheslaveregulatorenableinput,willturnoff theoutputvoltageand entera low Iq state.A summary ofthelogicinputsand outputsisgivenisLOGIC INPUTS AND OUTPUTS table.
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VOUT = VFB x 1 + - I AVS x RFB1 R FB1 R FB2 Slave Regulator ASICVDD RTN (Non AVS) IAVS CNTL_EN SPWI SCLK AVS APC2 PWI 2.0 FB FLTN CONTROL RESETN EN_BIAS Logic inputs for Vout sequencing control LM10000 Logic output for enabling slave regulator System uC LM10000 www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 Figure7. LM10000 providesflexibledigitalpower management viamulti-masterPWI 2.0,and flexible VOUT sequencing control IAVS OUTPUT CURRENT: CONTROLLING THE OUTPUT VOLTAGE The LM10000 uses a 7-bitcurrentDAC to controlthe outputvoltageof a slavepower regulator.Since itisa currentoutput,IAVS can be connecteddirectlytothefeedbacknode oftheslavepower regulator.IAVS has a rangeof0 – 60 µA with7 bitsofresolution,ora 0.469µA LSB. A typicalconnectionoftheIAVS injectioncurrentintoa slaveregulatorisshown inFigure8.The outputvoltage VOUT isexpressedas: (1) Where VFB = theregulatedfeedbackvoltageoftheslaveregulator.ThisequationisvalidforVOUT > VFB. Figure8. IAVS InjectionCurrentIntoA SlaveRegulator Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM10000
Adjust Command (value) LM10000 SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com USING REGISTER R9 TO CHANGE THE DEFAULT OUTPUT VOLTAGE The LM10000 defaultIAVS currentissetby R9. R9 istrimmed to 0x7F, so thatIAVS = 0µA when power is appliedtoLM10000. Between power cycling,R9 can be changed so thatIAVS defaultstovaluesbetween 0 -60 µA. Thiscan be usefulforsoftwaretrimof the defaultoutputvoltageof the LM10000 controlledregulator.In orderto do this,the system must take care to writeto R9 beforeenablingthe output(theoutputcan be enabled/disabledwhilekeepingtheLM10000 logicon viatheCONTROL input).Therefore,R9 must be writtento by some system controllerthatison a differentpower domain thanthatprovidedby LM10000. Inaddition,the “INITIAL_VDD” registerintheAdvanced Power Controller(APC) must have thesame valueas R9 so thatthe APC and LM10000 defaulttothesame voltagecode. IAVS MIRROR OUTPUT CURRENT IAVS Mirrorsourcesa currentequaltoIAVS. DIGITAL SLEW RATE CONTROL The IAVS and IAVS Mirroroutputshave an adjustable,digitalslew ratecontrol.The slew ratecontrolis programmed inregisterR10. The slew rateof the outputvoltagewilleffectboth the outputand inputinrush currentneeded toscaletheoutputvoltageup or down. The amount ofoutputcurrentsourceor sinkneeded to scaletheoutputvoltageisgovernedby theequationdescribingcurrentina capacitor: iC= C x dV/dt (2) Therefore,more currentisneeded forlargervoltagesteps(dV)and forsmallersettlingtimes(dt).Thiscurrentis inadditiontotheloadcurrentthattheslaveregulatorisproviding.Itisrecommended thatthetotalcurrent(load current+ voltageslewcurrent)notexceed theslaveregulatorcurrentlimit. Figure9. DigitalSlew Rate Control PWI ADDRESS A resistorfromtheADDR pintogroundsetsthedevice'sPWI address.The devicesenses theresistanceas itis initializingfrom the shutdown state.The devicewillnot update the address untilitcyclesthroughshutdown again.Use thetablebelowtochoose theappropriateresistortoplaceformADDR pintoground. PWI Address Resistance(± 1% tolerance) 0 ≤ 40.2kΩ 1 60.4kΩ 2 80.6kΩ 3 100 kΩ 4 120 kΩ 5 140 kΩ 6 160 kΩ 7 180 kΩ
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www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 INPUTS: ENBIAS, CONTROL, FLT_N, RESET_N, SCLK, SPWI ENBIAS The ENBIAS logicinputenables the internalcircuitryof the LM10000. The LM10000 goes through an initializationprocedureupon therisingedge ofENBIAS. Initializationiscompletewithin100 µsec,afterwhichthe deviceisreadytobe used. Ifatany pointENBIAS goes low,thedeviceentersa lowIq shutdownstate. CONTROL The CONTROL logicinputallowscontrolof the CNTL_EN outputwithoutincurringdelaysassociatedwith initialization.ThissignaliseffectivelyANDed withtheinternal‘ready’signal,which ishighonce initializationis complete. The CONTROL pinleveltogglesthedevicebetween Activeand Sleepstates,and willresettheR0 register FLT_N The FLT_N logicinputresetsand holds the R0 registerwhen itsinputsignalis low.Ithas no effecton CNTL_EN. This providesa convenientway to supportautomaticfaultrecoverymodes in the slavepower regulator.When connectedtoa standardPWGD pinofa DC/DC regulator,FLT_N willresetand holdR0 as long as PWGD islow,allowingtheslaveregulatortorecoverfromthefaultby returningtothedefaultvoltage.Once FLT_N returnshigh,R0 can be writtento. RESET_N The RESET_N providesa separate,levelcontrolledlogicreset. SCLK and SPWI SCLK and SPWI provideserialPWI communication OUTPUTS: CNTL_EN, IAVS CNTL_EN The CNTL_EN outputconnectstotheslaveregulatorenablepin.CNTL_EN allowspower statecontrolviathe PWI interfaceorENBIAS/CONTROL logicinputs.For a directconnectionfromCNTL_EN totheenablepinofthe slaveregulator,the enablepinon the slaveregulatorneeds to be levelbased and activehigh(a logichigh voltageenablesthe slaveregulator).LM10000 willdriveCNTL_EN to the VDD voltageto enable the slave regulator,and to0V todisabletheslaveregulator.Inthecase thattheenable/disableon theslaveregulatorisa differentfunction(impedancebased oractivelow),extracircuitryisrequired. UVLO The LM10000 includesa UVLO circuitwithhysteresisthattriggersoffofVDD. The system designershouldbe aware ofthedifferentUVLO thresholdsofLM10000 and theslaveregulatoritiscontrolling.SinceLM10000 is controllingtheoutputoftheslaveregulator,theUVLO circuitsinboththeLM10000, and theslaveregulatorcan reacttosevereinputvoltagetransients.Thisisnormallynota problemunlesstheapplicationisoperatingvery closetotheUVLO thresholdsofthetwo devices. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM10000
CNTL_EN = 0 Low iq state Active CNTL_EN = 1 Startup CNTL_EN = 0 ENBIAS Falling Edge Sleep Cmd Wakeup Cmd (Reset R0) Shutdown CmdShutdown Cmd CONTROL = 0 CONTROL = 1 CONTROL = 1 (Reset R0) CONTROL = 0 Pin State Fault Reset and hold FLTN = 0 ENBIAS Rising Edge CONTROL = 0 RESET Cmd FLTN = 0 FLTN = 1 FLTN = 1 SLEEP CNTL_EN = 0 LM10000 SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com STATES STARTUP Duringthestartupstate,theLM10000 initializesallitsregistersand enablesitsbandgap.Thisprocesstypically takes100 µsec.CNTL_EN islowduringstartup. ACTIVE Duringtheactivestate,CNTL_EN ishigh,theIAVS DACs areenabled,and PWI registerscan be accessed. SLEEP Duringthesleepstate,CNTL_EN islow,theIAVS DACs aredisabled,and PWI registerscan be accessed. FAULT Duringthefaultstate,theIAVS currentregister(R0)isreset,afterwhichtheLM10000 automaticallyreturnstoits previousstate. SHUTDOWN Duringtheshutdown state,CNTL_EN islow,theIAVS DACs aredisabled,and most internalcircuitryisdisabled. OnlythePWI statemachine isbiasedtoallowregisteraccess. Figure10. LM10000 StateDiagram
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RESET! APC 2 V I/O System Enable Control AVS VDD RTN 0.6 ± 1.2 V 40 ± 60 A VDD ADDR R VINC VIN LM10000 www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013 APPLICATION CIRCUITS Figure11. 60A AVS solutionusing LM10000 pairedwithLM3573/4 2-Phase Controller Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM10000
RESET! APC 2 V I/O System Enable Control AVS VDD RTN 0.8V - 1.2V VDD ADDR C OUTC IN GND VIN EN FB VOUT 47 PF 6.6k13.2k LMZ10505 47 PF LM10000 SNVS643C –JUNE 2010–REVISED APRIL 2013 www.ti.com Figure12. 5A AVS solutionLM10000 pairedwithLMZ10505 Simple SwitcherModule
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www.ti.com SNVS643C –JUNE 2010–REVISED APRIL 2013
REVISION HISTORY
Changes from RevisionB (April2013)toRevisionC Page Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM10000
www.ti.com 22-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LM10000SD/NOPB ACTIVE WSON NHK 14 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 10000SD LM10000SDE/NOPB ACTIVE WSON NHK 14 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 10000SD LM10000SDX/NOPB ACTIVE WSON NHK 14 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 10000SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10000SD/NOPB WSON NHK 14 1000 210.0 185.0 35.0 LM10000SDE/NOPB WSON NHK 14 250 210.0 185.0 35.0 LM10000SDX/NOPB WSON NHK 14 4500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2
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