LIS3LV02DL_08 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Features
■ 2.16 V to 3.6 V single supply operation ■ 1.8 V compatible IOs ■ I2C/SPI digital output interfaces ■ Programmable 12 or 16 bit data representation ■ Interrupt activated by motion ■ Programmable interrupt threshold ■ Embedded self test ■ High shock survivability ■ ECOPACK® compliant (see Section 9)
Description
The LIS3LV02DL is a three axes digital output linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an I 2C/SPI serial interface. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. The LIS3LV02DL has a user selectable full scale of ±2g, ±6g and it is capable of measuring acceleration over a bandwidth of 640 Hz for all axes. The device bandwidth may be selected accordingly to the application requirements. The self-test capability allows the user to check the functioning of the device. The device may be also configured to generate an inertial wake-up/free-fall interrupt signal when a programmable acceleration threshold is crossed at least in one of the three axes. The LIS3LV02DL is available in plastic SMD package and it is specified over a temperature range extending from -40°C to +85°C. The LIS3LV02DL belongs to a family of products suitable for a variety of applications: – Free-Fall detection – Motion activated functions in portable terminals – Antitheft systems and Inertial navigation – Gaming and virtual reality input devices – Vibration monitoring and compensation LGA-16 Table 1. Device summary
8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 LGA-16 pin description
Figure 2. Pin connection Table 2. Pin description
1 RDY/INT Data ready/inertial wake-up interrupt
2 SDO SPI Serial Data Output
4 Vdd_IO Power supply for I/O pads
7 NC Internally not connected
9 GND 0 V supply
10 Reserved Either leave uncon nected or connect to Vdd_IO
11 Vdd Power supply
12 Reserved Connect to Vdd
13 Vdd Power supply
14 GND 0 V supply
15 Reserved Either leave unconnected or connect to GND
16 GND 0 V supply
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted (1)
- Typical specificat ions are not guaranteed
- Verified by wafer level test and specif ication of initial offset and sensitivity
- Zero-g level offset value after MSL3 preconditioning
- Offset can be eliminated by enabling the built-in high pass filter (HPF)
- Results of accelerated reliability tests
- Self Test output changes with the power supply. “Self test output change” is defined as OUTPUT[LSb]
- Output data reach 99% of final value after 5/OD R when enabling Self-Test mode due to device filtering
- ODRx is output data rate. Refer to Table 5 for specifications
Table 4. Mechanical characteristics @ Vdd=2.5 V, T=25 °C unless otherwise noted (1)
- Typical specificat ions are not guaranteed
- Verified by wafer level test and specif ication of initial offset and sensitivity
- Zero-g level offset value after MSL3 preconditioning
- Offset can be eliminated by enabling the built-in high pass filter (HPF)
- Results of accelerated reliability tests
- Self Test output changes with the power supply. “Self test output change” is defined as OUTPUT[LSb]
- Output data reach 99% of final value after 5/OD R when enabling Self-Test mode due to device filtering
- ODRx is output data rate. Refer to Table 5 for specifications
2.2 Electrical characteristics
Table 5. Electrical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted (1)
- Typical specificat ions are not guaranteed
- Digital filter cut-off frequency
- Time to obtain valid data after exiting Power-Down mode
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram (2)
- Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port
- When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up
Table 6. SPI Slave Timing Values
- Values are guaranteed at 8 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization
2.3.2 I 2C - Inter IC control interface
Subject to general operating conditions for Vdd and Top. Figure 4. I 2C slave timing diagram (4) Table 7. I2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production
- A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
- Cb = total capacitance of one bus line, in pF
2.4 Absolute maximum ratings
Note: Supply voltage on any pin should never exceed 6.0 V. Table 8. Absolute maximum ratings
Mechanical and electrical specifications LIS3LV02DL
2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, ±1g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensors.
2.5.2 Zero-g level
Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, 00h with 16 bit representation, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population of sensors.
2.5.3 Self test
Self Test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. The Self Test function is off when the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the self-test bit of CTRL_REG1 is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which is related to the selected full scale and depending on the Supply Voltage through the device sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3 or 4 then the sensor is working properly and the parameters of the interface chip are within the defined specification.
3 Functionality
The LIS3LV02DL is a high performance, low-power, digital output 3-axis linear accelerometer packaged in an LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I 2C/SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is up to 100fF .
3.2 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by three Σ∆ analog-to-digital converters, one for each axis, that translate the produced signal into a digital bitstream. The Σ∆ converters are coupled with dedicated reconstruction filters which remove the high frequency components of the quantization noise and provide low rate and high resolution digital words. The charge amplifier and the Σ∆ converters are operated respectively at 61.5 kHz and 20.5 kHz. The data rate at the output of the reconstruction depends on the user selected Decimation Factor (DF) and spans from 40 Hz to 2560 Hz. The acceleration data may be accessed through an I 2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS3LV02DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. The LIS3LV02DL may also be configured to generate an inertial Wake-Up, Direction Detection and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes.
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. This allows the user to employ the device without further calibration.
4 Application hints
Figure 5. LIS3LV02DL electrical connection placed as near as possible to the pin 13 of the device (common design practice).
4.1 Soldering Information
The LGA-16 package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Leave “Pin 1 Indicator” unconnected during soldering.
5 Digital interfaces
line must be tied high (i.e connected to Vdd_IO).
5.1 I 2C serial interface
whose content can also be read back. The relevant I2C terminology is given in the table below. embedded inside the LIS3LV02DL. When the bus is free both the lines are high. Table 9. Serial interface pin description Table 10. Serial interface pin description
5.1.1 I 2C operation
by the Master. The Slave ADdress (SAD) associated to the LIS3LV02DL is 0011101b. to allow multiple data read/write. (Write) the Master will transmit to the slave with direction unchanged. Table 11. Transfer when master is writing one byte to slave Table 12. Transfer when master is writing multiple bytes to slave Table 13. Transfer when master is receiving (reading) one byte of data from slave Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
terminated by the generation of a STOP (SP) condition. address of first register to read.
5.2 SPI bus interface
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. Read and write protocol the transmission and goes back high at the end. CS is high (no transmission). at the falling edge of SPC and should be captured at the rising edge of SPC.
from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. is ‘1’ the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 7. SPI read protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register.
Figure 8. Multiple bytes SPI read protocol (2 bytes example)
5.2.2 SPI write
Figure 9. SPI write protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 10. Multiple bytes SPI write protocol (2 bytes example)
5.2.3 SPI Read in 3-wires mode
Figure 11. SPI read protocol in 3-wires mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Multiple read command is also available in 3-wires mode.
6 Register mapping
Table 15. Registers address map
cause permanent damages to the device. Table 15. Registers address map (continued)
7 Register description
necessary to change their value for normal device operation.
7.1 WHO_AM_I (0Fh)
physical address assigned in factory is 3Ah.
7.2 OFFSET_X (16h)
7.3 OFFSET_Y (17h)
7.4 OFFSET_Z (18h)
Table 16. Register (0Fh) Table 17. Register description (0Fh) Table 18. Register (16h) Table 19. Register description (16h) Table 20. Register (17h) Table 21. Register description (17h) Table 22. Register (18h)
7.5 GAIN_X (19h)
7.6 GAIN_Y (1Ah)
7.7 GAIN_Z (1Bh)
7.8 CTRL_REG1 (20h)
Table 23. Register description (18h) Table 24. Register (19h) Table 25. Register description (19h) Table 26. Register (1Ah) Table 27. Register description (1Ah) Table 28. Register (1Bh) Table 29. Register description (1Bh) Table 30. Register (20h) Table 31. Register description (20h)
when either PD1 or PD0 is set to 1. check the functionality of the whole measurement chain. Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the Y -axis measurement channel when set to 1. The default value is 1. Xen bit enables the X-axis measurement channel when set to 1. The default value is 1.
7.9 CTRL_REG2 (21h)
Table 31. Register description (continued) (20h) Table 32. Register (21h) Table 33. Register description (21h)
value is +/-2g. In order to obtain a +/-6g full scale it is necessary to set FS bit to ‘1’. that output registers is not updated until the upper (lower) part is read too. This feature avoids reading LSB and MSB related to different samples. inverted (refer to data register description for more details). internal registers related to trimming functions to permit a good behavior of the device itself. process the BOOT bit is set again to ‘0’. modify DRDY bit to enable Data-Ready signal generation. frequency of the data rate chosen. interface mode output data are sent to SDA/SDI pad. bits are replaced by the bit representing the sign. Table 33. Register description (continued) (21h)
7.10 CTRL_REG3 (22h)
7.11 HP_FILTER_RESET (23h)
high pass-filter. Read data is not significant.
7.12 STATUS_REG (27h)
Table 34. Register (22h) Table 35. Register description (22h) Table 36. Register (27h) Table 37. Register description (27h)
7.13 OUTX_L (28h)
7.14 OUTX_H (29h)
replaced with bit 11 (i.e. XD15-XD12=XD11, XD11, XD11, XD11).
7.15 OUTY_L (2Ah)
Table 37. Register description (continued) (27h) Table 38. Register (28h) Table 39. Register description (28h) Table 40. Register (29h) Table 41. Register description (29h) Table 42. Register (2Ah)
7.16 OUTY_H (2Bh)
replaced with bit 11 (i.e. YD15-YD12=YD11, YD11, YD11, YD11).
7.17 OUTZ_L (2Ch)
7.18 OUTZ_H (2Dh)
replaced with bit 11 (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11). Table 43. Register description (2Ah) Table 44. Register (2Bh) Table 45. Register description (2Bh) Table 46. Register (2Ch) Table 47. Register description (2Ch) Table 48. Register (2Dh) Table 49. Register description (2Dh)
7.19 FF_WU_CFG (30h)
Free-fall and inertial wake-up configuration register.
7.20 FF_WU_SRC (31h)
Table 50. Register (30h) Table 51. Register description (30h) And/Or combination of Interrupt events. Default value: 0. Latch interrupt request. Default value: 0. Enable Interrupt request on Z High event. Default value: 0. Enable Interrupt request on Z Low event. Default value: 0. Enable Interrupt request on Y High event. Default value: 0. Enable Interrupt request on Y Low event. Default value: 0. Enable Interrupt request on X High event. Default value: 0. Enable Interrupt request on X Low event. Default value: 0. Table 52. Register (31h)
7.21 FF_WU_ACK (32h)
allows the FF_WU_SRC register refresh. Read data is not significant.
7.22 FF_WU_THS_L (34h)
7.23 FF_WU_THS_H (35h)
Table 53. Register description (31h) Table 54. Register (34h) Table 55. Register description (34h) Table 56. Register (35h) Table 57. Register description (35h)
7.24 FF_WU_DURATION (36h)
This register sets the minimum duration of the free-fall/wake-up event to be recognized.
7.25 DD_CFG (38h)
Table 58. Register (36h) Table 59. Register description (36h) Table 60. Register (38h) Table 61. Register description (38h) DD_ACK reg. Default value: 0.
Direction-detector configuration register.
7.26 DD_SRC (39h)
Direction detector source register. Table 61. Register description (continued) (38h) Table 62. Register (39h) Table 63. Register description (39h) Interrupt event from direction change.
7.27 DD_ACK (3Ah)
the DD_SRC register refresh. Read data is not significant.
7.28 DD_THSI_L (3Ch)
7.29 DD_THSI_H (3Dh)
7.30 DD_THSE_L (3Eh)
7.31 DD_THSE_H (3Fh)
Table 64. Register (3Ch) Table 65. Register description (3Ch) Table 66. Register (3Dh) Table 67. Register description (3Dh) Table 68. Register (3Eh) Table 69. Register description (3Eh) Table 70. Register (3Fh) Table 71. Register description (3Fh)
8 Typical performance characteristics
8.1 Mechanical characteristics at 25°C
Figure 12. X-axis zero-g level at 3.3 V Figure 13. X-axis sensitivity at 3.3 V Figure 14. Y-axis zero-g level at 3.3 V Figure 15. Y-axis sensitivity at 3.3 V
8.2 Mechanical characteristics de rived from measurement in the
Figure 16. Z-axis zero-g level at 3.3 V Figure 17. Z-axis Sensitivity at 3.3 V Figure 18. X-axis zero-g level change vs. Figure 19. X-axis sensitivity change vs.
8.3 Electro-mechanical characteristics at 25°C
Figure 20. Y-axis zero-g level change vs. Figure 21. Y-axis sensitivity change vs. Figure 22. Z-axis zero-g level change vs. Figure 23. Z-axis sensitivity change vs. Figure 24. X and Y axis zero-g level as Figure 25. Z axis zero-g level as function of
9 Package information
ECOPACK® specifications are available at: www.st.com. Figure 28. LGA-16 mechanical data and package dimensions
Table 72. Document revision history 15-Feb-2006 1 Initial release. Typical performance characteristics.