LIS3DH STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 42
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Mechanical and electrical specifications
- 2.1 Mechanical characteristics
- 2.2 Temperature sensor characteristics
- 2.3 Electrical characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I2C - Inter IC control interface
- 2.5 Absolute maximum ratings
- 3 Terminology and functionality
- 3.1 Terminology
- 3.1.1 Sensitivity
- 3.1.2 Zero-g level
- 3.2 Functionality
- 3.2.1 Normal mode, low power mode
- 3.2.2 Self-test
- 3.3 Sensing element
- 3.4 IC interface
- 3.5 Factory calibration
- 3.6 FIFO
- 3.7 Auxiliary ADC
- 4 Application hints
- 4.1 Soldering information
- 5 Digital main blocks
- 5.1 FIFO
- 5.1.1 Bypass mode
Datasheet sections
- 8.20 FIFO_SRC_REG (2Fh)
- 8.21 INT1_CFG (30h)
- 8.22 INT1_SRC (31h)
- 8.23 INT1_THS (32h)
- 8.24 INT1_DURATION (33h)
- 8.25 CLICK_CFG (38h)
- 8.26 CLICK_SRC (39h)
- 8.27 CLICK_THS (3Ah)
- 8.28 TIME_LIMIT (3Bh)
- 8.29 TIME_LATENCY (3Ch)
- 8.30 TIME WINDOW(3Dh)
- 9 Package information
- 10 Revision history
Features
■ Wide supply voltage, 1.71 V to 3.6 V ■ Independent IOs supply (1.8 V) and supply voltage compatible ■ Ultra low-power mode consumption down to 2 µA ■ ±2g/±4g/±8g/±16g dynamically selectable full- scale ■ I2C/SPI digital output interface ■ 16 bit data output ■ 2 independent programmable interrupt generators for free-fall and motion detection ■ 6D/4D orientation detection ■ Free-fall detection ■ Motion detection ■ Embedded temperature sensor ■ Embedded self-test ■ Embedded 96 levels of 16 bit data output FIFO ■ 10000 g high shock survivability ■ ECOPACK® RoHS and “Green” compliant
Applications
■ Motion activated functions ■ Free-fall detection ■ Click/double click recognition ■ Intelligent power saving for handheld devices ■ Pedometer ■ Display orientation ■ Gaming and virtual reality input devices ■ Impact recognition and logging ■ Vibration monitoring and compensation
Description
The LIS3DH is an ultra low-power high performance three axes linear accelerometer belonging to the “nano” family, with digital I2C/SPI serial interface standard output. The device features ultra low-power operational modes that allow advanced power saving and smart embedded functions. The LIS3DH has dynamically user selectable full scales of ±2g/±4g/±8g/±16g and it is capable of measuring accelerations with output data rates from 1 Hz to 5 kHz. The self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself. Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS3DH has an integrated 32-level first in, first out (FIFO) buffer allowing the user to store data for host processor intervention reduction. The LIS3DH is available in small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. Table 1. Device summary
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connection
96 Level
Table 2. Pin description
1 Vdd_IO Power supply for I/O pins
2 NC Not connected
3 NC Not connected
4 SCL
5 GND 0V supply
7 SDO
9 INT2 Inertial interrupt 2
10 RES Connect to GND
11 INT1 Inertial interrupt 1
12 GND 0 V supply
13 ADC3 Analog to digital converter input 3
14 Vdd Power supply
15 ADC2 Analog to digital converter input 2
16 ADC1 Analog to digital converter input 1
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics
- Typical specificat ions are not guaranteed.
- Verified by wafer level test and measur ement of initial offset and sensitivity.
- Typical zero- g level offset value after MSL3 preconditioning.
- Offset can be eliminated by enablin g the built-in high pass filter.
- The sign of “Self-test output change” is defined by CTRL_REG4 STsign bit, for all axes.
- Self-test output changes with the power supply. “Self-test output change” is defined as
OUTPUT[LSb](CTRL_REG4 ST bit=1) - OUTPUT[LSb](CTRL_REG4 ST bit=0). 1LSb=1mg, ±2 g Full-scale.
- Output data reach 99% of final value after 1 ms when enabling self-test mode, due to device filtering.
2.2 Temperature sensor characteristics
2.3 Electrical characteristics
b. The product is factory calibrated at 2.5 V. Table 4. Temperature sensor characteristics
- Typical specificat ions are not guaranteed.
Table 5. Electrical characteristics
- Typical specification are not guaranteed.
- It is possible to remove Vdd maintaining Vdd_IO withou t blocking the communication busses, in this condition the
measurement chain is powered off.
- Referred to Table 25 for the ODR value and configuration.
- Time to obtain valid data after exiting power-down mode.
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram characterization results, not tested in production. 2 Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port.
3 When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal
Table 6. SPI slave timing values
2.4.2 I 2C - Inter IC control interface
Subject to general operating conditions for Vdd and top. Figure 4. I 2C Slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port. Table 7. I 2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
- Cb = total capacitance of one bus line, in pF.
2.5 Absolute maximum ratings
Table 8. Absolute maximum ratings
3 Terminology and functionality
3.1 Terminology
3.1.1 Sensitivity
the range of Sensitivities of a large population of sensors.
3.1.2 Zero- g level
deviation of the range of Zero-g levels of a population of sensors.
3.2 Functionality
3.2.1 Normal mode, low power mode
further the current consumption. The table below reported summarizes how to select the operating mode. Table 9. Operating mode selection
Terminology and functionality LIS3DH 16/42 Doc ID 17530 Rev 1
3.2.2 Self-test
Self-test allows to check the sensor functionality without moving it. The self-test function is off when the self-test bit (ST) is programmed to ‘0‘. When the self-test bit is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 3.2.3 6D / 4D orientation detection The LIS3DH include 6D / 4D orientation detection. 6D / 4D orientation recognition: In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration Z axis position detection is disable.
3.3 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows carrying out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in the fF range.
3.4 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by an analog-to-digital converter. The acceleration data may be accessed through an I 2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS3DH features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The LIS3DH may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free- Fall and Wake-Up can be available simultaneously on two different pins.
LIS3DH Terminology and functionality Doc ID 17530 Rev 1 17/42
3.5 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows to use the device without further calibration.
3.6 FIFO
The LIS3DH contains a 10 bit, 32-level FIFO. Buffered output allows 4 operation modes: FIFO, stream, trigger and FIFO ByPass. Where FIFO bypass mode is activated FIFO is not operating and remains empty. In FIFO mode, data from acceleration detection on x, y, and z- axes measurements are stored in FIFO.
3.7 Auxiliary ADC
The LIS3DH contains an auxiliary 10 bit ADC with 3 separate dedicated inputs.
4 Application hints
Figure 5. LIS3DH electrical connection be placed as near as possible to the pin 14 of the device (common design practice). 2C or SPI interfaces.When using the I2C, CS must be tied high. The ADC1, ADC2 & ADC3 if not used can be left floating or keep connected to Vdd or GND.
4.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering.
LIS3DH Digital main blocks Doc ID 17530 Rev 1 19/42
5 Digital main blocks
5.1 FIFO
LIS3DH embeds a 32-slot of 10bit data FIFO for each of the three output channels, X, Y and Z. This allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wakeup only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to four different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits into the FIFO_CTRL_REG (2E). Programmable Watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on INT1/2 pin (configuration through FIFO_CFG_REG).
5.1.1 Bypass mode
In Bypass mode, the FIFO is not operational and for this reason it remains empty. As described in the next figure, for each channel only the first address is used. The remaining FIFO slots are empty.
5.1.2 FIFO mode
In FIFO mode, data from X, Y and Z channels are stored into the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG in order to be raised when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG. The FIFO continues filling until it is full (32 slots of 10data for X, Y and Z). When full, the FIFO stops collecting data from the input channels.
5.1.3 Stream mode
In the stream mode, data from X, Y and Z measurement are stored into the FIFO. A watermark interrupt can be enabled and set as in the FIFO mode.The FIFO continues filling until it’s full (32 slots of 10data for X, Y and Z). When full, the FIFO discards the older data as the new arrive.
5.1.4 Stream-to-FIFO mode
In Stream-to_FIFO mode, data from X, Y and Z measurement are stored into the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG) in order to be raised when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG. The FIFO continues filling until it’s full (32 slots of 10 data for X, Y and Z). When full, the FIFO discards the older data as the new arrive. Once trigger event occurs, the FIFO starts operating in FIFO mode.
5.1.5 Retrieve data from FIFO
FIFO data is read through OUT_X (Addr reg 28h,29h), OUT_Y (Addr reg 2Ah,2Bh) and OUT_Z (Addr reg 2Ch,2Dh). When the FIFO is in stream, Trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z registers provides the data stored into the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed into the OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst operations can be used.
6 Digital interfaces
line must be tied high (i.e. connected to Vdd_IO).
6.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. resistor. When the bus is free both the lines are high. Table 10. Serial interface pin description Table 11. Serial interface pin description
6.1.1 I 2C operation
SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 12. SAD+Read/Write patterns Table 13. Transfer when master is writing one byte to slave Table 14. Transfer when master is writing multiple bytes to slave:
terminated by the generation of a STOP (SP) condition. address of first register to be read.
6.2 SPI bus interface
The LIS3DH SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. Read and write protocol Table 15. Transfer when master is receiving (reading) one byte of data from slave: Table 16. Transfer when master is receiving (reading) multiple bytes of data from slave
falling edge of SPC and should be captured at the rising edge of SPC. from the device is read. In latter case, the chip drives SDO at the start of bit 8. bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
6.2.1 SPI read
Figure 7. SPI read protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Figure 8. Multiple bytes SPI read protocol (2 bytes example)
6.2.2 SPI write
Figure 9. SPI write protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 10. Multiple bytes SPI write protocol (2 bytes example)
6.2.3 SPI read in 3-wires mode
Figure 11. SPI read protocol in 3-wires mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Multiple read command is also available in 3-wires mode.
7 Register mapping
Table 17. Register address map
cause permanent damages to the device.
8 Registers description
8.1 STATUS_AUX (07h)
8.2 OUT_1_L (08h), OUT_1_H (09h)
1-axis acceleration data. The value is expressed in two’s complement.
8.3 OUT_2_L (0Ah), OUT_2_H (0Bh)
2-axis acceleration data. The value is expressed in two’s complement.
8.4 OUT_3_L (0Ch), OUT_3_H (0Dh)
3-axis acceleration data. The value is expressed in two’s complement. Table 18. STATUS_REG_AUX register Table 19. STATUS_REG_AUX description
8.5 INT_COUNTER (0Eh)
8.6 WHO_AM_I (0Fh)
Device identification register.
8.7 TEMP_CFG_REG (1Fh)
8.8 CTRL_REG1 (20h)
Table 20. INT_COUNTER register Table 21. WHO_AM_I register Table 22. TEMP_CFG_REG register Table 23. TEMP_CFG_REG description Table 24. CTRL_REG1 register Table 25. CTRL_REG1 description
8.9 CTRL_REG2 (21h)
Table 26. Data rate configuration Table 27. CTRL_REG2 register Table 28. CTRL_REG2 description HPCLICK High pass filter enabled for CLICK function.
8.10 CTRL_REG3 (22h)
8.11 CTRL_REG4 (23h)
Table 29. High pass filter mode configuration Table 30. CTRL_REG3 register Table 31. CTRL_REG3 description I1_CLICK CLICK interrupt on INT1. Default value 0. I1_AOI1 AOI1 interrupt on INT1. Default value 0. I1_AOI2 AOI2 interrupt on INT1. Default value 0. I1_DRDY1 DRDY1 interrupt on INT1. Default value 0. I1_DRDY2 DRDY2 interrupt on INT1. Default value 0. I1_WTM FIFO Watermark interrupt on INT1. Default value 0. I1_OVERRUN FIFO Overrun interrupt on INT1. Default value 0. Table 32. CTRL_REG4 register Table 33. CTRL_REG4 description BLE Big/little endian data selection. Default value 0.
8.12 CTRL_REG5 (24h)
8.13 CTRL_REG6 (25h)
8.14 REFERENCE/DATACAPTURE (26h)
(0: 4-wire interface; 1: 3-wire interface). Table 34. Self test mode configuration Table 33. CTRL_REG4 description (continued) Table 35. CTRL_REG5 register Table 36. CTRL_REG5 description cleared by reading INT1_SRC itself. Default value: 0. Table 37. CTRL_REG6 register Table 38. REFERENCE register
8.15 STATUS_REG (27h)
8.16 OUT_X_L (28h), OUT_X_H (29h)
X-axis acceleration data. The value is expressed in two’s complement.
8.17 OUT_Y_L (2Ah), OUT_Y_H (2Bh)
Y-axis acceleration data. The value is expressed in two’s complement.
8.18 OUT_Z_L (2Ch), OUT_Z_H (2Dh)
Z-axis acceleration data. The value is expressed in two’s complement. Table 39. REFERENCE register description Table 40. STATUS register Table 41. STATUS register description
8.19 FIFO_CTRL_REG (2Eh)
8.20 FIFO_SRC_REG (2Fh)
8.21 INT1_CFG (30h)
Table 42. REFERENCE register Table 43. REFERENCE register description Table 44. FIFO mode configuration Table 45. FIFO_SRC register Table 46. INT1_CFG register Table 47. INT1_CFG description
Content of this register is loaded at boot. Write operation at this address is possible only after system boot. Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. unknown zone to known zone. The interrupt signal stay for a duration ODR. known zone. The interrupt signal stay until orientation is inside the zone.
8.22 INT1_SRC (31h)
Table 48. Interrupt mode Table 49. INT1_SRC register
0 I A Z HZ LY HY LX HX L
Table 50. INT1_SRC description
Interrupt 1 source register. Read only register. allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
8.23 INT1_THS (32h)
8.24 INT1_DURATION (33h)
steps and maximum values depend on the ODR chosen.
8.25 CLICK_CFG (38h)
Table 51. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 52. INT1_THS description Table 53. INT1_DURATION register
0 D 6D 5D 4D 3D 2D 1D 0
Table 54. INT1_DURATION description Table 55. CLICK_CFG register
8.26 CLICK_SRC (39h)
Table 56. CLICK_CFG description Table 57. CLICK_SRC register Table 58. CLICK_SRC description
8.27 CLICK_THS (3Ah)
8.28 TIME_LIMIT (3Bh)
8.29 TIME_LATENCY (3Ch)
8.30 TIME WINDOW(3Dh)
Table 59. CLICK_THS register Table 60. CLICK_SRC description Table 61. TIME_LIMIT register Table 62. TIME_LIMIT description Table 63. TIME_LATENCY register Table 64. TIME_LATENCY description Table 65. TIME_WINDOW register Table 66. TIME_WINDOW description
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Figure 12. LGA-16: Mechanical data and package dimensions Table 67. LGA-16: Mechanical data
Table 68. Document revision history