LIS331DLF STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 38
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Mechanical and electrical specifications
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Communication interface characteristics
- 2.3.1 SPI - serial peripheral interface
- 2.3.2 I2C - Inter IC control interface
- 2.4 Absolute maximum ratings
- 2.5 Terminology
- 2.5.1 Sensitivity
- 2.5.2 Zero-g level
- 2.5.3 Self-test
- 2.5.4 Sleep to wake-up
- 3 Functionality
- 3.1 Sensing element
- 3.2 IC interface
- 3.3 Factory calibration
- 4 Application hints
- 4.1 Soldering information
- 5 Digital interfaces
- 5.1 I2C serial interface
- 5.1.1 I2C operation
- 5.2 SPI bus interface
- 5.2.1 SPI read
- 5.2.2 SPI write
- 5.2.3 SPI read in 3-wires mode
Features
■ Wide supply voltage, 2.16 V to 3.6 V ■ Low voltage compatible IOs, 1.8 V ■ Ultra low-power mode consumption down to 10 µA ■ ±2g/±4g/±8g dynamically selectable full-scale ■ I2C/SPI digital output interface ■ 6 bit resolution ■ 2 independent programmable interrupt generators for free-fall and motion detection ■ Sleep to wake-up function ■ 6D orientation detection ■ Embedded self-test ■ 10000 g high shock survivability ■ ECOPACK® RoHS and “Green” compliant (see Section 8)
Applications
■ Display orientation ■ Gaming ■ User interface ■ Motion activated functions ■ Intelligent power saving for handheld devices ■ Impact recognition and logging
Description
The LIS331DLF is an ultra low-power high performance three axes linear accelerometer belonging to the “nano” family, with digital I2C/SPI serial interface standard output. The device features ultra low-power operational modes that allow advanced power saving and smart sleep to wake-up functions. The LIS331DLF has dynamically user selectable full scales of ±2g/±4g/±8g and it is capable of measuring accelerations with output data rates from 0.5 Hz to 400 Hz. The self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate interrupt signal by inertial wake-up/free-fall events as well as by the position of the device itself. Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS331DLF is available in small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. LGA 16 (3x3x1 mm) Table 1. Device summary
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connection
Table 2. Pin description
1 Vdd_IO Power supply for I/O pins
2 NC Not connected
3 NC Not connected
4 SCL
5 GND 0 V supply
7 SDO
9 INT 2 Inertial interrupt 2
10 Reserved Connect to GND
11 INT 1 Inertial interrupt 1
12 GND 0 V supply
13 GND 0 V supply
14 Vdd Power supply
15 Reserved Connect to Vdd
16 GND 0 V supply
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted (1)
- Typical specificat ions are not guaranteed
- Verified by wafer level test and measur ement of initial offset and sensitivity
- Typical zero-g level offset value after MSL3 preconditioning
- Offset can be eliminated by enabl ing the built-in high pass filter
- The sign of “Self-test output change” is defined by CTRL_REG4 STsign bit (Table 28), for all axes.
- Self-test output changes with the power supply. “Self-test output change” is defined as
- Output data reach 99% of final value after 1/ODR+1 ms when enabling Self-test mode, due to device filtering
2.2 Electrical characteristics
Table 4. Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted (1)
- Typical specification are not guaranteed
- It is possible to remove Vdd maintaining Vdd_IO withou t blocking the communication busses, in this condition the
measurement chain is powered off.
- Refer to Table 20 for filter cut-off frequency
- Time to obtain valid data after exiting power-down mode
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram (2)
- Values are guaranteed at 10 MHz clock fr equency for SPI with both 4 and 3 wires, based on characterization results, not
- Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port
- When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors
Table 5. SPI slave timing values
2.3.2 I 2C - Inter IC control interface
Subject to general operating conditions for Vdd and top. Figure 4. I 2C Slave timing diagram (a) Table 6. I 2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production
- Cb = total capacitance of one bus line, in pF
2.4 Absolute maximum ratings
Table 7. Absolute maximum ratings
Mechanical and electrical specifications LIS331DLF 14/38 Doc ID 15101 Rev 4
2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensors.
2.5.2 Zero- g level
Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level tolerance (TyOff) describes the Standard deviation of the range of Zero-g levels of a population of sensors.
2.5.3 Self-test
Self-test allows to check the sensor functionality without moving it. The Self-test function is off when the self-test bit (ST) of CTRL_REG4 (control register 4) is programmed to ‘0‘. When the self-test bit of CTRL_REG4 is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
2.5.4 Sleep to wake-up
The “sleep to wake-up” function, in conjunction with low-power mode, allows to further reduce the system power consumption and develop new smart applications. LIS331DLF may be set in a low-power operating mode, characterized by lower date rates refreshments. In this way the device, even if sleeping, keep on sensing acceleration and generating interrupt requests. When the “sleep to wake-up” function is activated, LIS331DLF is able to automatically wake- up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. With this feature the system may be efficiently switched from low-power mode to full- performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility.
3 Functionality
The LIS331DLF is a “nano”, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I 2C/SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in the fF range.
3.2 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by an analog-to-digital converter. The acceleration data may be accessed through an I 2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS331DLF features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The LIS331DLF may also be configured to generate an inertial wake-up and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free-Fall and Wake-Up can be available simultaneously on two different pins.
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows to use the device without further calibration.
4 Application hints
Figure 5. LIS331DLF electrical connection be placed as near as possible to the pin 14 of the device (common design practice). 2C or SPI interfaces.When using the I2C, CS must be tied high. completely programmed by the user through the I2C/SPI interface.
4.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Leave “pin 1 indicator” unconnected during soldering.
5 Digital interfaces
line must be tied high (i.e. connected to Vdd_IO).
5.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. embedded inside the LIS331DLF. When the bus is free both the lines are high. Table 8. Serial interface pin description Table 9. Serial interface pin description
5.1.1 I 2C operation
7 LSb represent the actual register address while the MSB enables address auto increment. allow multiple data read/write. SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns Table 11. Transfer when master is writing one byte to slave
terminated by the generation of a STOP (SP) condition. address of first register to be read.
5.2 SPI bus interface
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Table 12. Transfer when master is writing multiple bytes to slave: Table 13. Transfer when master is receiving (reading) one byte of data from slave: Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave
Figure 6. Read and write protocol falling edge of SPC and should be captured at the rising edge of SPC. before the rising edge of CS. from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). is ‘1’ the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 7. SPI read protocol
performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Figure 8. Multiple bytes SPI read protocol (2 bytes example)
5.2.2 SPI write
Figure 9. SPI write protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register.
Figure 10. Multiple bytes SPI write protocol (2 bytes example)
5.2.3 SPI read in 3-wires mode
Figure 11. SPI read protocol in 3-wires mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Multiple read command is also available in 3-wires mode.
6 Register mapping
Table 15. Register address map
Register mapping LIS331DLF 24/38 Doc ID 15101 Rev 4 Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.
7 Register description
write the data through serial interface.
7.1 WHO_AM_I (0Fh)
Device identification register. This register contains the device identifier that for LIS331DLF is set to 52h.
7.2 CTRL_REG1 (20h)
the possible configuration for DR1 and DR0 bits. Table 16. WHO_AM_I register Table 17. CTRL_REG1 register Table 18. CTRL_REG1 description
7.3 CTRL_REG2 (21h)
Table 19. Power mode and low-power output data rate configurations Table 20. Normal-mode output data rate configurations and low-pass cut-off
- “11” bit configuration is not allow ed and may cause incorrect device functionality.
Table 21. CTRL_REG2 register Table 22. CTRL_REG2 description
internal registers related to trimming functions to permit a good behavior of the device itself. process the BOOT bit is set again to ‘0’. Table 23. High-pass filter mode configuration Table 24. High-pass filter cut-off frequency configuration Table 22. CTRL_REG2 description (continued)
7.4 CTRL_REG3 [Interrupt CTRL register] (22h)
7.5 CTRL_REG4 (23h)
Table 25. CTRL_REG3 register Table 26. CTRL_REG3 description PP_OD Push-pull/Open drain selection on interrupt pad. Default value 0. reading INT2_SRC itself. Default value: 0. Data signal on INT 2 pad control bits. Default value: 00. reading INT1_SRC register. Default value: 0. Data signal on INT 1 pad control bits. Default value: 00. Table 27. Data signal on INT 1 and INT 2 pad Table 28. CTRL_REG4 register
7.6 CTRL_REG5 (24h)
TurnOn bits are used for turning on the sleep to wake function.
7.7 HP_FILTER_RESET (25h)
high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g. This allows to overcome the settling time of the high pass filter.
7.8 REFERENCE (26h)
This register sets the acceleration value taken as a reference for the high-pass filter output. bits are set to “01”, filter out is generated taking this value as a reference. Table 29. CTRL_REG4 description FS1, FS0 Full-scale selection. Default value: 00. STsign Self-test sign. Default value: 00. ST Self-test enable. Default value: 0. SIM SPI serial interface mode selection. Default value: 0. Table 30. CTRL_REG5 register
000000 T u r n O n 1 T u r n O n 0
Table 31. CTRL_REG5 description Tur nOn0 Turn-on mode selection for sleep to wake function. Default value: 00. Table 32. REFERENCE register Table 33. REFERENCE description Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.
7.9 STATUS_REG (27h)
7.10 OUT_X (29)
representation right justified.
7.11 OUT_Y (2Bh)
representation right justified.
7.12 OUT_Z (2Dh)
representation right justified. Table 34. STATUS_REG register Table 35. STATUS_REG description
7.13 INT1_CFG (30h)
Configuration register for Interrupt 1 source. Table 36. INT1_CFG register Table 37. INT1_CFG description AOI AND/OR combination of Interrupt events. Default value: 0. 6D 6 direction detection function enable. Default value: 0. Table 38. Interrupt 1 source configurations
7.14 INT1_SRC (31h)
Interrupt 1 source register. Read only register. allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
7.15 INT1_THS (32h)
7.16 INT1_DURATION (33h)
Table 39. INT1_SRC register
0 I A Z HZ LY HY LX HX L
Table 40. INT1_SRC description Table 41. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 42. INT1_THS description Table 43. INT1_DURATION register
0 D 6D 5D 4D 3D 2D 1D 0
steps and maximum values depend on the ODR chosen.
7.17 INT2_CFG (34h)
Configuration register for Interrupt 2 source. Table 44. INT2_DURATION description Table 45. INT2_CFG register Table 46. INT2_CFG description AOI AND/OR combination of Interrupt events. Default value: 0. 6D 6 direction detection function enable. Default value: 0. Table 47. Interrupt mode configuration
7.18 INT2_SRC (35h)
Interrupt 2 source register. Read only register. allows the refreshment of data in the INT2_SRC register if the latched option was chosen.
7.19 INT2_THS (36h)
Table 47. Interrupt mode configuration (continued) Table 48. INT2_SRC register Table 49. INT2_SRC description Table 50. INT2_THS register Table 51. INT2_THS description
7.20 INT2_DURATION (37h)
time steps and maximum values depend on the ODR chosen. Table 52. INT2_DURATION register Table 53. INT2_DURATION description
8 Package information
specifications, grade definitions and product status are available at: www.st.com. Figure 12. LGA16: mechanical data and package dimensions
9 Revision history
Table 54. Document revision history