LIS2MDL STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 41
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Module specifications
- 2.1 Sensor characteristics
- 2.2 Temperature sensor characteristics
- 2.3 Electrical characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I 2C - inter-IC control interface
- 2.5 Absolute maximum ratings
- 3 Terminology
- 3.1 Sensitivity
- 3.2 Zero-gauss level
- 3.3 Magnetic dynamic range
- 4 Functionality
- 4.1 Power modes
- 4.2 IC interface
- 4.3 Factory calibration
- 5 Application hints
- 5.1 Soldering information
- 5.2 High-current wiring effects
- 5.3 Startup sequence
- 6 Digital interfaces
- 6.1 I 2C serial interface
- 6.1.1 I 2C operation
- 6.2 SPI bus interface
- 6.2.1 SPI write
Features
3 magnetic field channels ±50 gauss magnetic dynamic range 16-bit data output SPI/I2C serial interfaces Analog supply voltage 1.71 V to 3.6 V Selectable power mode/resolution Single measurement mode Programmable interrupt generator Embedded self-test Embedded temperature sensor ECOPACK®, RoHS and “Green” compliant
Applications
Tilt-compensated compasses Map rotation Intelligent power saving for handheld devices Gaming and virtual reality input devices
Description
The LIS2MDL is an ultra-low-power, high- performance 3-axis digital magnetic sensor. The LIS2MDL has a magnetic field dynamic range of ±50 gauss. The LIS2MDL includes an I2C serial bus interface that supports standard, fast mode, fast mode plus, and high-speed (100 kHz, 400 kHz, 1 MHz, and 3.4 MHz) and an SPI serial standard interface. The device can be configured to generate an interrupt signal for magnetic field detection. The LIS2MDL is available in a plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. /*$ [[PP Table 1. Device summary
Table 16. I
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
Table 2. Pin description
1 SCL
2 NC Internally not connected. Can be tied to Vdd, Vdd_IO or GND.
5 C1 Capacitor connection (C1 = 220 nF)
6 GND Connected to GND
7 INT/DRDY/SDO Interrupt/data-ready signal or SDO line for 4-wire SPI connection
8 GND 0 V
9 Vdd Power supply
10 Vdd_IO Power supply for I/O pins
11 NC Internally not connected. Can be tied to Vdd, Vdd_IO or GND. 12 NC Internally not connected. Can be tied to Vdd, Vdd_IO or GND.
2 Module specifications
2.1 Sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(a). Table 3. Sensor characteristics
- Typical specifications are not guaranteed.
- Values after factory calibration test and trimming.
- Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited
number of samples, not measured during final test for production.
- Based on characterization data on a limited number of samples, not measured during final test for production.
- Excluding drift due to magnetic shock.
- With low-pass filter or offset cancellation enabled.
“Self-test” is defined as: OUTPUT[gauss](Self-test enabled) - OUTPUT[gauss](Self-test disabled).
2.2 Temperature sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted (b).
2.3 Electrical characteristics
Table 4. Temperature sensor characteristics
- Typical specifications are not guaranteed.
Table 5. Electrical characteristics
- Typical specifications are not guaranteed.
- 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pin in order to
guarantee the correct digital output voltage levels VOH and VOL.
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram characterization results, not tested in production. Table 6. SPI slave timing values
2.4.2 I 2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Table 7. I2C slave timing values (standard and fast mode)
- Data based on standard I 2C protocol requirement, not tested in production.
Table 8. I2C slave timing values (fast mode plus and high speed)
- Data based on standard I 2C protocol requirement, not tested in production.
Figure 4. I2C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
2.5 Absolute maximum ratings
Note: Supply voltage on any pin should never exceed 4.8 V. Table 9. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
3 Terminology
3.1 Sensitivity
Sensitivity describes the ratio of the output digital data expressed in LSB units and the applied magnetic field expressed in mG (milligauss). It can be measured, for example, by applying a known magnetic field along one axis and measuring the digital output of the device.
3.2 Zero-gauss level
Zero-gauss level offset (TyOff) describes the deviation of an actual output signal from the ideal output if no magnetic field is present.
3.3 Magnetic dynamic range
The magnetic dynamic range is defined as the magnetic field driven along one sensitive axis, giving the maximum digital output value.
4 Functionality
4.1 Power modes
The LIS2MDL provides two different power modes: high-resolution and low-power modes. improved without any increase in power consumption. Table 10. RMS noise of operating modes Table 11. Current consumption of operating modes
respectively, in Table 5 and Table 11.). Single measurement mode is enabled by writing bits MD[1:0] to '01' in CFG_REG_A (60h). configured in idle mode by setting the MD[1] bit to '1'. at which the MD[1:0] bits are written by the microcontroller/application processor. found, respectively, in Table 5 and Table 11. Table 12. Operating mode and turn-on time Table 13. Maximum ODR in single measurement mode (HR and LP modes)
100 Hz High resolution (LP = ‘0’)
150 Hz Low power (LP = ‘1’)
4.2 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter. The magnetic data may be accessed through an I 2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS2MDL features a data-ready signal which indicates when new sets of measured magnetic data are available, thus simplifying data synchronization in the digital system that uses the device.
4.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-gauss level (TyOff). The trim values are stored inside the device in nonvolatile memory. Anytime the device is turned on, the trim parameters are downloaded into the registers to be used during active operation. This allows using the device without further calibration.
5 Application hints
Figure 5. LIS2MDL electrical connections be placed as near as possible to pin 9 of the device (common design practice). in this condition the measurement chain is powered off. due to the length of the copper strips. 2C or SPI interfaces. When using the I2C, CS must be tied high (i.e. programmed by the user through the I2C/SPI interface.
DRDY_on_PIN bit to '1' in CFG_REG_C (62h). magnetometer hard-iron compensation, interrupt generation, self-test procedure). Table 14. Internal pin status
2 NC Internally not connected
5 C1 Capacitor connection (C1 = 220 nF) External capacitor, voltage forced
6 GND 0 V
7 INT/DRDY/SDO Interrupt/data-ready signal or SDO for 4-wire SPI
11 NC Internally not connected
12 NC Internally not connected
5.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standards. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Land pattern and soldering recommendations are available at www.st.com.
5.2 High-current wiring effects
High current in wiring and printed circuit traces can be culprits in causing errors in magnetic field measurements for compassing. Conductor-generated magnetic fields will add to the Earth’s magnetic field, leading to errors in compass heading computation. Keep currents higher than 10 mA a few millimeters away from the sensor IC.
5.3 Startup sequence
The following general-purpose sequence can be used to configure the device: 1. Write CFG_REG_A = 80h // Enable temperature compensation //Mag = 10 Hz (high-resolution and continuous mode) 2. Write CFG_REG_C = 01h // Mag data-ready interrupt enable
6 Digital interfaces
CS line must be tied high (i.e. connected to Vdd_IO).
6.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. up resistor. When the bus is free, both the lines are high. mode plus (1 MHz) and high-speed mode (3.4 MHz). Table 15. Serial interface pin description Table 16. I2C terminology
6.1.1 I 2C operation
7 LSb represent the actual register address while the MSB enables address auto increment. allow multiple data read/writes. SAD+read/write bit pattern is composed, listing all the possible configurations. Table 17. Transfer when master is writing one byte to slave Table 18. Transfer when master is writing multiple bytes to slave Table 19. Transfer when master is receiving (reading) one byte of data from slave Table 20. Transfer when master is receiving (reading) multiple bytes of data from slave
terminated by the generation of a STOP (SP) condition. The slave address is 0011110b. SAD+Read/Write bit patterns are composed, listing all the possible configurations. Table 21. SAD + Read/Write patterns
6.2 SPI bus interface
The default serial interface interacts with the application using 3 wires: CS, SPC, SDI/O. The 4-wire SPI interface mode can be activated by writing bit 2 of CFG_REG_C (62h) to 1. Of course, doing this disables the interrupt and data-ready signaling capability of the device.
6.2.1 SPI write
Figure 6. SPI write protocol command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1-7: address AD(6:0). This is the address field of the indexed register. Figure 7. Multiple byte SPI write protocol (2-byte example)
6.2.2 SPI read
Figure 8. SPI read protocol bit 0: WRITE bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is available in 3-wire mode.
7 Register mapping
Table 22. Register address map
- R = read-only register, R/W = readable/writable register
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
LIS2MDL Register description
8 Register description
8.1 OFFSET_X_REG_L (45h) and OFFSET_X_REG_H (46h)
These registers comprise a 16-bit register and represent X hard-iron offset in order to compensate environmental effects (data in two’s complement). These values act on the magnetic output data value in order to delete the environmental offset.
8.2 OFFSET_Y_REG_L (47h) and OFFSET_Y_REG_H (48h)
These registers comprise a 16-bit register and represent Y hard-iron offset in order to compensate environmental effects (data in two’s complement). These values act on the magnetic output data value in order to delete the environmental offset.
8.3 OFFSET_Z_REG_L (49h) and OFFSET_Z_REG_H (4Ah)
These registers comprise a 16-bit register and represent Z hard-iron offset in order to compensate environmental effects (data in two’s complement). These values act on the magnetic output data value in order to delete the environmental offset.
8.4 WHO_AM_I (4Fh)
The identification register is used to identify the device. 01000000
8.5 CFG_REG_A (60h)
Table 23. CFG_REG_A register Table 24. CFG_REG_A register description
- For proper operation, this bit must be set to '1'.
SOFT_RST When this bit is set, the configuration registers and user registers are reset. Table 25. Output data rate configuration Table 26. Mode of operation DRDY_on_PIN bit in CFG_REG_C (62h). register returns to idle mode bit values. 1 1 Idle mode. Device is placed in idle mode. I 2C and SPI active (default).
8.6 CFG_REG_B (61h)
Table 27. CFG_REG_B_M register Table 28. CFG_REG_B_M register description must be set to 1 when enabling offset cancellation in single measurement mode. Table 29. Digital low-pass filter
8.7 CFG_REG_C (62h)
Table 30. CFG_REG_C register Table 31. CFG_REG_C register description
8.8 INT_CTRL_REG (63h)
The interrupt control register is used to enable and to configure the interrupt recognition. Table 32. INT_CRTL_REG register
0 INT_on_PIN I2C_DIS BDU BLE 4WSPI Self_test DRDY_on_PIN
on the INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode. 2C interface is inhibited. Only the SPI interface can be used. one part is updated and the other one remains old. BLE If ‘1’, an inversion of the low and high parts of the data occurs. 4WSPI Set to '1' to enable SDO line on pin 7. Self_test If ‘1’, the self-test is enabled. INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode.
- This bit must be set to ‘0’ for the correct operation of the device.
Table 33. INT_CTRL_REG register description IEA Controls the polarity of the INT bit ( INT_SOURCE_REG (64h)) when an interrupt occurs.
8.9 INT_SOURCE_REG (64h)
When interrupt latched is selected, reading this register resets all the bits in this register. Table 34. INT_SOURCE_REG register Table 35. INT_SOURCE_REG register description
8.10 INT_THS_L_REG (65h)
This register contains the least significant bits of the threshold value chosen for the interrupt. Table 36. INT_THS_L_REG register Table 37. INT_THS_L_REG register description
8.11 INT_THS_H_REG (66h)
Table 38. INT_THS_H_REG register If IEL = 0, then INT is pulsed. If IEL = 1, then INT is latched. Once latched, INT remains in the same state until INT_SOURCE_REG (64h) is read. Table 33. INT_CTRL_REG register description (continued) INT This bit signals when the interrupt event occurs. TH[7:0] Threshold value for the interrupt.
Table 39. INT_THS_H_REG register description detected for both positive and negative sides.
8.12 STATUS_REG (67h)
Table 40. STATUS_REG register Table 41. STATUS_REG register description
8.13 OUTX_L_REG, OUTX_H_REG (68h - 69h)
output X LSB register (68h). otherwise hard-iron calibration is included. Table 42. OUTX_L_REG register TH[15:8] Threshold value for the interrupt. (0: no overrun has occurred; 1: a new set of data has overwritten the previous set). (0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data). (0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data). (0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data). (0: a new set of data is not yet available; 1: a new set of data is available).
Table 43. OUTX_H_REG register X component of the magnetic data.
8.14 OUTY_L_REG, OUTY_H_REG (6Ah - 6Bh)
output Y LSB register (6Ah). otherwise hard-iron calibration is included. Table 44. OUTY_L_REG register Table 45. OUTY_H_REG register Y component of the magnetic data.
8.15 OUTZ_L_REG, OUTZ_H_REG (6Ch - 6Dh)
output Z LSB register (6Ah). otherwise hard-iron calibration is included. Table 46. OUTZ_L_REG register Table 47. OUTZ_H_REG register Z component of the magnetic data.
8.16 TEMP_OUT_L_REG (6Eh), TEMP_OUT_H_REG (6Fh)
significant bits contain a copy of the sign bit. The nominal sensitivity is 8 LSB/°C.
9 Package information
specifications, grade definitions and product status are available at: www.st.com.
9.1 LGA-12 package information
Figure 9. LGA-12 2.0 x 2.0 x 0.7 mm package outline and mechanical data
9.2 LGA-12 packing information
Figure 10. Carrier tape information for LGA-12 package Figure 11. LGA-12 package orientation in carrier tape
Figure 12. Reel information for carrier tape of LGA-12 package Table 48. Reel dimensions for carrier tape of LGA-12 package
Table 49. Document revision history