LIS2DW STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 63
Technical content
Datasheet sections
- 1 Block diagram and pin descripti on
- 1.1 Block diagram
- 1.2 Pin description
- 2 Mechanical and electrical speci fications
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Temperature sensor characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I²C - inter-IC control interface
- 2.5 Absolute maximum ratings
- 3 Terminology and functionality
- 3.1 Terminology
- 3.1.1 Sensitivity
- 3.1.2 Zero-g level offset
- 3.2 Functionality
- 3.2.1 Operating modes
- 3.2.2 Single data conversion on demand mode
- 3.2.3 Self-test
- 3.2.4 Activity/Inactivity, Android stationary/motion detection f unctions
- 3.2.5 High tap/double-tap user configurability
- 3.2.6 Offset management
- 3.3 Sensing element
- 3.4 IC interface
- 3.5 Factory calibration
- 3.6 Temperature sensor
- 4 Application hints
- 5 Digital main blocks
- 5.1 Block diagram of filters
Datasheet sections
- 8.17 OUT_Z_H (2Dh)
- 8.18 FIFO_CTRL (2Eh)
- 8.19 FIFO_SAMPLES (2Fh)
- 8.20 TAP_THS_X (30h)
- 8.21 TAP_THS_Y (31h)
- 8.22 TAP_THS_Z (32h)
- 8.23 INT_DUR (33h)
- 8.24 WAKE_UP_THS (34h)
- 8.25 WAKE_UP_DUR ( 35h)
- 8.26 FREE_FALL (36h)
- 8.27 STATUS_DUP (37h)
- 8.28 WAKE_UP_SRC (38h)
- 8.29 TAP_SRC (39h)
- 8.30 SIXD_SRC (3Ah)
- 8.31 ALL_INT_SRC (3Bh)
- 8.32 X_OFS_USR (3Ch)
- 8.33 Y_OFS_USR (3Dh)
- 8.34 Z_OFS_USR (3Eh)
- 8.35 CTRL7 (3Fh)
- 9 Package information
- 9.1 Soldering information
- 9.2 LGA-14 package information
- 10 Revision history
Features
Ultra-low power consumption: 50 nA in power- down mode, below 1 µA in active low-power mode Very low noise: down to 1.3 mg RMS in low- power mode Multiple operating modes with multiple bandwidths Android stationary detection, motion detection Supply voltage, 1.62 V to 3.6 V Independent IO supply 2g/4g/8g/16g full scale High-speed I²C/SPI digital output interface Single data conversion on demand 16-bit data output Embedded temperature sensor Self-test 32-level FIFO 10000 g high shock survivability ECOPACK, RoHS and “Green” compliant
Applications
Motion detection for wearables Gesture recognition and gaming Motion-activated functions and user interfaces Display orientation Tap/double-tap recognition Free-fall detection Smart power saving for handheld devices Hearing aids Portable healthcare devices Wireless sensor nodes Motion-enabled metering devices
Description
The LIS2DW is an ultra-low-power, high performance three-axis linear accelerometer belonging to the “femto” family which leverages on the robust and mature manufacturing processes already used for the production of micromachined accelerometers. The LIS2DW has user-selectable full scales of 2g/4g/8g/16g and is capable of measuring accelerations with output data rates from 1.6 Hz to 1600 Hz. The LIS2DW has an integrated 32-level first-in, first-out (FIFO) buffer allowing the user to store data in order to limit intervention by the host processor. The embedded self-test capability allows the user to check the functioning of the sensor in the final application. The LIS2DW has a dedicated internal engine to process motion and acceleration detection including free-fall, wakeup, highly configurable single/double-tap recognition, activity/inactivity, stationary/motion detection, portrait/landscape detection and 6D/4D orientation. The LIS2DW is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. /*$ [[PP Table 1. Device summary
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections Table 2. Pin description
1 SCL
- SDO/SA0 and CS pins are inte rnally pulled up. Refer to Table 3 for the internal pull-up values (typ).
6 INT1 Interrupt pin 1
7 Vdd_IO Power supply for I/O pins
8 Vdd Power supply
9 GND 0 V supply
10 Res Connect to GND
11 Res Connect to GND
Table 3. Internal pull-up values (typ.) for SDO/SA0 and CS pins
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 4. Mechanical characteristics @ Vdd = 1.8 V, T = 25 °C unless otherwise noted(1)
- Typical specifications are not guaranteed.
- Noise density is the same for al l ODRs. Low-noise setting enabled.
- RMS noise is the same for all ODRs. Low-noise setting enabled.
- Values after factory calibration test and trimming.
2.2 Electrical c haracteristics
Table 5. Electrical characteristics @ Vdd = 1.8 V, T = 25 °C unless otherwise noted (1)
12.5 Hz - 1600 Hz,
- Typical specifications are not guaranteed.
- It is possible to remove Vdd maintaining Vdd_IO without block ing the communication busses. In this condition the
measurement chain is powered off.
- Low-noise setting disabled.
- Low-Power Mode 1. Low-noise setting disabled.
- 4 mA is the maximum driving capability, ie. the maximum DC current that can be sourced/sunk by the digital pad in order to
2.3 Temperature sens or characteristics
Table 6. Temperature sensor characteristics
- Typical specifications are not guaranteed.
- The output of the temperature sensor is 0 LSB (typ.) at 25 °C .
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram Table 7. SPI slave timing values
- 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
2.4.2 I ²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Figure 4. I²C slave timing diagram Note: Measurement points are done at 0.2 ꞏVdd_IO and 0.8ꞏVdd_IO, for both ports. Table 8. I²C slave timing values
- Data based on standard I²C protocol requirement, not tested i n production
Table 9. I²C high-speed mode specifications at 1 MHz and 3.4 MHz
- Data based on characterization, not tested in production
2.5 Absolute maximum ratings
Note: Supply voltage on any pin should never exceed 4.8 V. Table 10. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
LIS2DW Terminology and functionality
3 Terminology and functionality
3.1 Terminology
3.1.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
3.1.2 Zero- g level offset
Zero-g level offset describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on the X-axis and 0 g on the Y-axis whereas the Z-axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from ideal value in this case is called Zero-g level offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level offset change vs. temperature”.
3.2 Functionality
3.2.1 Operating modes
Writing the LOW_NOISE bit in CTRL6 (25h) selects the operating mode (low-noise). Table 11. Operating modes - low-noise setting disabled
3.2.2 Single data con version on demand mode
selected by writing the LP_MODE[1:0] bits in CTRL1 (20h). the INT2 pin (see Figure 5). this bit is automatically set to '0' and the device is ready for another triggered session. Output data are generated according to the selected low-power mode. mode and waits for a new trigger. All ODRs in the range from 0 up to 200 Hz are supported due to the INT2 clock input. A DRDY signal or FIFO flags are available on the INT1 pin. Power consumption is the same as that of standard low-power modes for the same ODR. Table 12. Operating modes - low-noise setting enabled
Figure 5. Single data conversion on demand functionality
3.2.3 Self-test
changed, an actuation force is applied to the sensor, simulating a definite input acceleration. of the interface chip are within the defined specifications.
LIS2DW Terminology and functionality
3.2.4 Activity/Inactivity, Androi d stationary/motion detection functions
The activity/inactivity function recognizes the device’s sleep state and allows reducing system power consumption. When the activity/inactivity function is activated by setting the SLEEP_ON bit in WAKE_UP_THS (34h), the LIS2DW automatically goes to 12.5 Hz ODR in the low-power mode previously selected by the LP_MODE[1:0] bits in CTRL1 (20h) if the sleep state condition is detected and wakes up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. With this feature the system may be efficiently switched from low-power mode to full performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility. The Android stationary/motion detection function only recognizes the device’s sleep state. When the Android stationary/motion detection function is activated by setting the STATIONARY bit in WAKE_UP_DUR (35h), the LIS2DW detects acceleration below a fixed threshold but does not change either ODR or operating mode (High-Performance mode or Low-Power mode) after sleep state detection. The Activity/Inactivity recognition and Android stationary/motion detection functions are activated by writing the desired threshold in the WAKE_UP_THS (34h) register. The high- pass filter is automatically enabled. If the device is in sleep (inactivity/stationary) mode, when at least one of the axes exceeds the threshold in WAKE_UP_THS (34h), the device goes into a sleep-to-wake state (as wake-up). For the activity/inactivity function, the device, in a wake-up state, will return to the operating mode (HP or LP) and ODR before sleep state detection. Activity/Inactivity, Android stationary/motion detection threshold and duration can be configured in the following control registers: WAKE_UP_THS (34h) WAKE_UP_DUR (35h)
3.2.5 High tap/double-ta p user configurability
The device embeds the possibility to select the following parameters: single axis or multiple axes in TAP_THS_Z (32h) axis priority in TAP_THS_Y (31h) threshold value of each axis in TAP_THS_X (30h), TAP_THS_Y (31h), and TAP_THS_Z (32h) max time threshold between 2 consecutive taps for double-tap recognition, min time threshold between 2 consecutive taps to detect a new tap event in INT_DUR (33h)
3.2.6 Offset management
The user can manage offset in the output or for wakeup detection using dedicated embedded hardware (see Section 5.1: Block diagram of filters).
Terminology and functionality LIS2DW
3.3 Sensing element
A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. In order to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half- bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.
3.4 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter. The acceleration data may be accessed through an I²C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS2DW features a data-ready signal which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device.
3.5 Factory calibration
The IC interface is factory-calibrated for sensitivity (So) and Zero-g level offset. The trim values are stored inside the device in nonvolatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. This allows using the device without further calibration. If an accidental write occurs in the registers where trimming parameters are stored, the BOOT bit in CTRL2 (21h) can help to retrieve the correct trimming parameters from nonvolatile memory without the need to switch on/off the device. This bit is automatically reset at the end of the download operation. Setting this bit has no impact on the control registers.
3.6 Temperature sensor
The temperature is available in OUT_T_L (0Dh), OUT_T_H (0Eh) stored as two's complement data, left-justified in 12-bit mode and in OUT_T (26h) stored as two's complement data, left-justified in 8-bit mode. Refer to Table 6: Temperature sensor characteristics for the conversion factor.
4 Application hints
Figure 6. LIS2DW electrical connections (top view) be placed as near as possible to pin 8 of the device (common design practice). accessible through the I²C or SPI interfaces. When using the I²C, CS must be tied high (i.e. completely programmed by the user through the I²C/SPI interface.
Table 13. Internal pin status
3 SDO
6 INT1 Interrupt pin 1 Default: push-pull output forced to Gnd
- In order to disable the internal pull-up on the CS pin, write '1' to the CS_PU_DISC bit in CTRL2 (21h).
5 Digital main blocks
5.1 Block diagram of filters
Figure 7. Accelerometer chain HP_REF_MODE bit in CTRL7 (3Fh).
Table 14. Number of samples to be discarded
LIS2DW Digital main blocks
5.3 FIFO
The LIS2DW embeds 32 slots of 14-bit data FIFO for each of the three output channels, X, Y and Z of the acceleration data. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. The internal FIFO allows collecting 32 samples (14-bit size data) for each axis. When the FIFO mode is other than Bypass, reading the output registers (28h to 2Dh) returns the oldest FIFO sample set. In order to minimize communication between the master and slave, the address read may be automatically incremented by the device by setting the IF_ADD_INC bit of CTRL2 (21h) to '1'; the device rolls back to 0x28 when register 0x2D is reached. This buffer can work according to the following 5 different modes: Bypass mode FIFO mode Continuous Continuous-to-FIFO Bypass-to-Continuous Each mode is selected by the FMode[2:0] bits in the FIFO_CTRL (2Eh) register. Programmable FIFO threshold is selected in FIFO_CTRL (2Eh). Status and FIFO overrun events are available in the FIFO_SAMPLES (2Fh) register and can be used to generate dedicated interrupts on the INT1 and INT2 pins using the CTRL4_INT1_PAD_CTRL (23h) and CTRL5_INT2_PAD_CTRL (24h) registers. FIFO_SAMPLES (2Fh) (FIFO_FTH) goes to '1' when the number of unread samples FIFO_SAMPLES (2Fh) (Diff[5:0]) is greater than or equal to FTH[4:0] in FIFO_CTRL (2Eh). If FTH[4:0] is equal to '0', FIFO_SAMPLES (2Fh) (FIFO_FTH) goes to '0'. FIFO_SAMPLES (2Fh) (FIFO_OVR) is equal to '1' if a FIFO slot is overwritten. FIFO_SAMPLES (2Fh) (Diff[5:0]) contains stored data levels of unread samples. When Diff[5:0] is equal to ‘000000’, FIFO is empty. When Diff[5:0] is equal to ‘100000’, FIFO is full and the unread samples are 32. To guarantee the correct acquisition of data during the switching into and out of FIFO, the first sample acquired must be discarded. When the FIFO threshold status flag is '0'-logic, FIFO filling is lower than the threshold level and when '1'-logic, FIFO filling is equal to or higher than the threshold level.
Digital main blocks LIS2DW
5.3.1 Bypass mode
In Bypass mode (FIFO_CTRL (2Eh) (FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers. Bypass mode is also used to reset the FIFO when in FIFO mode. For each channel only the first address is used. When new data is available, the old data is overwritten.
5.3.2 FIFO mode
In FIFO mode (FIFO_CTRL (2Eh)(FMode [2:0])= 001) data from the X, Y and Z channels are stored in the FIFO until it is full, when 32 unread samples are stored in memory, data collecting is stopped. To reset the FIFO content, Bypass mode should be written in the FIFO_CTRL (2Eh) register, setting the FMODE [2:0] bits to '000'. After this reset command, it is possible to restart FIFO mode, writing the value '001' in FIFO_CTRL (2Eh)(FMODE [2:0]). The FIFO buffer can memorize 32 slots of X, Y and Z data.
5.3.3 Continuous mode
Continuous mode (FIFO_CTRL (2Eh) (FMode[2:0] = 110) provides a continuous FIFO update: when 32 unread samples are stored in memory, as new data arrives the oldest data is discarded and overwritten by the newer. A FIFO threshold flag FIFO_SAMPLES (2Fh) (FIFO_FTH) is asserted when the number of unread samples in FIFO is greater than or equal to (FIFO_CTRL (2Eh)FTH[4:0]). It is possible to route FIFO_SAMPLES (2Fh)(FTH) to the INT1 pin by writing the INT1_FTH bit to '1' in register CTRL4_INT1_PAD_CTRL (23h) or to the INT2 pin by writing the INT2_FTH bit to '1' in register CTRL5_INT2_PAD_CTRL (24h). If an overrun occurs, the oldest sample in FIFO is overwritten and the FIFO_OVR flag in FIFO_SAMPLES (2Fh) is asserted. In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in FIFO_SAMPLES (2Fh) (Diff[5:0]).
5.3.4 Continuous-to-FIFO mode
corresponding pad to be used as a trigger. Figure 8. Continuous-to-FIFO mode Figure 9. Trigger event to FIFO for Continuous-to-FIFO mode
5.3.5 Bypass-to-Continuous mode
has to be routed on the corresponding pad to be used as a trigger. Figure 10. Bypass-to-Continuous mode Figure 11. Trigger event to FIFO for Bypass-to-Continuous mode
6 Digital interfaces
CS line must be tied high (i.e. connected to Vdd_IO).
6.1 I ²C serial interface
content can also be read back. The relevant I²C terminology is given in the table below. up resistor. When the bus is free, both the lines are high. In order to disable the I²C block, CTRL2 (21h) (I2C_DISABLE) = 1 must be set. Table 15. Serial interface pin description Table 16. I²C terminology
6.1.1 I ²C operation
different accelerometers to the same I²C lines.
7 LSb represents the actual register address while the CTRL2 (21h) (IF_ADD_INC) bit
defines the address increment. SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 17. SAD+Read/Write patterns
terminated by the generation of a STOP (SP) condition. Table 18. Transfer when master is writing one byte to slave Table 19. Transfer when master is writing multiple bytes to slave Table 20. Transfer when master is receiving (reading) one byte of data from slave Table 21. Transfer when master is receiving (reading) multiple bytes of data from slave
6.2 SPI bus interface
The serial interface interacts with the application using 4 wires: CS, SPC, SDI and SDO. Figure 12. Read and write protocol falling edge of SPC and should be captured at the rising edge of SPC. from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
6.2.1 SPI read
Figure 13. SPI read protocol performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. Figure 14. Multiple byte SPI read protocol (2-byte example)
6.2.2 SPI write
Figure 15. SPI write protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1 -7: address AD(6:0). This is the address field of the indexed register. Figure 16. Multiple byte SPI write protocol (2-byte example)
6.2.3 SPI read in 3-wire mode
Figure 17. SPI read protocol in 3-wire mode bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
7 Register mapping
Table 22. Register map
permanent damage to the device.
- R = read-only register, R/W = readable/writable register
Table 22. Register map (continued)
8 Register description
8.1 OUT_T_L (0Dh)
Temperature output register in 12-bit resolution (r).
8.2 OUT_T_H (0Eh)
Temperature output register in 12-bit resolution (r).
8.3 WHO_AM_I (0Fh)
Who_AM_I register (r). This register is a read-only register. Its value is fixed at 44h. Table 23. OUT_T_L register Table 24. OUT_T_L register description TEMP[3:0] The 8 least significant bits of the temperature sensor output. Sensitivity = 16 LSB/°C. Table 25. OUT_T_H register Table 26. OUT_T_H register description TEMP[11:4] The 8 most significant bits of the temperature sensor output. Sensitivity = 16 LSB/°C. Table 27. WHO_AM_I register default values
8.4 CTRL1 (20h)
Table 28. Control register 1 Table 29. Control register 1 description settings for power-down mode and each available frequency. Table 30. Data rate configuration Table 31. Mode selection Table 32. Low-power mode selection
0000 Power-down
0011 High-Performance / Low-Power mode 25 Hz
0100 High-Performance / Low-Power mode 50 Hz
0101 High-Performance / Low-Power mode 100 Hz
0110 High-Performance / Low-Power mode 200 Hz
0111 High-Performance / Low-Power mode 400/200 Hz
1000 High-Performance / Lo w-Power mode 800/200 Hz
1001 High-Performance / Low-Power mode 1600/200 Hz
00 Low-Power mode (12/14-bit resolution)
01 High-Performance mode (14-bit resolution)
10 Single data conver sion on demand mode (12/14-bit resolution)
00 Low-Power Mode 1 (12-bit resolution)
01 Low-Power Mode 2 (14-bit resolution)
10 Low-Power Mode 3 (14-bit resolution)
11 Low-Power Mode 4 (14-bit resolution)
8.5 CTRL2 (21h)
Table 33. Control register 2 Table 34. Control register 2 description
- This bit must be set to ‘0’ fo r the correct operation of the device.
into registers where trimming parameters are stored. Once the operation is over, this bit automatically returns to 0. SOFT_RESET Soft reset acts as reset for all control registers, then goes to 0.
8.6 CTRL3 (22h)
Table 35. Control register 3 Table 36. Control register 3 description function source signals and interrupts routed to pins (wakeup, single/double-tap). 1: enabled by I²C/SPI writing SLP_MODE_1 to 1. ready for another triggered session. Table 37. Self-test mode selection
8.7 CTRL4_INT1_PAD_CTRL (23h)
Table 38. Control register 4 Table 39. Control register 4description
8.8 CTRL5_INT2_PAD_CTRL (24h)
Table 40. Control register 5 Table 41. Control register 5 description
8.9 CTRL6 (25h)
Table 42. Control register 6 Table 43. Control register 6 description Table 44. Digital filtering cutoff selection Table 45. Full-scale selection
8.10 OUT_T (26h)
Table 46. OUT_T register Table 47. OUT_T register description LOW_NOISE Low-noise configuration.
00 ODR/2 (up to ODR = 800 Hz, 400 Hz when ODR = 1600 Hz)
01 ODR/4 (HP/LP)
10 ODR/10 (HP/LP)
11 ODR/20 (HP/LP)
Temperature sensor output data. 0 LSB represents T=25 °C ambient.
8.11 STATUS (27h)
Table 48. STATUS register Table 49. STATUS register description
8.12 OUT_X_L (28h)
X-axis LSB output register (r). Table 50. OUT_X_L register WU_IA Wakeup event detection status. 6D_IA Source of change in position portrait/landscape/face-up/face-down. FF_IA Free-fall event detection status.
- If Low-Power Mode 1 is enabled, this bit is set to 0.
8.13 OUT_X_H (29h)
X-axis MSB output register (r). Table 51. OUT_X_H register
8.14 OUT_Y_L (2Ah)
Y-axis LSB output register (r). Table 52. OUT_Y_L register
8.15 OUT_Y_H (2Bh)
Y-axis MSB output register (r). Table 53. OUT_Y_H register
8.16 OUT_Z_L (2Ch)
Z-axis LSB output register (r). Table 54. OUT_Z_L register
- If Low-Power Mode 1 is enabled, this bit is set to 0.
- If Low-power Mode 1 is enabled, this bit is set to 0.
8.17 OUT_Z_H (2Dh)
Z-axis MSB output register (r). Table 55. OUT_Z_H register
8.18 FIFO_CTRL (2Eh)
FIFO control register (r/w). Table 56. FIFO_CTRL register Table 57. FIFO_CTRL register description FTH[4:0] FIFO threshold level setting. Table 58. FIFO mode selection
000 Bypass mode: FIFO turned off
001 FIFO mode: Stops collecting data when FIFO is full.
010 Reserved
011 Continuous-to-FIFO: Stream m ode until trigger is deasserted, then FIFO mode
100 Bypass-to-Continuous: Bypass mode until trigger is deasserted, then FIFO mode
101 Reserved
110 Continuous mode: If the FIFO i s full, the new sample overwrites the older sample.
111 Reserved
8.19 FIFO_SAMPLES (2Fh)
FIFO_SAMPLES control register (r). Table 59. FIFO_SAMPLES register Table 60. FIFO_SAMPLES register description
8.20 TAP_THS_X (30h)
4D configuration enable and TAP threshold configuration (r/w). Table 61. TAP_THS_X register Table 62. TAP_THS_X register description Table 63. 4D/6D threshold setting FS @ ±2 g Diff[5:0] Represents the number of unread samples stored in FIFO. (000000 = FIFO empty; 100000 = FIFO full, 32 unread samples). 4D detection portrait/landscape position enable. 1: portrait/landscape detection and face-up/face-down position enabled).
8.21 TAP_THS_Y (31h)
Table 64. TAP_THS_Y register Table 65. TAP_THS_Y register description Table 66. Selection of axis priority for tap detection
8.22 TAP_THS_Z (32h)
Table 67. TAP_THS_Z register Table 68. TAP_THS_Z register description TAP_PRIOR_[2:0] Selection of prior ity axis for tap detection (see Table 66). TAP_THSY_[4:0] Threshold for tap recognition @ FS = ±2 g on Y direction.
000 X Y Z
001 Y X Z
010 X Z Y
011 Z Y X
100 X Y Z
101 Y Z X
110 Z X Y
111 Z Y X
TAP_X_EN Enables X direction in tap recognition. TAP_Y_EN Enables Y direction in tap recognition. TAP_Z_EN Enables Z direction in tap recognition. TAP_THSZ_[4:0] Threshold for tap recognition @ FS = ±2 g on Z direction.
8.23 INT_DUR (33h)
Interrupt duration register (r/w). Table 69. INT_DUR register Table 70. INT_DUR register description
8.24 WAKE_UP_THS (34h)
Wakeup threshold register (r/w). Table 71. WAKE_UP_THS register Table 72. WAKE_UP_THS register description successive detected taps to determine a double-tap event.
1 LSB = 32 * 1/ODR
first detected tap in which there must not be any overthreshold event.
1 LSB = 4 * 1/ODR
time of an over-threshold signal detection to be recognized as a tap event.
1 LSB = 8 * 1/ODR
8.25 WAKE_UP_DUR (35h)
Wakeup and sleep duration configuration register (r/w). Table 73. WAKE_UP_DUR register Table 74. WAKE_UP_DUR register description
8.26 FREE_FALL (36h)
Free-fall duration and threshold configuration register (r/w). Table 75. FREE_FALL register Table 76. FREE_FALL register description Table 77. FREE_FALL threshold decoding @ ±2 g FS Duration to go in sleep mode.
1 LSB = 512 * 1/ODR
8.27 STATUS_DUP (37h)
Event detection status register (r). Table 78. STATUS_DUP register Table 79. STATUS_DUP register description 6D_IA Source of change in position portrait/landscape/face-up/face-down. FF_IA Free-fall event detection status.
8.28 WAKE_UP_SRC (38h)
Table 80. WAKE_UP_SRC register Table 81. WAKE_UP_SRC register description
8.29 TAP_SRC (39h)
Table 82. TAP_SRC register Table 83. TAP_SRC register description
00 F F _ I A SLEEP_
FF_IA Free-fall event detection status. WU_IA Wakeup event detection status. X_WU Wakeup event detection status on X-axis. Y_WU Wakeup event detection status on Y-axis. Z_WU Wakeup event detection status on Z-axis.
0 TAP_IA SINGLE_
SINGLE_TAP Single-tap event status. DOUBLE_TAP Double-tap event status. TAP_SIGN Sign of acceleration detected by tap event. X_TAP Tap event detection status on X-axis. Y_TAP Tap event detection status on Y-axis. Z_TAP Tap event detection status on Z-axis.
8.30 SIXD_SRC (3Ah)
Table 84. SIXD_SRC register Table 85. SIXD_SRC register description
8.31 ALL_INT_SRC (3Bh)
Table 86. ALL_INT_SRC register Table 87. ALL_INT_SRC register description 6D_IA Source of change in position portrait/landscape/face-up/face-down.
00 SLEEP_
6D_IA Source of change in position portrait/landscape/face-up/face-down. DOUBLE_TAP Double-tap event status. WU_IA Wakeup event detection status. FF_IA Free-fall event detection status.
8.32 X_OFS_USR (3Ch)
Table 88. X_OFS_USR Table 89. X_OFS_USR register description
8.33 Y_OFS_USR (3Dh)
Table 90. Y_OFS_USR register Table 91. Y_OFS_USR register description
8.34 Z_OFS_USR (3Eh)
Table 92. Z_OFS_USR register Table 93. Z_OFS_USR register description X_OFS_USR_[7:0] Two's complement user offset value on X-axis data, used for wakeup function. Y_OFS_USR_[7:0] Two's complement user offset value on Y-axis data, used for wakeup function. Z_OFS_USR_[7:0] Two's complement user offset value on Z-axis data, used for wakeup function.
8.35 CTRL7 (3Fh)
Table 94. CTRL7 register Table 95. CTRL7 register description Switches between latched and pulsed mode for data ready interrupt. INT2_ON_INT1 Signal routing. Enable application of user offset value on XL output data registers. FDS bit in CTRL6 (25h) must be set to '0'-logic (low-pass path selected). _ON_WU Enable application of user offset value on XL data for wakeup function only. Y_OFS_USR_[7:0] and Z_OFS_USR_[7:0] bits. High-pass filter reference mode enable.
9 Package information
specifications, grade definitions and product status are available at: www.st.com.
9.1 Soldering information
The LGA package is compliant with the ECOPACK, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com.
9.2 LGA-14 package information
Figure 18. LGA-14 2x2x0.70 mm package outline and mechanical data
Table 96. Document revision history