LIS2DH STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Mechanical and electrical specifications
- 2.1 Mechanical characteristics
- 2.2 Temperature sensor characteristics
- 2.3 Electrical characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I 2C - inter IC control interface
- 2.5 Absolute maximum ratings
- 2.6 Terminology and functionality
- 2.6.1 Sensitivity
- 2.6.2 Zero-g level
- 2.6.3 High resolution, normal mode, low power mode
- 2.6.4 Self-test
- 2.7 Sensing element
- 2.8 IC interface
- 2.9 Factory calibration
- 2.10 FIFO
- 2.11 Temperature sensor
- 3 Application hints
- 3.1 Soldering information
- 4 Digital main blocks
- 4.1 FIFO
- 4.1.1 Bypass mode
Datasheet sections
- 7.20 INT1_SRC (31h)
- 7.21 INT1_THS (32h)
- 7.22 INT1_DURATION (33h)
- 7.23 INT2_CFG (34h)
- 7.24 INT2_SRC (35h)
- 7.25 INT2_THS (36h)
- 7.26 INT2_DURATION (37h)
- 7.27 CLICK_CFG (38h)
- 7.28 CLICK_SRC (39h)
- 7.29 CLICK_THS (3Ah)
- 7.30 TIME_LIMIT (3Bh)
- 7.31 TIME_LATENCY (3Ch)
- 7.32 TIME WINDOW(3Dh)
- 7.33 Act_THS(3Eh)
- 7.34 Act_DUR (3Fh)
- 8 Package information
- 9 Revision history
Features
■ Wide supply voltage, 1.71 V to 3.6 V ■ Independent IOs supply (1.8 V) and supply voltage compatible ■ Ultra low-power mode consumption down to 2 µA ■ ±2g/±4g/±8g/±16g dynamically selectable full- scale ■ I2C/SPI digital output interface ■ 2 independent programmable interrupt generators for free-fall and motion detection ■ 6D/4D orientation detection ■ “Sleep to wake” and “return to sleep” function ■ Freefall detection ■ Motion detection ■ Embedded temperature sensor ■ Embedded FIFO ■ ECOPACK® RoHS and “Green” compliant
Applications
■ Motion activated functions ■ Display orientation ■ Shake control ■ Pedometer ■ Gaming and virtual reality input devices ■ Impact recognition and logging
Description
The LIS2DH is an ultra low-power high performance three-axis linear accelerometer belonging to the “femto” family, with digital I 2C/SPI serial interface standard output. The LIS2DH has dynamically user selectable full scales of ±2g/±4g/±8g/±16g and it is capable of measuring accelerations with output data rates from 1 Hz to 5.3 kHz. The self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself. The LIS2DH is available in small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. LGA-14 (2.0x2.0x1 mm) Table 1. Device summary
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connection
32 Level
Table 2. Pin description
1 SCL
3 SDO
5 INT2 Intterupt pin 2
6 INT1 Intterupt pin 1
7 Vdd_IO Power supply for I/O pins
8 Vdd Power supply
9 GND 0 V supply
10 Res Connect to GND
11 Res Connect to GND
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics
2.2 Temperature sensor characteristics
- Typical specificat ions are not guaranteed.
- Verified by wafer level test and measur ement of initial offset and sensitivity.
- Typical zero- g level offset value after MSL3 preconditioning.
- Offset can be eliminated by enablin g the built-in high pass filter.
- The sign of “Self-test out put change” is defined by CTRL_REG4 ST bit, for all axes.
- “Self-test output change” is defined as the absolute value of:
- After enabling ST, correct data is obtained after two samples ( Low power mode / Normal mode) or after eight samples (high
Table 3. Mechanical characteristics (continued) Table 4. Temperature sensor characteristics
- Typical specificat ions are not guaranteed.
- Refer to Table 28: Data rate configuration.
2.3 Electrical characteristics
Table 5. Electrical characteristics
- Typical specification are not guaranteed.
- It is possible to remove Vdd maintaining Vdd_IO withou t blocking the communication busses, in this condition the
measurement chain is powered off.
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram (d)
- When no communication is on-going, data on SDO is driven by internal pull-up resistors
Table 6. SPI slave timing values
- Values are guaranteed at 10 MHz clock fr equency for SPI with both 4 and 3 wires, based on characterization results, not
d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port.
2.4.2 I 2C - Inter IC control interface
Subject to general operating conditions for Vdd and top. Figure 4. I 2C Slave timing diagram (e) Table 7. I 2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
- Cb = total capacitance of one bus line, in pF.
e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port.
2.5 Absolute maximum ratings
Table 8. Absolute maximum ratings
2.6 Terminology and functionality
2.6.1 Sensitivity
the range of Sensitivities of a large population of sensors.
2.6.2 Zero- g level
standard deviation of the range of Zero-g levels of a population of sensors.
2.6.3 High resolution, Normal mode, Low power mode
resolution mode, Normal mode and Low power mode. The table below reported summarizes how to select among the different operating modes. Table 9. Operating mode selection
2.6.4 Self-test
and the parameters of the interface chip are within the defined specifications. Table 10. Turn-on time for Table 11. Operating modes current consumption
Mechanical and electrical specifications LIS2DH 18/49 Doc ID 022516 Rev 1 2.6.5 6D / 4D orientation detection The LIS2DH include 6D / 4D orientation detection. 6D / 4D orientation recognition In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration Z axis position detection is disable. 2.6.6 “Sleep to wake” and “Return to sleep” The LIS2DH can be programmed to automatically switch to Low power mode upon recognition of a determined event. Once the event condition is over, the device returns back to the preset Normal or High resolution mode. To enable this function the desired threshold value must be stored inside Act_THS(3Eh) registers while the duration value written inside Act_DUR(3Fh) registers. When acceleration module becomes lower than the treshold value, the device automatically switches to Low power mode (10Hz ODR). During this condition, ODRx bits and LPen bit inside CTRL_REG1 (20h) and HR bit in CTRL_REG3 (22h) are not considered. As soon as the acceleration goes back over the threshold, the systems restores the operating mode and ODRs as for CTRL_REG1 (20h) and CTRL_REG3 (22h) settings.
2.7 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows carring out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in the fF range.
2.8 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by an analog-to-digital converter. The acceleration data may be accessed through an I 2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS2DH features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device.
LIS2DH Mechanical and electrical specifications Doc ID 022516 Rev 1 19/49 The LIS2DH may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free- Fall and Wake-Up can be available simultaneously on two different pins.
2.9 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows to use the device without further calibration.
2.10 FIFO
The LIS2DH contains a 10 bit, 32-level FIFO. Buffered output allows 4 operation modes: FIFO, stream, trigger and FIFO ByPass. Where FIFO bypass mode is activated FIFO is not operating and remains empty. In FIFO mode, data from acceleration detection on x, y, and z- axes measurements are stored in FIFO.
2.11 Temperature sensor
The LIS2DH is supplied with an internal temperature sensor. Temperature data can be enabled by setting the TEMP_EN bit of the TEMP_CFG_REG register to 1. To retrieve the temperature sensor data BDU bit on CTRL_REG4 (23h) must be set to ‘1’. Both OUT_TEMP_H and OUT_TEMP_L registers must be read. Temperature data is stored inside OUT_TEMP_H as 2’s complement data in 8 bit format left justified.
3 Application hints
Figure 5. LIS2DH electrical connection be placed as near as possible to the pin 8 of the device (common design practice). 2C or SPI interfaces.When using the I2C, CS must be tied high. completely programmed by the user through the I2C/SPI interface.
3.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering.
LIS2DH Digital main blocks Doc ID 022516 Rev 1 21/49
4 Digital main blocks
4.1 FIFO
The LIS2DH embeds a 32-slot data FIFO for each of the three output channels, X, Y and Z. This allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wakeup only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to four different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits into the FIFO_CTRL_REG (2E). Programmable Watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on INT1/2 pin (configuration through FIFO_CFG_REG).
4.1.1 Bypass mode
In bypass mode, the FIFO is not operational and for this reason it remains empty. As described in the next figure, for each channel only the first address is used. The remaining FIFO slots are empty.
4.1.2 FIFO mode
In FIFO mode, data from X, Y and Z channels are stored into the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG (2E) in order to be raised when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG (2E). The FIFO continues filling until it is full (32 slots of data for X, Y and Z). When full, the FIFO stops collecting data from the input channels.
4.1.3 Stream mode
In the stream mode, data from X, Y and Z measurement are stored into the FIFO. A watermark interrupt can be enabled and set as in the FIFO mode.The FIFO continues filling until it’s full (32 slots of data for X, Y and Z). When full, the FIFO discards the older data as the new arrive.
4.1.4 Stream-to-FIFO mode
In Stream-to_FIFO mode, data from X, Y and Z measurement are stored into the FIFO. A watermark interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG) in order to be raised when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits of FIFO_CTRL_REG. The FIFO continues filling until it’s full (32 slots of 10 bit for for X, Y and Z). When full, the FIFO discards the older data as the new arrive. Once trigger event occurs, the FIFO starts operating in FIFO mode.
4.1.5 Retrieve data from FIFO
FIFO data is read through OUT_X (Addr reg 29h), OUT_Y (Addr reg 2Bh) and OUT_Z (Addr reg 2Dh). When the FIFO is in stream, Trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z regiters provides the data stored into the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed into the OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst operations can be used.
Digital main blocks LIS2DH 22/49 Doc ID 022516 Rev 1 The reading address is automatically updated by the device and it rolls back to 0x28 when register 0x2D is reached. In order to read all FIFO levels in a multiple byte reading,192 bytes (6 output registers by 32 levels) have to be read.
5 Digital interfaces
line must be tied high (i.e. connected to Vdd_IO).
5.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. resistor. When the bus is free both the lines are high. Table 12. Serial interface pin description Table 13. Serial interface pin description
5.1.1 I 2C operation
SAD+read/write bit pattern is composed, listing all the possible configurations. Table 14. SAD+read/write patterns Table 15. Transfer when master is writing one byte to slave
terminated by the generation of a STOP (SP) condition. address of first register to be read.
5.2 SPI bus interface
The LIS2DH SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Table 16. Transfer when master is writing multiple bytes to slave: Table 17. Transfer when master is receiving (reading) one byte of data from slave: Table 18. Transfer when Master is receiving (reading) multiple bytes of data from slave
Figure 6. Read and write protocol falling edge of SPC and should be captured at the rising edge of SPC. from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). is ‘1’ the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 7. SPI read protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Figure 8. Multiple bytes SPI read protocol (2 bytes example)
5.2.2 SPI write
Figure 9. SPI write protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 10. Multiple bytes SPI write protocol (2 bytes example)
5.2.3 SPI read in 3-wires mode
Figure 11. SPI read protocol in 3-wires mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Multiple read command is also available in 3-wires mode.
6 Register mapping
Table 19. Register address map
writing to those registers may cause permanent damages to the device. Boot procedure is complete about 5 milliseconds just after powered up the device. Table 19. Register address map (continued)
7 Registers Description
7.1 STATUS_AUX (07h)
7.2 OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)
enable and read the temperature sensor output data.
7.3 INT_COUNTER (0Eh)
7.4 WHO_AM_I (0Fh)
Device identification register.
7.5 TEMP_CFG_REG (1Fh)
Table 20. STATUS_REG_AUX register Table 21. STATUS_REG_AUX description Table 22. INT_COUNTER register Table 23. WHO_AM_I register Table 24. TEMP_CFG_REG register
7.6 CTRL_REG1 (20h)
Table 25. TEMP_CFG_REG description Table 26. CTRL_REG1 register Table 27. CTRL_REG1 description Table 28. Data rate configuration
7.7 CTRL_REG2 (21h)
7.8 CTRL_REG3 (22h)
Table 29. CTRL_REG2 register Table 30. CTRL_REG2 description HPCLICK High Pass filter enabled for CLICK function. Table 31. High pass filter mode configuration Table 32. CTRL_REG3 register Table 33. CTRL_REG3 description I1_CLICK CLICK interrupt on INT1 pin. Default value 0. I1_AOI1 AOI1 interrupt on INT1 pn. Default value 0.
7.9 CTRL_REG4 (23h)
I1_AOI2 AOI2 interrupt on INT1 pin. Default value 0. I1_DRDY1 DRDY1 interrupt on INT1 pin. Default value 0. I1_DRDY2 DRDY2 interrupt on INT1 pin. Default value 0. I1_WTM FIFO Watermark interrupt on INT1 pin. Default value 0. I1_OVERRUN FIFO Overrun interrupt on INT1 pin. Default value 0. Table 33. CTRL_REG3 description (continued) Table 34. CTRL_REG4 register
- BLE function can be activated only in High Resolution mode
Table 35. CTRL_REG4 description (0: 4-wire interface; 1: 3-wire interface). Table 36. Self test mode configuration
7.10 CTRL_REG5 (24h)
7.11 CTRL_REG6 (25h)
Table 37. CTRL_REG5 register Table 38. CTRL_REG5 description reading INT1_SRC itself. Default value: 0. reading INT2_SRC itself. Default value: 0. Table 39. CTRL_REG6 register Table 40. CTRL_REG6 description P2_ACT Activity interrupt enable on INT2 pin. Default value: 0. H_LACTIVE interrupt active. Default value: 0.
7.12 REFERENCE/DATACAPTURE (26h)
7.13 STATUS_REG (27h)
7.14 OUT_X_L (28h), OUT_X_H (29h)
X-axis acceleration data. The value is expressed as two’s complement left justified. Please refer to Section 2.6.3: High resolution, Normal mode, Low power mode. Table 41. REFERENCE register Table 42. REFERENCE register description Table 43. STATUS register Table 44. STATUS register description
7.15 OUT_Y_L (2Ah), OUT_Y_H (2Bh)
Y -axis acceleration data. The value is expressed as two’s complement left justified. Please refer to Section 2.6.3: High resolution, Normal mode, Low power mode.
7.16 OUT_Z_L (2Ch), OUT_Z_H (2Dh)
Z-axis acceleration data. The value is expressed as two’s complement left justified. Please refer to Section 2.6.3: High resolution, Normal mode, Low power mode.
7.17 FIFO_CTRL_REG (2Eh)
7.18 FIFO_SRC_REG (2Fh)
Table 45. FIFO_CTRL_REG register Table 46. FIFO_CTRL_REG register description Table 47. FIFO mode configuration Table 48. FIFO_SRC register
7.19 INT1_CFG (30h)
Content of this register is loaded at boot. Write operation at this address is possible only after system boot. Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. unknown zone to known zone. The interrupt signal stay for a duration ODR. known zone. The interrupt signal stay untill orientation is inside the zone. Table 49. INT1_CFG register Table 50. INT1_CFG description Table 51. Interrupt mode
7.20 INT1_SRC (31h)
Interrupt 1 source register. Read only register. allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
7.21 INT1_THS (32h)
Table 52. INT1_SRC register
0 I A Z HZ LY HY LX HX L
Table 53. INT1_SRC description Table 54. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 55. INT1_THS description
7.22 INT1_DURATION (33h)
steps and maximum values depend on the ODR chosen. Duration time is measured in N/ODR, where N is the content of the duration register.
7.23 INT2_CFG (34h)
Table 56. INT1_DURATION register
0 D 6D 5D 4D 3D 2D 1D 0
Table 57. INT1_DURATION description
1 LSb = 1/ODR
Table 58. INT2_CFG register Table 59. INT2_CFG description AOI AND/OR combination of interrupt events. Default value: 0.
Content of this register is loaded at boot. Write operation at this address is possible only after system boot. Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. unknown zone to known zone. The interrupt signal stay for a duration ODR. known zone. The interrupt signal stay untill orientation is inside the zone.
7.24 INT2_SRC (35h)
Table 60. Interrupt mode Table 59. INT2_CFG description (continued) Table 61. INT2_SRC register Table 62. INT2_SRC description
Interrupt 2 source register. Read only register. allows the refreshment of data in the INT2_SRC register if the latched option was chosen.
7.25 INT2_THS (36h)
7.26 INT2_DURATION (37h)
time steps and maximum values depend on the ODR chosen. Table 62. INT2_SRC description (continued) Table 63. INT2_THS register Table 64. INT2_THS description Table 65. INT2_DURATION register Table 66. INT2_DURATION description
1 LSb = 1/ODR(1)
- Duration time is measured in N/ODR, where N is the content of the duration register.
7.27 CLICK_CFG (38h)
7.28 CLICK_SRC (39h)
Table 67. CLICK_CFG register Table 68. CLICK_CFG description Table 69. CLICK_SRC register Table 70. CLICK_SRC description
7.29 CLICK_THS (3Ah)
7.30 TIME_LIMIT (3Bh)
7.31 TIME_LATENCY (3Ch)
7.32 TIME WINDOW(3Dh)
Table 70. CLICK_SRC description (continued) Table 71. CLICK_THS register Table 72. CLICK_SRC description Table 73. TIME_LIMIT register Table 74. TIME_LIMIT description Table 75. TIME_LATENCY register Table 76. TIME_LATENCY description Table 77. TIME_WINDOW register
7.33 Act_THS(3Eh)
7.34 Act_DUR (3Fh)
Table 78. TIME_WINDOW description Table 79. TIME_WINDOW register Table 80. TIME_WINDOW description Table 81. Act_DUR register Table 82. Act_DUR description
8 Package information
specifications, grade definitions and product status are available at: www.st.com. Figure 12. LGA-14 2x2x1 mechanical drawing Table 83. LGA-14 2x2x1 mechanical dimensions
9 Revision history
Table 84. Document revision history 25-Nov-2011 1 Initial release.
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