LIS25BA STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 32
Technical content
Datasheet sections
- 1 Pin description
- 2 Mechanical and electrical specifications
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Absolute maximum ratings
- 3 TDM interface characteristics
- 3.1 I²C interface characteristics
- 4 TDM interface specifications
- 4.1 TDM interface overview
- 4.2 Frame synchronization (WCLK)
- 4.3 Serial clock (BCLK)
- 4.4 TDM axes mapping
- 4.5 TDM configurations
- 4.5.1 Configuration
- 4.5.2 Configuration
- 4.5.3 Configuration
- 4.5.4 Configuration
- 4.6 TDM clocks and MCLK requirements
- 4.7 I²C axis disable
- 5 I²C- inter-IC control interface
- 5.1 I²C interface
- 5.2 I²C interface details
- 5.3 I²C slave address
- 5.4 I²C read and write sequences
- 6 Features
- 6.1 Self-test mode
- 6.2 Power cycle/reset information
- 6.2.1 TDM interface power-on sequence
Features
±3.85 g full scale TDM slave interface Low noise Signal bandwidth 2400 Hz High, flat bandwidth 16-bit data output 20000 g high shock survivability Lead-free, ECOPACK, RoHS and “Green” compliant
Description
The LIS25BA is a low-noise high-bandwidth three-axis digital accelerometer with a dedicated TDM interface. The LIS25BA has a full scale of ±3.85 g and works with a Time-Division Multiplexing (TDM) interface. The LIS25BA is available in a small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. /*$ [[PP Table 1. Device summary
1 Pin description
Figure 1. Pin connections Table 2. Pin description
1 I2C_SCL (1) IN I²C serial clock - SCL
2 I2C_SDA (1) IN/OUT I²C serial data - SDA
3 TDM_BCLK IN TDM bit clock
4 TDM_WCLK IN TDM word clock
5 TDM_SDOUT OUT TDM serial data output
6 RES (GND) - Reserved pin (connect to GND)
7 TDM_MCLK IN TDM master clock
8 VDD Power supply
9 GND 0 V supply
10 RES (VDD) - Reserved pin (connect to VDD)
11 I2C_A0 IN I²C slave address selection
12 RES (GND) - Reserved pin (connect to GND)
13 RES (GND) - Reserved pin (connect to GND)
14 RES (GND) - Reserved pin (connect to GND)
- Only for test and trim. I²C timing values are not guaranteed.
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted(a). Table 3. Mechanical characteristics
- Typical specifications are not guaranteed.
- MEMS non-linearity based on simulation data.
- Values are based on preliminary corner simulation data.
- Max. value is guaranteed by characterization and not tested in production.
2.2 Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted(b). Table 4. Electrical characteristics (1) "Electrical noise" test mode. "Electrical noise" test mode.
10 MHz
2.3 Absolute maximum ratings
Table 5. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
3 TDM interface characteristics
Please refer to Section 4: TDM interface specifications for additional details. Table 6. TDM interface characteristics (1)
- All setup times and hold times in Table 6 and in Figure 4 are valid for BCLK polarity set to “clock on rising”. If BCLK polarity
Section 4: TDM interface specifications for additional details.
- All the DUT measurement points are normalized to the 294 Hz measurement. The deviation between each point and
Figure 4. TDM interface characteristics
3.1 I²C interface characteristics
Please refer to Section 5: I²C- inter-IC control interface for additional details. Table 7. Digital input/output voltage for I²C pins(1)
- Data based on standard I²C protocol requirement, intended only for test and trim. Values are not
- Typical specifications are not guaranteed.
- 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the dig-
ital pad in order to guarantee the correct digital output voltage levels VOH and VOL.
Figure 5. I²C slave timing diagram Note: Measurement points are done at 0.2·Vdd and 0.8·Vdd, for both ports. Table 8. I²C interface characteristics
- Typical specifications are not guaranteed.
Table 9. I²C high-speed mode specifications at 1 MHz
- Data based on characterization, not tested in production
4 TDM interface specifications
signal by separating the signal into many frames. There are many ways to accomplish this.
4.1 TDM interface overview
Figure 6. TDM block diagram frame synchronization (WCLK) a serial clock (BCLK), and the serial data out (SDOUT).
TDM interface specifications LIS25BA
4.2 Frame synchronization (WCLK)
The function of the WCLK is simply to identify the beginning of a frame. In particular the frame start at the rising edge of WCLK, and the WCLK widths supported are: 50% duty cycle One slot width (16 BCLK) One BCLK width In TDM mode, LIS25BA shall output accelerometer data on the SDOUT pin at the following sampling rates: WCLK = 8 kHz WCLK = 16 kHz WCLK = 24 kHz As depicted in Figure 6, the TDM input sampling rate (ODR_8kHz, ODR_16kHz and ODR_24kHz), and the associated data inputs (dataX_8kHz, dataX_16kHz, dataX_24kHz, dataY_8kHz, dataY_16kHz, dataY_24kHz, dataZ_8kHz, dataZ_16kHz and dataZ_24kHz ) can be selected in two different ways: 1. Using the I²C register wclk_fq (TDM_CTRL_REG (2Eh), bits 2 and 1). In this case the I²C register ODR_AUTO_EN (AXES_CTRL_REG (2Fh), bit 0) is equal to zero, that means that the ODR_auto functionality is disabled. 2. Using the output of the ODR_auto block (ODR_AUTO_EN (AXES_CTRL_REG (2Fh), bit 0) equal to one). This latter simply receives as inputs both the MCLK and the WCLK and it computes the current sampling frequency as a ratio between the MCLK and WCLK. The possible outputs of the ODR_auto block are: a) 00: sampling rate equal to 8 kHz (MCLK/WCLK = 1536) b) 01: sampling rate equal to 16 kHz (MCLK/WCLK = 768) c) 10: sampling rate equal to 24 kHz (MCLK/WCLK = 512) Observing Figure 6, it is possible to see, that if a ratio between MCLK and WCLK differ from 1536, 768 and 512, the sampling rate equal to 8 kHz is selected.
4.3 Serial clock (BCLK)
The sole purpose of the serial clock BCLK is to shift the data out of the serial SDOUT port. To this purpose, the TDM interface uses an internal counter that is set to one when the rising edge of the WCLK is detected, and it is reset to zero when the maximum number of BCLK in a WCLK period is reached. The maximum number of BCLK contained in a WCLK period (cmax input of the TDM in Figure 6) can be expressed as a function of both the BCLK and WCLK frequencies, and can be computed using the following equation: Equation 1
employing the I²C register ODR_AUTO_EN (AXES_CTRL_REG (2Fh) bit 0). The TDM cmax can be programmed through the I²C registers TDM_cmax (24h-25h).
4.4 TDM axes mapping
segment a slot thereafter in this document. The data slot width is fixed and equal to 16 bits. In each slot, data should be left-justified (MSB first). Figure 7. Axes X, Y, Z mapped to SLOT0, SLOT1, SLOT2 Figure 8. Axes X, Y, Z mapped to SLOT4, SLOT5, SLOT6
4.5 TDM configurations
I²C interface will be detailed.
4.5.1 Configuration 1
Figure 9. WCLK, SDOUT change on the falling edge of BCLK and are valid on the Note: Setup and hold times are defined in Table 6: TDM interface characteristics.
4.5.2 Configuration 2
Figure 10. WCLK, SDOUT change on the rising edge of BCLK and are valid on the Note: Setup and hold times are defined in Table 6: TDM interface characteristics.
4.5.3 Configuration 3
Figure 11. WCLK, SDOUT change on the falling edge of BCLK and are valid on the Note: Setup and hold times are defined in Table 6: TDM interface characteristics.
4.5.4 Configuration 4
Figure 12. WCLK, SDOUT change on the rising edge of BCLK and are valid on the Note: Setup and hold times are defined in Table 6: TDM interface characteristics.
TDM interface specifications LIS25BA
4.6 TDM clocks and MCLK requirements
The relationship between TDM clocks and MCLK should be: Both BCLK and WCLK must be obtained from MCLK by integer division. This requirement is mandatory since ADC is clocked by MCLK, so the TDM data rate must be perfectly synchronous in frequency and phase with the decimated ADC data rate. The BCLK/WCLK ratio must be an integer value.
4.7 I²C axis disable
In TDM mode, a host processor can power down each axis of the LIS25BA accelerometer independently, overriding the I²C registers (AXISX_EN, AXISY_EN, AXISZ_EN in AXES_CTRL_REG (2Fh)) interface to reduce power consumption during operation. When an axis is powered down, the corresponding TDM slot will be put in HiZ.
5 I²C- inter-IC control interface
5.1 I²C interface
content can also be read back. The relevant I²C terminology is given in the table below. resistor. When the bus is free, both lines are high.
5.2 I²C interface details
is receiving data from the slave or transmitting data to the slave (SAD subsequences). more than one device of the same type to be connected to the I²C bus. Table 10. I²C serial interface pin description Table 11. I²C terminology
transmit to the slave with direction unchanged.
5.3 I²C slave address
of writing or reading respectively.
5.4 I²C read and write sequences
terminated by the generation of a STOP condition. Table 12. Transfer when master is writing one byte to slave Table 13. Transfer when master is writing multiple bytes to slave Table 14. Transfer when master is receiving (reading) one byte of data from slave Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
6 Features
6.1 Self-test mode
comparable with the full-scale range in order to have an effective self-test mode. For the self-test values of each axis please refer to Table 3: Mechanical characteristics.
6.2 Power cycle/reset information
6.2.1 TDM interface power-on sequence
In TDM, the LIS25BA starts in disabled mode with the following sequence. Figure 13. Power-on sequence (TDM interface) In Figure 13 T0 represents the time when Vdd reaches 90% of the final value. After TDIS = 5.5 ms the LIS25BA reaches the disabled mode condition. also in this case the first 3 samples after the TDM configuration change will be invalid.
6.2.2 Disabled mode
command will be executed immediately (no wait state). MCLK/BCLK/WCLK clocks must be set to the correct values before writing to the I²C. Please refer to Figure 14 for the disabled mode sequence. Figure 14. Disabled mode sequence
7 Register mapping
Table 16. Register address map
- Read only (r) - read/write (rw)
8 Register description
8.1 TEST_REG (0Bh)
Table 17. TEST_REG register
8.2 WHO_AM_I (0Fh)
Device identification register.
8.3 TDM_cmax (24h-25h)
TDM counter max value when the BCLK autoconfiguration feature is disabled.
8.4 CTRL_REG (26h)
Table 21. CTRL_REG register
- For proper operation of the device, this bit must be set to ‘0’.
Table 18. TEST_REG register description Table 19. WHO_AM_I register Table 20. TDM_cmax register
- For proper operation of the device, this bit must be set to ‘0’.
Table 22. CTRL_REG register description
8.5 TDM_CTRL_REG (2Eh)
Table 23. TDM_CTRL_REG register
8.6 AXES_CTRL_REG (2Fh)
Table 25. AXES_CTRL_REG register
- For proper operation of the device, this bit must be set to ‘0’.
Table 24. TDM_CTRL_REG register description
- For proper operation of the device, this bit must be set to ‘0’.
Table 26. AXES_CTRL_REG register description
- In this case it is mandatory to set TDM_CTRL_REG (2Eh) bits 2 and 1 to match the WCLK sampling rate
- LIS25BA automatically measures the ratio r = MCLK/WCLK. The WCLK frequency is internally
proper TDM configuration as described in TDM_cmax (24h-25h).
9 Package information
specifications, grade definitions and product status are available at: www.st.com.
9.1 LGA-14 package information
The LGA-14 package is classified MSL 3. Figure 15. LGA-14 2.5x2.5x0.86 mm package outline and mechanical data
9.2 LGA-14 packing information
Figure 16. Carrier tape information for LGA-14 package Figure 17. LGA-14 package orientation in carrier tape
Figure 18. Reel information for carrier tape of LGA-14 package Table 27. Reel dimensions for carrier tape of LGA-14 package
Table 28. Document revision history