LIS202DL STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram & pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Mechanical and electrical specifications
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Absolute maximum ratings
- 2.4 Terminology
- 2.4.1 Sensitivity
- 2.4.2 Zero-g level
- 2.4.3 Self test
- 2.4.4 Click and double click recognition
- 3 Functionality
- 3.1 Sensing element
- 3.2 IC interface
- 3.3 Factory calibration
- 4 Application hints
- 4.1 Soldering information
- 5 Digital interfaces
- 5.1 I2C serial interface
- 5.1.1 I2C operation
- 5.2 SPI bus interface
- 5.2.1 SPI read
- 5.2.2 SPI write
- 5.2.3 SPI read in 3-wires mode
- 6 Register mapping
- 7 Register description
2-axis - ±2g/±8g smart digital output “piccolo” accelerometer Feature ■ 2.16V to 3.6V supply voltage ■ 1.8V compatible IOs ■ <1mW power consumption ■ ±2g/±8g dynamically selectable Full-Scale ■ I2C/SPI digital output interface ■ Programmable interrupt generator ■ Click and double click recognition ■ Embedded high pass filter ■ Embedded self test ■ 10000g high shock survivability ■ ECOPACK® RoHS and “Green” compliant (see Section 9)
Description
The LIS202DL is an ultra compact low-power two axes linear accelerometer. It includes a sensing element and an IC interface able to provide the measured acceleration to the external world through I 2C/SPI serial interface. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon. The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The LIS202DL has dynamically user selectable full scales of ±2g/±8g and it is capable of measuring accelerations with an output data rate of 100Hz or 400Hz. A self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate inertial wake-up interrupt signals when a programmable acceleration threshold is crossed at least in one of the two axes. Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS202DL is available in plastic Thin Land Grid Array package (TLGA) and it is guaranteed to operate over an extended temperature range from -40°C to +85°C. The LIS202DL belongs to a family of products suitable for a variety of applications: – Motion activated functions – Gaming and Virtual Reality input devices – Vibration Monitoring and Compensation LGA-14 (3x5x0.9mm) Table 1. Device summary
8.2 Mechanical Characteristics derived from measurement in the -40°C to
1 Block diagram & pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connection Table 2. Pin description
1 Vdd_IO Power supply for I/O pins
2 GND 0V supply
3 Reserved Connect to Vdd
4 GND 0V supply
5 GND 0V supply
6 Vdd Power supply
8 INT 1 Inertial interrupt 1
9 INT 2 Inertial interrupt 2
10 GND 0V supply
11 Reserved Connect to Gnd
12 SDO SPI Serial Data Output
14 SCL
Table 2. Pin description (continued)
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics (1)
- Typical specificat ions are not guaranteed
- Verified by wafer level test and measur ement of initial offset and sensitivity
- Typical zero-g level offset value after MSL3 preconditioning
- Offset can be eliminated by enabl ing the built-in high pass filter
- If STM bit is used values change in sign for all axes
- Output data reach 99% of final value after 3/OD R when enabling Self-Test mode due to device filtering
- ODR is output data rate. Refer to table 3 for specifications
2.2 Electrical characteristics
Table 4. Electrical Characteristics (1)
- Typical specification are not guaranteed
- It is possible to remove Vdd maintaining Vdd_IO withou t blocking the communication busses, in this condition the
measurement chain is powered off.
- Time to obtain valid data after exiting Power-Down mode
2.3 Absolute maximum ratings
Table 5. Absolute maximum ratings
LIS202DL Mechanical and electrical specifications
2.4 Terminology
2.4.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensors.
2.4.2 Zero-g level
Zero-g level Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0g in X axis and 0g in Y axis. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level tolerance (TyOff) describes the Standard Deviation of the range of Zero-g levels of a population of sensors.
2.4.3 Self test
Self Test allows to check the sensor functionality without moving it. The Self Test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to ‘0‘. When the self- test bit of ctrl_reg1 is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When Self Test is activated, the device output level is given by the algebric sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
2.4.4 Click and double click recognition
The click and double click recognition functions help to create man-machine interface with little software overload. The device can be configured to output an interrupt signal on dedicated pin when tapped in any direction. If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial interrupt pins (INT1 and/or INT2). A more advanced feature allows to generate an interrupt request when a “double click” stimulus is applied. A programmable time between the two events allows a flexible adoption to the application requirements. Mouse-button like application like clicks and double clicks can be implemented. This function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli.
3 Functionality
The LIS202DL is an ultracompact, low-power, digital output 2-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I 2C/SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in pF range.
3.2 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by analog-to-digital converters. The acceleration data may be accessed through an I 2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS202DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The LIS202DL may also be configured to generate an inertial Wake-Up interrupt signal accordingly to a programmed acceleration event along the enabled axes.
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. This allows to use the device without further calibration.
4 Application hints
Figure 3. LIS202DL electrical connection placed as near as possible to the pin 6 of the device (common design practice). measurement chain is powered off. completely programmed by the user though the I2C/SPI interface.
4.1 Soldering information
5 Digital interfaces
line must be tied high (i.e connected to Vdd_IO).
5.1 I 2C serial interface
whose content can also be read back. The relevant I2C terminology is given in the table below. embedded inside the LIS202DL. When the bus is free both the lines are high. Table 6. Serial interface pin description Table 7. Serial interface pin description
LIS202DL Digital interfaces
5.1.1 I 2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. The Slave ADdress (SAD) associated to the LIS202DL is 001110xb. SDO pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’ (address 0011100b). This solution permits to connect and address two different accelerometer to the same I 2C lines. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The I 2C embedded inside the LIS202DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically increment to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the Master will transmit to the slave with direction unchanged.
Digital interfaces LIS202DL Transfer when Master is writing one byte to slave: Transfer when Master is writing multiple bytes to slave: Transfer when Master is receiving (reading) one byte of data from slave: Transfer when Master is receiving (reading) multiple bytes of data from slave: Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge.
5.2 SPI bus interface
The LIS202DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Master ST SAD + W SUB DATA SP Slave SAK SAK SAK Master ST SAD + W SUB DATA DATA SP Slave SAK SAK SAK SAK Master ST SAD+W SUB SR SAD+R NMAK SP Slave SAK SAK SAK DATA Master ST SAD + W SUB SR SAD + R MAK Slave SAK SAK SAK DATA Master MAK NMAK SP Slave DATA DATA
Figure 4. Read & write protocol falling edge of SPC and should be captured at the rising edge of SPC. from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 5. SPI read protocol performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Figure 6. Multiple bytes SPI read protocol (2 bytes example)
5.2.2 SPI write
Figure 7. SPI write protocol
performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 8. Multiple bytes SPI write protocol (2 bytes example)
5.2.3 SPI read in 3-wires mode
Figure 9. SPI read protocoin 3-wires model bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Multiple read command is also available in 3-wires mode.
6 Register mapping
Table 8. Register address map
cause permanent damages to the device.
7 Register description
write the data through serial interface.
7.1 WHO_AM_I (0Fh)
Device identification register. This register contains the device identifier that for LIS202DL is set to 3Bh.
7.2 CTRL_REG1 (20h)
to “1” the selected data-rate will be set equal to 400Hz. Table 9. Register Table 10. Register
- Bit to be set to “0” for correct device functionality
Table 11. Register description
thus allowing to check the functionality of the whole measurement chain. set to 1. The default value is 1. set to 1. The default value is 1.
7.3 CTRL_REG2 (21h)
interface mode output data are sent to SDA_SDI pad. internal registers related to trimming functions to permit a good behavior of the device itself. process the BOOT bit is set again to ‘0’. HP_coeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft. Table 12. Register Table 13. Register description
7.4 CTRL_REG3 [Interrupt CTRL register] (22h)
Table 14. Truth table Table 15. Register Table 16. Register description IHL Interrupt active high, low. Default value 0. PP_OD Push-pull/Open Drain selection on interrupt pad. Default value 0. Data Signal on Int2 pad control bits. Default value 000. Data Signal on Int1 pad control bits. Default value 000. Table 17. Truth table
001 W U _ 1
010 W U _ 2
7.5 HP_FILTER_RESET (23h)
high pass-filter. If the high pass filter is enabled all two axes are instantaneously set to 0g. This allows to overcome the settling time of the high pass filter.
7.6 STATUS_REG (27h)
7.7 OUT_X (29h)
7.8 OUT_Y (2Bh)
Table 18. Register Table 19. Register description Table 20. Register Table 21. Register
7.9 WU_CFG_1 (30h)
7.10 WU_SRC_1 (31h)
Table 22. Register Table 23. Register description res_1 Reserved at Value: 0. Value should not be changed. res_2 Reserved at Value: 0. Value should not be changed. Table 24. Register Table 25. Register description
Wake-up source register. Read only register. refreshment of data in the SRC_1 register if the latched option was chosen.
7.11 WU_THS_1 (32h)
7.12 WU_DURATION_1 (33h)
Table 26. Register Table 27. Register description Table 28. Register Table 29. Register description
7.13 WU_CFG_2 (34h)
7.14 WU_SRC_2 (35h)
Table 30. Register Table 31. Register description res_1 Reserved at Value: 0. Value should not be changed. res_2 Reserved at Value: 0. Value should not be changed. Table 32. Register Table 33. Register description
Wake-up source register. Read only register. refreshment of data in the WU_SRC_2 register if the latched option was chosen.
7.15 WU_THS_2 (36h)
7.16 WU_DURATION_2 (37h)
blocked when LIR=1 in configuration register and the interrupt event is verified. Table 34. Register Table 35. Register description Table 36. Register Table 37. Register description
7.17 CLICK_CFG (38h)
Table 39. Register description res_1 Reserved at Value: 0. Value should not be changed. res_2 Reserved at Value: 0. Value should not be changed. Table 40. Truth table
7.18 CLICK_SRC (39h)
7.19 CLICK_THSY_X (3Bh)
7.20 CLICK_TimeLimit (3Dh)
From 0 to 127.5msec with step of 0.5 msec. Table 41. Register Table 42. Register description Table 43. Register Table 44. Register description Table 45. Register
7.21 CLICK_Latency (3Eh)
From 0 to 255 msec with step of 1 msec.
7.22 CLICK_Window (3Fh)
From 0 to 255 msec with step of 1 msec. Table 46. Register Table 47. Register
8 Typical performance characteristics
8.1 Mechanical characteristics at 25°C
Figure 10. X axis 0-g level at 2.5V Figure 11. X axis sensitivity at 2.5V Figure 12. Y axis 0-g level at 2.5V Figure 13. Y axis sensitivity at 2.5V
8.2 Mechanical Characteristics de rived from measurement in the
Figure 14. X axis 0-g level change vs. Figure 15. X axis sensitivity change vs. Figure 16. Y axis 0-g level change vs. Figure 17. Y axis sensitivity change vs.
8.3 Electro-mechanical ch aracteristics at 25°C
Figure 18. Current consumption in normal Figure 19. Current consumption in power
9 Package information
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 20. LGA 14: mechanical data & package dimensions
Table 48. Document revision history 11-Jun-2007 1 Initial release.