LH4860

LH4860 NSC | Alldatasheet

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Technical content

Super Fast 12-Bit Track-Hold Amplifier General Description Features The LH4860 is an extremely fast high resolution Sample- ™ 200 ns max acquisition time 10V step to +0.01% FS. Hold (track-and-hold) amplifier. It guarantees acquisition m™@ 100 ns max sample-to-hold settling time time and sample-to-hold settling time to +0.01%. The m +50 Ps aperture jitter LH4860 will acquire a full 10V signal to +0.01% full scale 74 dB feedthrough attenuation (or £1 mY) in less than 200 ns. The bandwidth of the track- iw TTL compatible ing amplifier is 16 MHz. In the track mode, offset error is i typically +0.5 mV and gain error is typically +0.05%, The ™ Direct replacement for HTC-0300, 4860, and HS9720 LH4860 is precisely laser trimmed for pedestal compensa- tion. The “Hold” capacitor is internal for ease of use. Also, Applications the bypassing power supply capacitors are inside the pack- ™ Transient recorders age. Fast fourier analysis mt High speed DAS's ™ High speed DDS's @ Analog delay and storage Block and Connection Diagrams ANALOG: jka wput 150 1 ANALOG O” OUTPUT

21 GROUND

GROUND 15O—> 0.001 = = e000: 9 95¥ HOLD 1146 " ‘COMMAND, BD 0 Fal 24 415V PS BYPASS 22 =15V CAPACITORS 0.001 ws 4 hors caow could 120 GROUND 100—p> TUK/9770-2 VS Analog Output 71 (24 5-+15V Supply N/Cmd2 23}=Ground N/C—s 22 F=15V Supply N/om4 21)—Ground N/c—s 20 N/C N/c—7 18 N/C nota 7eNye 45V Supply 9 16-N/c Digital Ground—4 10 15}Ground Hold Command —4 11 14f-N/c old Command 412 13 Analog Input TUK/O770-1 Top View Duatin-Line Metal Package (D) Order Number LH4860D or LH4860CD ‘See NS Package Number D241 5:37

3 Absolute Maximum Ratings

J | It muttary/Aerospace specified devices are required, Output Short Circuit Duration Continuous please contact the National Semiconductor Sales Operating Temperature Range Office/Distributors for avaliability and specifications. LH4860C —25°C to + 85°C Supply Voltage (Vg+ and Vs~) £18V LH4860 —55°C to + 125°C Logic Supply Voltage (Vp) +7V Storage Temperature Range —65°C to + 150°C Analog Input Voltage +V5 Power Dissipation (Pp) Digital Input Voltage -0.5V to +5.5V (See Graph) 2.4W Output Current (Note 1) +65mA ESD (Note 6) TBD Unie Uniess Tested Design (Max Symbol Conditions Typ Limit Limit Otherwise (Notes) | (Note 9) Stated) Input/Output , a | Outpwtcurent | woe) | | wo Tm | Ouputimpedence [fot fT Maximum Capacitive F Load pl a La v (Min) a ee [/digtatinputtoading | | tT tt Oe 77 | Geinaccwacy | | tos, | toe | Tt Gain Linearity | Otteetvotage | Sampiomode | sos | ss | | mw | Holastep | Pedostalrigwor | 25 | so | | mv (Note 7) ppm of Offset Drift Sample Mode ppm of 5-38

c . = LH4860C/LH4860 Units 3 (Max Uniess Symbol Conditions. "rete _— Otherwise (Notes) | (Notes) Stated) ‘Acquisition 10V Stop to £0.01% 150 ns Time (Notes 4, 5) FS (+1 mV) 10V Step to £0.1% 10V Step to +1% ns FS (+100 mV) 1V Step to +1% Pea fs | Setting Time Sample | _tozo.o1%Fs(imy | 60 | to | «| ns to Hold (Note 4) toxormrsciomy | 4 | | | ns ‘Sample to Hold Transient mVp-p | ApertureDelayTime [| es TTC ns | Apertureiter | CT co TT ps OutputSiewRate | | coo PTs ‘Small Signal Droop Rate Po tos Pes avis a 77 [vic Tene vis Feedthrough 2.5 MHz, 20 Vp_p thput 74 dB PSRR Power Supply Rejection Ratio £05 mv/V Quiescent Current +15V Supply a Drai |_=1svSupply | 2a [25 Tm +5V Supply a |_PowerGonsumption [| 7aos| os] |S Note 1: The LH4860 output is current limited at approximately + 65 mA and the unit can withstand a sustained short-to-ground. For normal operation, load current should not exceed +40 mA. Note 2: See Application Information for use of Hold and Hold inputs. Note 3: The Hold Command inputs appear as one TTL load and are defined as sinking 40 »A with logic “1” applied and sourcing 1.6 mA with logic “0” applied. Note 4; FS means “Full Scale” and is equivalent to 10V. FSR means “Full Scale Range” and is equivalent to 20V. For a 12-bit system, 1 LSB = 0.024% FS. Note 5: Acquisition time is tested with no load. Note 6: The test circuit used consists of the human body model of 100 pF in series with 1500N. . Note 7: Bokdface limits are guaranteed over full temperature range. Operating ambient temperature range of LH4860C is — 25°C to + 85°C, and LH4860 is — 55°C to + 125°C. Note 8: Tested limits are guaranteed and 100% production tested. Note 9: Design limits ase guaranteed (but not production tested) over the indicated temperature or temperature range. These limits are not used to calculate 5-39

3 ‘TRACK MODE, HOLD MODE overs ON Se TaNSE a 2 sooixrs FEDTINOUGH y “At: My ‘SLEW RATE / ACQUISITION HOLD MODE ™E ™e TUK/9770-5 FIGURE 1. Timing Diagram

0 LTT TTT AL

FIGURE 2. Accuracy Error Due to a +50 ps Aperture uitter at 10V Full Scale

Application information

LAYOUT logic supply needs to be well bypassed. Although both +5V The LH4860 is constructed in a way that with proper care in and + 15V are internally decoupled with 0.001 pF, in critical the layout it will meet its specifications without additional applications, additional bypass capacitors are recommend- extemal components. ed (0.1 pF-1 pF tantalum). A large analog ground plane will provide uniform ground LOGIC COMMANDS potential to the four ground pins {Pin 10, 15, 21 and 23). ATTL logic “0” on Pin 14 (or a logic “1” on Pin 12) will put These pins should be connected to the ground plane with the LH4860 into the sample (track) mode. In this mode, the minimum lead length. Any difference in ground potential, device acts as an inverting unity gain amplifier, and its out- due to ground current, will degrade the performance of the put will track the input. device. a. A logic “1” on Pin 11 and logic “O" on Pin 12 will put the The analog and digital grounds of the LH4860 should be device into the hold mode, where the output will be held connected together close to the device. The +5V digital constant at the level present when the command was given. 8-40

Application Information (continues) 3 Unused logic pins need to be tied to a fixed logic level. maximum allowable rate of change, the frequency that can When Pin 11 is used, then Pin 12 must be tied to ground; be converted accurately becomes: when Pin 12 is used as logic input, Pin 11 is to be tied to 122V/s +5V through 1k. = Say 7 38He caer in 11 or 12 represents one TTL load to the drive If a track-hold amplifier is used in front of the A/D, then orreul much faster signals can be accurately digitized. In this case, Pin 12 the input waveform has to be repetitive, and the hold pulse Hold) is shifted in phase every time a new conversion is made, (Hold) until the whole signal has been captured. The limitation for Track accuracy is determined by the aperture jitter, which is the Track uncertainty of the moment when the signal is frozen. In Hold this case, the maximum slew rate is 1.22 mV/100 ps = 12.2 Track V/us and the highest frequency at which accurate conver- sion occurs becomes: In the tracking mode, the Track-Hold Amplifier operates as _ 12.2V/ps _ an inverting amplifier with unity gain. It is limited by its small 1= Srey 938 kHz signal eee 43 ee 16 MHz, and the power band- The fact that the LH4860 can digitize the fastest part of a » typically 4. 7 338 kHz sine wave does not mean it can digitize that signal LOADING for reconstruction purposes. Realistically a sample can only ‘Some restrictions on the output load apply to avoid oscilla- be taken in the time it takes to acquire (200 ns for the tions and performance variations over temperature. LH4860) plus the conversion time of the ADC. ... Recommended load resistance is 5009 or above and A capacitance up to 50 pF; load resistance down to 2502 can Other Considerations for Using the be used without. degrading the performance, Capacitive LH4860 with A/D Converters loads up to 150 pF will be free of oscillations, but acquisition There are several considerations for good match between and parry times will be extended due to slew rate Imita- track hold amplifier and A/D. One is that the output resist- ions in the output. ance of the T/H should be low compared to the input resist- APERTURE JITTER ance of the A/D, up to frequencies 5 times the clockrate of i licati i . This is because of the digital nature of a succes- In a typical DSP Application, an analog signal needs to be the A/D. Th te i i digitized. This can be done with an A/D Converter; which sive approximation A/D its internal D/A changes its output has the limitation that the signal needs to be fairly constant momentarily and current transients occur at the A/D input. throughout the conversion time, therefore, only low frequen- These should be sunk and settled before the next bit con- cy signals can be converted without loss of accuracy. To version. In the hold mode, the LH4860 has a typical output handle faster signals, a Track-Hold Amplifier can be used in resistance of 0.19; its output, typically, recovers to +0.01% front of the A/D. from 2 mA step in less than 100 ns. In order not to lose accuracy, the standard rule of thumb is Another consideration is the LH4860's track-to-hold tran- that the input signal should not change more than + % LSB sient settling time. Normally, the same timing pulse that init- during the conversion time. This determines the maximum ates “hold” also starts the A/D conwersion. The decision for frequency for accurate conversion. the A/D’s MSB, normally, takes place one clock cycle after For example, take a 12-bit 10 ys A/D Converter. If it is he start signal ane owe time, the track-hold command : * oo . pin can be driven directly (or inverted) from the successive operated on a OV to 10V input range, 1 LSB is equivalent to: approximation A/D's conversion status output. During con- 10V _ 10V =o 4amv version the T/H is in hold. 212 4096 Many sampling A/D converter applications require that a and Y LSB is 1.22 mV. The maximum allowable rate of signal be sampled fast but held for a long time so that a change becomes: slow (inexpensive) A/D converter may be used. Such con- dv % LSB 1.22 mV flicting requirements place stringent demands on a S/H am- “at” ConversionTime ~ 10s 7 122W/S plifier, Fortunately, cascading two S/H ampiifiers, as in Fig- at Conver " ure 3, solves the problem. The LH4860 acquires the signal For a sinewave of v(t) = A sine 27r ft, the derivative is a rate to within 0.01% F.S. in under 200 ns and holds it until the 5 of change vs. time. LH0023 acquires the sampled signal. The tow droop rate of dv) _ 1LH0023 allows it to hold the sampled signal to within 0.01% at” 27f ACos (20 ft) for as long as the conversion time of ADC1210 (100 ys). i i = a Note that the start pulse for the A/D converter should occur Tokens tocones Dotan 0, and the maximum rate at the end of LH0023’s hold mode settling time. Figure 3's the sinewave le chooen for 10 Vp.p, or A — SY, the maxt circuit accepts a OV to —5V full scale input signal and pro- —p, oF A = BV, F d tary bit ical timing dia~ mum rate of change becomes 10-. If this is equated to the luces a complementary binary output. A typical timing dia 5-41

FIGURE 5. Fast Data Acquisition Using Ping-Pong Switching cycle time thus reducing system throughput. For example, S/H’s acquisition time from the system's overall cycle time. much as 300 ns to the converter’s conversion time thus less than the 100 ns hold mode settling time of the LH4860. signal. As soon as the ADC's conversion is complete, S/H2 combination.