LH4104 NSC | Alldatasheet
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P=4 : = GA National PRELIMINARY = rf a Semiconductor 3 . . = | LH4104/LH4104C Fast Settling High Current 4 | Operational Amplifier General Description Features The LH4104 is a fast settling high current Bi-Fet op amp '™ 500 ns settling time to 0.01% for a 10V step designed for applications that require a fast settling time of | m@ 100 mA continuous output current 500 ns to 0.01% and 100 mA continuous output current. 18 MHz gain bandwidth product The high output current eliminates the need for a buffer to Internal supply bypassing provide the additional current drive not available in most @ Unity gain stable operational amplifiers. The operational amplifier also fea- tures a gain bandwidth product of 18 MHz anda slewratec! Applications 40V/ns. m Cable Driv er Designed for use with minimum external circuitry, the sah Spee 3 Ram Generat LH4104 provides internal compensation for unity gain stabil- igh Sp Pp rators ity as well as internal supply bypass capacitors. These fea. DAC Output Amplifiers tures minimize the circuit's sensitivity to external layout con- ™ Fast Buffers ditions. m= Sample and Holds & Fast Integrators ES Schematic Diagram OFFSET OFFSET AD) AD) oN ve veo ED) | +nput i 8 osae ; 3 2) | 91s) 10(4) : oD v= ve- wu Pinout shown for metal can package (for molded package in parenthesis) Wesdo-t *On metal can package (G) pins #2 and #8 are internally connected. The case is electrically isolated. The molded package (N) does not have ground j ‘connections or bypass capacitors. | Connection Diagrams Metal Can Package 16-Lead Molded Dual-in-Line Package (N) GND ar sONST vs ner? 6 Ene ney? Bh we. l®, @ Og Ver ven oo ie = nour ovreut ves 13 orrser apwst Ps ovrurs. a vos si ewour £MeT XO © OF ve- OFFSET ADWSTJ7 10F-nc - ne afenc ose’ JY Putte TLk/e840-2 TUK/9840-14 Top View Top View Order Number LH4104CG or LH4104G Order Number LH4104CN See NS Package Number H12B See NS Package Number N16A 3-254
. = Absolute Maximum Ratings = If Military/Aerospace specified devices are required, Differential input Voltage, Vin +30V but < +2V, 2 please contact the National Semiconductor Sales Input Voltage Range, Vom +18V but < +V. r Office/Distributors for availability and specifications. Oper Temperature Range, Ta = Supply Voltage, Vs £18V LH4104 —S5°Cto+125°C | = Steady State Output Current, lo 100 mA LH4104C —25Cto+asc |S Power Dissipation (See Curves) Storage Temperature Range, Tst¢ -e5Cto +1500 | Ta = 25°C, rHaiodG. LH41046G Y sew Maximum Junction Temperature, Tj 150°C To = 25°C, LH4104G, LH41046G 25W Lead Temperature (Soldering < 10 sec.) 300°C ESD rating is to be determined. | twatoac unite Design | (Max Unless Symbol Conditions ym Typ Limit | Otherwise (Note 3) Stated) Vos | input Offset Voltage [As=son Te Ts To Tow ° — na mm a ee ee Po 20 Avo, | LargesignatvorageGan | R= soon toe | oor fT jin) Vo Output Voltage Swing RL = 1000 (Note 5) [| | +o | | veatin lin) CMRR | CommonMede Rejection Rato | Vw= -tiviotiv | 100 | eo [70 | a8 ain | PSRR__ | Power Supply Rejection Ratio | Voc = +10Vto +15V [100 | 80 | 70 | aacmin a LH4104C Units Tested | Design | (Max Unless mbol sy Typ | Limit Limit Otherwise (Note 2) | (Note 3) | Stated) ts Setting Time 100.01% | Ay = —1,Viy = —SVto+5V,R,= 1000 | 500| so | | ns Sa Vin = —10V to + 10V, R= 1008 [ao ff 32 | vipstminy GEW__| GainBandwiatnProduct [| te | Te t SmallSignalRisoTime | Ay=1A=s00n | wo TT | ns 3-255
(2) zs ©| DC Electrical Characteristics voc = +15v, Ta = 25°C unless otherwise noted (Notes 1 and 6) a = [tHtoe nits S| symbol Conditions Tested | Design | (Max Uniess S Typ Limit Limit Otherwise = (Note 2) | (Note 3) Stated) | _Vos | input ottset Voltage [as=soo | 2 | to Tw Vos/AT | Offset Voltage Dritt [rs=son | co | |r a Input Bias Current T= 25°C, (Note 4)Vow=ov | 200 | 600 | _—i| pA Po so Tm los Input Offset Current 1) = 25°C, Vow = OV [2 | 40 | | pA Po so ‘Avo. | Large Signal Voltage Gain R, = 1009 [106 | eo | | Vo Output Voltage Swing Ry = 1000 (Note 5) [| +0 | | Vv (Min) AL=1k0 fe] so [| CMRR | Common Mode Rejection Ratio | Vin —11V to +41V | 10 | eo | ‘| ge wim ee " PSRR | Power Supply Rejection Ratio | Voc = #10Vto +15V [ 10 | eo | | se (Min Po " Is Supply Curent [wo Ts Tm ' AC Electrical Characteristics voc = +15V, Ta = 25°C unless otherwise noted [tratoe | Units i ‘Symbol Parameter Tested | Design (ax unless | Typ | Limit Limit e' (Note 2) | (Note 3) | Stated) ' ts Setting Time t00.01% | Ay=—1,Viw=—SVto+5V,R,= 1000 | 500| eo | | ns Sr Viv = —10V to +10v, Ry = 1008 Pao [a2 | viastein BW | GainBandwatnroauct| te |e | t Small Signal Rise Time _| Ay = 1,Ri = 1000 [wf[ | 2 | os i Note 1: Boldiace limits are guaranteed over full temperature range. Operating ambient temperature range of LH4104C is — 25°C to +85°C, and LH4104 is, | “BSC to +125. Note 2: Tested limits are guaranteed and 100% production tested. Note 4: Specifications is at 25°C junction temperature due to requirements of high speed automatic testing. Actual values at operating temperature will exceed ' value at Tj = 25°C. Note 5: The output swing is limited by the maximum output current of + 100 mA when R, = 1002. Note 6: When the LH4104 is operated at elevated temperture (such as 125°C), some form of heat sinking or forced air cooling is required. The quiescent power with Voc of + 15V is 750 mW, whereas the package can only handle 500 mW without a heatsink at 125°C. 3-256
Typical Performance Characteristics =
120 Open Loop Frequency Response sh H4104G, CG Power Dissipation ec
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3 oh . 1s = Bre Tt Aan SN [NIN EB , [oaq ore LTT Sy” ———o 20 o TL Tt tT tT Tt) 10 100 1K 10K 100K 1M 10M 100M t) B 5S 77 10 125 150 FREQUENCY (Hz) TEMPERATURE (°C) TUK/6840-4 TUk/e840-5 astHa104CN Power Dissipation Settling Signal =” HHH +4 Dagenaceo Boum =5nee | g 8X EJ d Nace a a a 10 7 PENG Se MeSSene 2 05
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LTE L$ tT frcntso TEMPERATURE (°C) TUk/e840-3 TUK /e840~15 Applications Information POWER SUPPLY BYPASSING currents vary with temperature and input voltage range. Ig i The LH4104 will perform well in most circuit boards even will normally double with each 11°C rise in junction tempera- H without external supply bypassing; however it is recom- ture. \\ mended that some bulk bypassing be provided to maintain LAYOUT PRECAUTIONS optimum settling time. A 0.1 pF disc ceramic capacitor an ; ; 1 uF tantalum capacitor on each supply is recommended. een to ceting tine atthe LHatOal Th oimeertrt to oe ed the bypass capacitors close to the amplifiers supply single point ground retums for inputs, loads, and feedback " components and to keep the returns short. Compensation COMPENSATION components should be located close to the appropriate pins To minimize the effects of input capacitance at the to minimize stray reactances. Keep the system's digital sig- LH4104’s inverting input and any additional layout capaci- nals (or any other signals with fast rise times) separated tance, an extemal compensation capacitor must be used. from the amplifier. f such signals are too close to the ampli- The compensation capacitor (C1) used in Figure 2 (Test fier, they can couple capacitively to the amplifier’s inputs, : Circuit Section) is typically 66 pF. The optimum value for the resulting in undesirable signals at the output. compensation capacitor depends on the application circuit PRESERVING AND VERIFYING THE LH4104’S FAST and the board layout. SETTLING TIME. INPUT BIAS CURRENT To realize optimum settling performance in circuits using the The input devices are JFETs, and will normally have input LH4104, both the design and layout must be meticulous. bias (Ig) currents in the tens of picoamps. However, these Application note AN-428, “Preserving and Verifying the 3-257
1S] | Applications Information (continued) Z| LF 400’s Fast Settling Time", explains the required design mended that the negative supply be turned on first, if the ii] and measurement techniques. Although this application supplies can be turned on independently. = note was written for the LF400, it suggests good guidelines Also, even if the input stage is well protected with clamp | and is directly applicable to the LH4104. Only the sections diodes and current limiting, the inputs should not be allowed =| covering supply bypassing and output load limitations to be heavily unbalanced (for example, one input at ground | J | should be ignored. This is because the LH4104 has internal and the other at the rail) for extended periods of time (for bypassing capacitors and substantially greater output drive example, many hours). The long-term effects of an unbal- current than the LF400. The suggested circuits require only anced differential pair are increased offset voltage and off- small and straightforward modifications; even the printed set current. circuit board layout can be easily modified to accept the footprint of the LH4104 without impacting setting time. v PROTECTION SCHEMES FOR THE LH4104 The LH4104 has similar input characteristics of National Semiconductor's BI-FET™ family of operational amplifiers. As such, designing with this part requires that several pre- cautions are observed which are uncharacteristic of other ‘op amps. Application Note AN-447 covers these caveats in greater detail for the whole product family. (The LH4104's input stage shares its topology with the LF400.) NEVER LEAVE AN INPUT UNATTENDED! If an input to the LH4104 is left open circuited (or connected to an analog multiplexer in a high impedance state), the input bias current will be drawn from the very small parasitic input capacitance (<10 pF). This capacitor will rapidly as TUK/e840-19 charge up to the power supply rail at a rate of dv/dt = FIGURE 1. Clamping inputs of Op Amp Igias/Cin. Since the LH4104 is a capable of large output currents and has no internal current limiting, it will easily be Vog ADJUSTMENT destroyed by excessive power dissipation if such an input Offset voltage can be nulled using a S6K resistor and a 25K condition exists while driving a low impedance load (e.g. potentiometer connected to pins 3 and 7 as shown in Figure 500). 3. Bypassing the Vog adjust pins with 0.1 1F capacitors will To avoid this condition in circuits where the LH4104 is buff- help to avoid noise pickup. When not used for offset adjust- ering the FET switch of an analog multiplexer, one must ment, pins 3 and 7 can often be lett open, but to minimize connect a resistor between the input and ground to provide the possibility of noise pickup the unused Vos trim pins a bias current path. This will invariably degrade the effective should be connected to ground or V~. input impedance of the device, so a large resistor is desir- able. Test Circuit for Pulse Response For example, selecting a 1 MQ resistor will result in a harm- less 25 mV output signal during the “deselected” state (for v the worst case bias current of 25 nA). Increasing this resis- tor will increase the output signal for the deselected” state; decreasing it will reduce this signal while degrading the in- Tye uF put impedance. Depending on the user's circuit specifica- pur —t ne tions, a compromise must be selected. This resistor will not 2a OUTPUT j introduce an increase in the effective offset voltage during A ro ° the “selected” state because the input is driven by a low 1 | impedance source. rg H POWER SUPPLY SEQUENCING VPage Tor ur i Adding the clamp diodes shown in Figure 7 not only pro- = = tects the inputs from transients when the circuit is operating, Joon = : but protects them as power is being applied to the circuit. Because the parasitic transistor apears when the input voit- (77 : age is less than the negative supply, applying the positive Tuk/e840-6 supply or input voltage before the negative supply is applied FIGURE 2* can cause this problem. For this reason, it is always recom- *Pinouts shown are for the metal can package (LH4104G or LH4104CG) 3-258
2 OF =
FIGURE 3. Offset Null*