LH4003

LH4003 NSC | Alldatasheet

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Technical content

$ GA National PRELIMINARY = rf a Semiconductor oO = | LH4003/LH4003C Precision RF Closed Loop Buffer a General Description Features The LH4003 is a precision RF buffer optimized for unity gain ™ Operation from +6V supplies applications. The LH4003 features a small signal bandwidth = ™ Drive 509 directly ‘of 250 MHz. The buffer is internally compensated to be unity ™ Internal power supply bypassing gain stable and has internal short circuit protection. The —™ Short circuit protection LH4003 is useful in applications such as video buffering, g 4090 V/s slew rate cable driving, and flash converter input conditioning. § 0.97 gain accuracy into 509

Applications

@ Line drivers ® Video buffers Block and Connection Diagram we 10] (J 24 NC nc 20 0) 23 NC +INPUT 30) (122 NC nc 40) C) 21 NC Nc 5) O20 NC nc 60) O19 NC 5 70 (118 +V; nc 8) (J17 GND GND 90) 0116 -INPUT nc 100) V/ 88 15 NC ne 110) (114 FEEDBACK NC 120) eae 13 OUTPUT Note 1: NC = No Connection Note 2: Pins 9 & 17 Internally Connected ‘TLIK/9243-1 Top View Order Number LH4003D, LH4003CD See NS Package Number D24D 4-30

r . = Absolute Maximum Ratings 3s {f Milltary/Aerospace specified devices are required, Output Short Circuit Duration Continuous 8 please contact the National Semiconductor Sales Operating Temperature Range, Ta re Office/Distributors for availability and specifications. LH4003CD -2ctotesc | & ‘Supply Voltage, Vs +8V LH4003D ~55°C to + 125°C 3 Power Dissipation, Pp Storage Temperature Range, Tstg -E5Cto+150C | B Ta = 25°C, derate linearly at 62.5°C/W 2w Maximum Junction Temperature, Ty ec | O To = 25°C, derate linearly at 33.3°C/W 3.75W Lead Temperature (Soldering, 10 sec.) 300°C Input Common Mode Voltage Range, Vom +Vs Output Current, Io £100 mA | amas | bate (Max Unless. ‘Symbol Parameter " tr Tested Limit | Design Limit | Otherwise YP | (Note 2) (Note 3) Stated) Vos __| Output Offset Voltage | Ta = Ty = 25°C fs/| «6 | | mw Vosvar | OsetVottage Drit | (Note 4) Ee Ip Input Bias Current Rg = 3009, Ta = Ty = 25°C A (Note 4) » Vo | Outputvotage swing | ein PSRR Power Supply Vs = +4V to +8V dBase Rejection Ratio (Min) | SupplyCurent | = 1knwote7) [ss | es [Tm Po | Poworvissipation [TE reo | LH4003c Units (Max Unless: Symbol Conditions : ym tT Tested Limit | Design Limit | Otherwise YP | (Note 2) (Note 3) Stated) ns sr | SiewRete Viv= =svi0+3v | 10%-90% | roof [800g fap _| Small Signal Bandwidth | Vour = 100 mVp-p [250 | 200 | —*'| MHz (Min) FullPowerBandwicth | Viv= 22v,(Notes) | os ||| 4 | Harmonic Distortion Second Order, Vout = 4V p-p, 8 Sin = 10 MHz 4-31

(Max Unless 2 | Symbol a = Typ | Tested Limit Otherwise = YP! (Note 2) Stated) noe ee lb Input Bias Current remo =3002 = [Ta=Ty=26°C,(Note4)| 100] 200 | S| us Ay | Voltage Gain Viw=2Vep [R= 50n [ose] oss | oes | Vo. | Output Vottage Swing | Ay = +1 | | ss [+s J ov es Po ___| Power Dissipation es unl (Max Unless Symbol typ | Tested Limit Otherwise P | (Note 2) Stated) Vin = +3V to — = (Min) iN to —3V | 10%-90% 1000 f—3.48 | Small Signal Bandwidth | Vor = 100 mVp-p [ 250 | 200 =| S| (Min Ful Power Bandwidth | Vy ~ Z2V. (Noto 5) Des ||| Harmonic Distortion Second Order, Vout = 4V p-P, dB Sin = 10 MHz Note 1: These measurements are taken with the LH4003 strapped for a gain of +1. Note 2: Tested limits are guaranteed and 100% tested in production. Note 3: Design limits are guaranteed (but not 100% production tested) over indicated temperature and supply voltage ranges. These limits are not used to calculate outgoing quality levels. Note 4: Specification is at 25°C junction temperature due to requirements of high speed automatic testing. Actual values at operating temperature will exceed value at Ty = 25°C. See Typical Performance Characteristics for more information. Note 5: Full power bandwidth is calculated based on slew rate measurement using FPBW = slew rate / (2 7V peak). Note 6: Bokdface limits are guaranteed over full temperature. Operating ambient temperature range of LH4003C is —25°C to + 85°C, and LH4003 is — 55°C to ++ 125°C. Note 7: When the LH4003 is operated at elevated temperature (such as 125°C), some form of heat sinking or forced air cooling is required. The quiescent power with Vg of +6V is 780 mW, whereas the package is rated to 750 mW without a heatsink at 125°C. 4-32

. = Typical Performance Characteristics 5 Maximum Power Input Blas Current Offset Voltage (Typical) EJ Dissipation vs Time vs Time ec 80 pe 110 5 = pe a | ro ITT TTT “ssec| MUTT | MTT Tt] 5 woL_l i ji tt = wl MTT | — eet E.R TTT 3 eit T MUTT TT F Pees 8 2 x| | Nos! 7 | wT ri eT : 25| —,__N foeesssie7M| eo ope ase) SS TTT eased) pg a g TT TTT [| 8 TTT i is; IT NT vo FeTTo Lasoe] z So Biaeoe SONI) g Sn ee os Cases] NN alt MT Tt = o_ Ltt TT | MT TT MMT WT 0 2 1 7 10 125 150 “1 1 10 4 fi 10 TEMPERATURE (°C) TE (WIN) TIME (MIN) TUK/0243-2 TL/k/9243-10 TUK/9269-11

Application Information

The unity gain follower configuration shown in Figure 1, of- Although the LH4003 contains internal decoupling, it still fers a 250 MHz smail signal bandwidth to the —3dB point requires some external bypassing capacitors, which have to ang ne iow rate bead ps insures a he Powe pe jocated as coe bin suey pins as possible. pee rig fidth of iz for a 4V peak-to-pet ignal, accord- in parallel with a 100 nF low inductance capacitor will insure ing to the formula: good filtering. In some cases of noisy environment, or when B= SR/24Vp the power supply is located far from the circuit, it may be Where SR is the slew rate in ps, B is the bandwidth of the Necessary to use @ dual stage decoupling as shown in Fig- device in MHz for a peak sine wave voltage Vp. oo 5 "] leo be iderabl ol th The unity gain follower/buffer is therefore an excellent round can also become a considerable problem. It is as- choice for wideband sinewave butfering or pulse ampliica. SUT To be Unltormly Zar0 voll ar ot owen tion. Figure 2 shows the typical pulse response for such a Spit q i ly , every configuration. gle point may be at a dif ferent potential and at a different phase, which is a source of instability or signal distortion. DRIVING CAPACITIVE LOADS The most reliable solution to this problem is to have a ' Flash A/D, unterminated cables, etc, can exhibit up to ground plane that will minimize the parasitic inductance and 300 pF of capacitance, thus creating stability or settling therefore, potential and phase differences. problems. Figure 3 shows the compensation scheme for orving such capacitive Jonge wie osu getimurs The input capactence of the LH4003 is typically 8 pF and settling. The output current limit of the is a consid- | erable help for driving capacitive loads, the charging current will slightly increase with frequency. A large source resist- t is kept in control and the damping resistor can be small ance value in front of this will form a pole, which may sub- i without overloading the output stage. A 202 resistor in se- a reduce the bandwidth of the circuit and affect sta- i ties with the capacitance is required for insuring an optimum lity. | settling time of 0.5% in less than 20 ns which is suitable for This is the reason why resistor values higher than 500 ohms | driving a 7 bit flash A to D converter in video applications at should not be utilized in the feedback network and high i a sampling rate of 20 MSPS (see Figure 4). source impedance should be avoided. i LAYOUT CONSIDERATIONS BIAS CURRENT | The layout of a RF/Video PC board where the signal fre- The input bias current is typically 100 A and may create an ' quency is beyond 100 MHz required special attention. All undesirable output offset voltage when the source imped- i the traces or connections must be as short and as wide as ance is high. An interna! 502 resistor is provided for match- possible in order to keep their parasitic inductance to a mini- ing with a 509 source impedance in order to minimize the mum. This is especially critical for the supply lines where the ‘output offset voltage. Figure 6 shows a circuit that uses a current can reach over 100 mA in a few nanoseconds. FET transistor pair for the input stage in order to reduce the input bias current to the sub-nanoampere region. 4-33

7 TLK/9243-3

FIGURE 1. Unity Gain Follow, Note: Top trace is input and bottom trace is output. Veg = +6V,Rs = Ry = 500. FIGURE 2. Pulse Response of Follower

180 N [13 200

FIGURE 3. Driving Capacitance