LH245A

SN74LVCC3245A TI | Alldatasheet

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DB, DBQ, DW, NS, OR PW PACKAGE (TOP VIEW) VCCA DIR GND GND V CCB NC OE GND NC - No internal connection DESCRIPTION/ORDERING INFORMATION SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 Bidirectional Voltage Translator 2.3 V to 3.6 V on A Port and V to 5.5 V on B Port Control Inputs V IH IL Levels Are Referenced to V CCA Voltage Latch-Up Performance Exceeds 250 mA Per JESD ESD Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track V CCB which accepts voltages from V to 5.5 and the A port is designed to track V CCA which operates at 2.3 V to 3.6 This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a 3.3-V system environment and vice versa. The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable OE input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE is powered by V CCA ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of SN74LVCC3245ADW SOIC DW LVCC3245A Reel of 2000 SN74LVCC3245ADWR SOP NS Reel of 2000 SN74LVCC3245ANSR LVCC3245A SSOP DB Reel of 2000 SN74LVCC3245ADBR LH245A C to C SSOP (QSOP) DBQ Reel of 2500 SN74LVCC3245ADBQR LVCC3245A Tube of SN74LVCC3245APW TSSOP PW Reel of 2000 SN74LVCC3245APWR LH245A Reel of 250 SN74LVCC3245APWT (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH TRANSCEIVER) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 1996 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DIR OE To Seven Other Channels Absolute Maximum Ratings (1) SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CCA Supply voltage range 0.5 V V CCB All A ports (2) 0.5 V CCA 0.5 V I Input voltage range All B ports (3) 0.5 V CCB 0.5 V Except I/O ports (2) 0.5 V CCA 0.5 All A ports 0.5 V CCA 0.5 V O Output voltage range (3) V All B ports 0.5 V CCB 0.5 I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through V CCA V CCB or GND 100 mA DB package DBQ package θ JA Package thermal impedance (4) DW package C/W NS package PW package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This value is limited to 4.6 V maximum. (3) This value is limited to V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7.

www.ti.com Recommended Operating Conditions (1) SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 V CCA V CCB MIN NOM MAX UNIT V CCA Supply voltage 2.3 3.3 3.6 V V CCB Supply voltage 5.5 V 2.3 V V 1.7 2.7 V V V IHA High-level input voltage V V 3.6 V 3.6 V 5.5 V 2.3 V V 2.7 V V V IHB High-level input voltage V V 3.6 V 3.6 V 5.5 V 3.85 2.3 V V 0.7 2.7 V V 0.8 V ILA Low-level input voltage V V 3.6 V 0.8 3.6 V 5.5 V 0.8 2.3 V V 0.8 2.7 V V 0.8 V ILB Low-level input voltage V V 3.6 V 0.8 3.6 V 5.5 V 1.65 2.3 V V 1.7 2.7 V V High-level input voltage (control pins) V IH V (referenced to V CCA V 3.6 V 3.6 V 5.5 V 2.3 V V 0.7 2.7 V V 0.8 Low-level input voltage (control pins) V IL V (referenced to V CCA V 3.6 V 0.8 3.6 V 5.5 V 0.8 V IA Input voltage V CCA V V IB Input voltage V CCB V V OA Output voltage V CCA V V OB Output voltage V CCB V 2.3 V V 2.7 V V I OHA High-level output current mA V V 2.7 V 4.5 V 2.3 V V 2.7 V V I OHB High-level output current mA V V 2.7 V 4.5 V 2.3 V V 2.7 V V I OLA Low-level output current mA V V 2.7 V 4.5 V (1) All unused inputs of the device must be held at the associated V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 Recommended Operating Conditions (continued) V CCA V CCB MIN NOM MAX UNIT 2.3 V V 2.7 V V I OLB Low-level output current mA V V 2.7 V 4.5 V Δ Δ v Input transition rise or fall rate ns/V T A Operating free-air temperature C

www.ti.com Electrical Characteristics SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CCA V CCB MIN TYP MAX UNIT I OH 100 µ A V V 2.9 I OH mA 2.3 V V 2.7 V V 2.2 2.5 V OHA I OH mA V V V 2.4 2.8 V V 2.2 2.6 I OH mA 2.7 V 4.5 V 2.3 I OH 100 µ A V V 2.9 2.3 V V 2.4 I OH mA V OHB 2.7 V V 2.4 2.8 V V V 2.2 2.6 I OH mA 2.7 V 4.5 V 3.2 4.2 I OL 100 µ A V V 0.1 I OL mA 2.3 V V 0.6 V OLA I OL mA 2.7 V V 0.1 0.5 V V V 0.2 0.5 I OL mA 2.7 V 4.5 V 0.2 0.5 I OL 100 µ A V V 0.1 I OL mA 2.3 V V 0.4 V OLB V V V 0.2 0.5 I OL mA 2.7 V 4.5 V 0.2 0.5 3.6 V 0.1 I I Control inputs V I V CCA or GND 3.6 V µ A 5.5 V 0.1 I OZ (1) A or B ports V O V CCA/B or GND, V I V IL or V IH 3.6 V 3.6 V 0.5 µ A A port V CCA or GND, I O 3.6 V Open I CCA B to A 3.6 V µ A B port V CCB or GND, I O 3.6 V 5.5 V 3.6 V I CCB A to B A port V CCA or GND, I O 3.6 V µ A 5.5 V V I V CCA 0.6 Other inputs at V CCA or GND, A port 3.6 V 3.6 V 0.35 0.5 OE at GND and DIR at V CCA V I V CCA 0.6 Other inputs at V CCA or GND, Δ I CCA (2) OE 3.6 V 3.6 V 0.35 0.5 mA DIR at V CCA V I V CCA 0.6 Other inputs at V CCA or GND, DIR 3.6 V 3.6 V 0.35 0.5 OE at GND V I V CCB 2.1 Other inputs at V CCB or GND, Δ I CCB (2) B port 3.6 V 5.5 V 1.5 mA OE at GND and DIR at GND C i Control inputs V I V CCA or GND Open Open pF C io A or B ports V O V CCA/B or GND 3.3 V V 18.5 pF (1) For I/O ports, the parameter I OZ includes the input leakage current. (2) This is the increase in supply current for each input that is at one of the specified voltage levels, rather than V or the associated V CC

www.ti.com Switching Characteristics Operating Characteristics Power-Up Considerations (1) SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 over recommended operating free-air temperature range (unless otherwise noted) (see Figure through Figure V CCA 2.5 V V CCA 2.7 V TO V CCA 2.7 V TO 0.2 3.6 3.6 FROM TO V CCB 3.3 V V CCB V V CCB 3.3 V PARAMETER UNIT (INPUT) (OUTPUT) 0.3 V 0.5 V 0.3 V MIN MAX MIN MAX MIN MAX t PHL 9.4 7.1 A B ns t PLH 9.1 5.3 7.2 t PHL 11.2 5.8 6.4 B A ns t PLH 9.9 7.6 t PZL 14.5 9.2 9.7 OE A ns t PZH 12.9 9.5 9.5 t PZL 8.1 9.2 OE B ns t PZH 12.8 8.4 9.9 t PLZ 7.1 6.6 OE A ns t PHZ 6.9 7.8 6.9 t PLZ 8.8 7.3 7.5 OE B ns t PHZ 8.9 7.9 V CCA 3.3 V CCB T A C PARAMETER TEST CONDITIONS TYP UNIT Outputs enabled C pd Power dissipation capacitance per transceiver C L 50, f MHz pF Outputs disabled 4.5 TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. To guard against such power-up problems, take these precautions: Connect ground before any supply voltage is applied. Power up the control side of the device CCA for all four of these devices). Tie OE to V CCA with a pullup resistor so that it ramps with V CCA Depending on the direction of the data path, DIR can be high or low. If DIR high is needed data to B bus), ramp it with V CCA Otherwise, keep DIR low. (1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices literature number SCEA021.

www.ti.com PARAMETER MEASUREMENT INFORMATION FOR A PORT VCC/2 VCC/2 VCC/2VCC/2 VCC/2VCC/2 VCC/2VCC/2 VOH VOL thtsu From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 500 Ω 500 Ω Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH - 0.15 V 0 V VCC 0 V 0 V tw VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. 0 V VCC VCC/2 tPHL VCC/2 VCC/2 VCC 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VCC/2 tPLH 2 × VCC VCC SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 V CCA 2.5 V 0.2 V AND V CCB 3.3 V 0.3 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION FOR B PORT VCC/2 VCC/2 VCC/2VCC/2 VCC/2VCC/2 VCC/2VCC/2 VOH VOL thtsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 Open GND 500 Ω 500 Ω Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH - 0.15 V 0 V VCC 0 V 0 V tw VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. 0 V VCC VCC/2 tPHL VCC/2 VCC/2 VCC 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VCC/2 tPLH 2 × VCC VCC SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 V CCA 2.5 V 0.2 V AND V CCB 3.3 V 0.3 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION FOR B PORT From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT 2 × VCC Open GND 500 Ω 500 Ω VCC 0 V tw VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL VOH VOL Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at Open (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ VCC 0 V VOL + 0.3 V VOH - 0.3 V ≈ 0 V 2.7 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING B-Port Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf/char????????≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. 50% VCC50% VCC B-Port Input VCC 0 V Input 50% VCC 50% VCC 50% VCC50% VCC 1.5 V 1.5 V 1.5 V 1.5 V SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 V CCA 3.6 V and v CCB 5.5 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT 7 V Open GND 500 Ω 500 Ω 2.7 V 0 V tw VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL VOH VOL Output Control Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 3.5 V 0 V VOL + 0.3 V VOH - 0.3 V ≈ 0 V 2.7 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7 V Open TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf/char????????≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Input 2.7 V 0 V Input 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V SN74LVCC3245A OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS SCAS585O NOVEMBER 1996 REVISED MARCH 2005 V CCA AND V CCB 3.6 V Figure Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74LVCC3245ADBQRE4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR 74LVCC3245ADBQRG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LVCC3245ADBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI SN74LVCC3245ADBQR ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LVCC3245ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245ADW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245ADWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245ANSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245ANSRE4 ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245APW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245APWLE OBSOLETE TSSOP PW 24 TBD Call TI Call TI SN74LVCC3245APWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245APWT ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCC3245APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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