LH0084 NSC | Alldatasheet
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c National 3 J Semiconductor = re LH0084/LH0084C Digitally-Programmable-Gain g Instrumentation Amplifier General Description The LHO084/LHO084C is a self-contained, high speed, high The LH0084 is guaranteed from —55°C to +125°C. The accuracy, digitally-programmable-gain instrumentation am- _ LHO084C is guaranteed from —25°C to +85°C. Both devic- Plifier. It consists of paired FET-input variable-gain voltage- _es are provided in a hermetically sealed 16-lead dual-in-line follower input stages followed by a differential-to-single- metal package. ended output stage. The input stage is programmable in accurate gain steps of 1, 2, 5, or 10 controlled by the logic +Features levels of a 2-bit TTL-compatible digital input word. For add- @ Excellent gain accuracy 0.075% max tional flexibility, the output stage is pin-strappable to fixed and low gait near i. 4 gain non-linearity 0.01% typ gains oft, 4,0r 10 for an overall gain range of 1 to 100. = Extremely low gain drit 1 ppm/*C typ Applications include increased dynamic range A-to-D con- 40 Po mi verters, test systems, and post multiplexer amplifier for data - . Ppm " ax acquisition systems. . High input impedance 10 ‘Atyp The device exhibits high input impedance, low offset vor- SHighPSRA 70 dB min age, high PSAR, high speed, and excellent gain accuracy # TTL compatible digital inputs and gain non-linearity. @ High speed, settling to 0.1% 4 ps max ee Simplified Schematic and Connection Diagrams v wnt, > Dual-tn-Line Package i 1 in | “ oo DIGITAL | ' ve 16 4, { ur | oxi 7 E mw vy 1 oyairat ono ‘ 1a | oxi nt sot 1 7 10 | oot! E ems | * WORE) ° A , DWGITAL {r olf. E "vot x10) Min(-) | orgitaL M4) (FORCE) | ‘uo E Tor VIEW ! E mt @ Case is electrically isolated ' oni i aa na 2 ogg | SIONAL Order Number LH0084D or LH0084CD | ono ‘See NS Package D16D ais s fa fo 285 38 TUH/se51—1 6-25
[s} zs 8| Absolute Maximum Ratings 2 If Military/Aerospace specified devices are required, Power Dissipation (Note 5) 2.5W a Please contact the National Semiconductor Sales Output Short Circuit Duration Continuous = Otfice/Distributors for availability and specifications. Operating Temperature Range r=) LHOOS4 —55°C to + 125°C | Supply Voltage (Note 1) £18V LHO084C —25°C to +85°C 1] Analog Input Voltage (Note 2) #15V Lead Temp. (Soldering, 10 seconds) + 260°C Differential Input Voltage (Note 2) +30V ESD rating to be determined. Digital Input Voltage —4V, +18V Symbol Parameter Units [emer [cent pa a a =~“ a Te _ Change with Temperature Voem=0 Voos (oie) [iewe[ [ests [| os [wo a = PPT | re _ Change with Temperature m Ciease [| ve | 00 || ve0 | 520 [pa (Note 4) es Pot eo Pf 0 | Rin InputResistance | Differential | ton ||| ort | [Commonmode | sf vor | TP ton | | O Ay Voltage Gain See Table | 1 1 2 2 5 5 10 10 viv 20 20 50 50 100 100 Tanase [Looe | or [| 003 | 2 | [[ooe [oe | [ooefoz| ,, pesca [ee home foe PT feof fooos | Sl OB a Coefficient MRR | Common-Mode Vin= £10V [av=1 [vo [eo | | 7} eo | | [Av=i00 | eo | 9 | [eo | om | | PsRR | Power Supply zevevgettev [ay=t [70 |e [| 70 |e [| op Rejection Ratio [av=10 | ve [ oe | [7 | 2 [| [Ay=i00 | a0 [tos | | a0 | toa | | Vo | OuipavonageSung [asim == tof ee] fete] |v 6-26
c J symbol Conditions |___tHooea_ | unis |= [rome [min [typ [max [win [typ [Max | c Viv Digital “0” 07 07 Input Voltage v Vie Digital “1” Input Voltage " input Cur pwr | [ele] [ele] Input Current pA ha Digital “1” Vin=2.4V Input Current Vg ‘Supply Voltage £8 +18 | +8 £18 v Range Ig(+) Positive Supply 18 Current mA Is(-) Negative Supply Vas +18V 12 Current Po Powerbissipation | vem sisv | [ais | aso | {ats | 600 | mw Symbot_| Parameter [| Gonaitions | in_ | Typ | Max | Units Bw Bandwidth (Figure 1) Small Signal, [aver | | aso [| | averoo [of aso fe Small Signal [aver [| ao || ~1% | aver [fo || [ averoo | [ss | | SR po [ow fT vas s Setting Time (Figure 2) | AVo= £20V [aver [| 2a [30 | [ av=i00 [| aa [so | En Equivalent input BW=0.1 Hz—10 Hz [| 7 | [| upp Noise Voltage (Figures) | BW=10H2-10KHZ | 4 sop [| | 14 | [nvm In Equivalent Input BW=10 Hz—10 kHz pArms Noise Current (Figure 3) Note 1: Improper supply power-on sequence may damage the davice. See Power Supply Connection section under Applications Information. Note 2: For supply voltages less than + 15V the maximum input voltage is equal to the supply voltage. Note 3: These parameters are specified at junction temperatura, T,. In normal operation the junction temperature rises above the ambient temperature, Ta, as a result of internal power dissipation, Pp. T)= T+ @jaPp where ja |s the thermal resistance from junction to ambient. Note 4: The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature. Note 5: See Typical Performance Characteristics for Thermal Resistance Information. Note 6: Refer to RETS0084D for LHO084D military specifications. 6-27
3 Typical Performance Characteristics
o a Power Dissipation : Gain Accuracy i Input Bias Current 3 , “ === Bla] eee | , pa =| § Sa oain 2 | Hats stl 2 SoZ a eth i====== 3 s 4 ==> SSS H N A ae a= “CELT eee ie Ol we ed cw ws we mm 1 ' . rm rere re eT renrenavune 0 cami ueient TeneenATURE C1 Small Signal * Frequency Response Common-Mode Rejection w Power Supply Rejection oe oe . ea meena ioe a aiesayi), SU eee yy Nell ™ a ees! a PSPs
2 HHT INN STN
ecccimniuiimti | » , Hee Hh Bh: » WITT ETT TI Lee! THM Ti wt ee wm . oe hm FREQUENCY We) FREQUENCY te) FREQUENCY Input Common-Mode - Range . ‘Supply Current i” Output Swing ett, :EEEEEB COT a g Lf, | re s Fy \\ 7 ee Pee el (peraene ee ese LZ TT peer ~ LLU | sw rT rr rr ‘SUPPLY VOLTAGE (:¥}. ‘SUPPLY VOLTAGE (:V) OUTPUT CURRENT (:mA) Equivalent Input Noise Voltage (Includes Broadband Output
1 Settling Time ww Source-Resistance Noise) 3 Nolse Voltage
3°) ae Sn NMA mil | 3 . Tare Cal a ei ge ae eg ee An 2 Fog & eer 2 aot ed al : “he Se mn Faery a A ° LCA Tn) og Pag a I 1 w 190 10 100k Ok a o41 fr ™ GAIN (V/V) FREQUENCY (Hz) Ay (VN) runsest-2 6-28
(5) z eae . 8] Applications Information S| THEORY OF OPERATION and bo and set the gain of the input stage as shown in =| The LHo084 is a digitally-programmable-gain true-instru- able |. _ ; & | _ mentation amplifier composed of a variable-gain voltage-fol- fe fr oxample, rae niet Geo) and 00 is row (0.7V), S | _ lower input stage (A1 and A2), followed by a differential out- FET switch pair S3A and S3B will be closed (and all remain- = put stage (A3). The schematic is shown in Figure 4. ing suns open). The input stage gain, Ay(1), can then be | The input stage contains matched high-speed FET-input op shown to be: amps (A1 and A2). A high-stability temperature-compensat- v2-V1 ed resistor network (R1 through R7) controls feedback ra- AVN =F ovala) (+)—Vint) tios at the inverting inputs of op amps A1 and A2 via FET IN iN switches S1A-S4A and S1B-S4B. Since the FET switches 214 R4+RS+R6+R7 are in series with the op amp input impedance their resist- R1+R2+R3 ance match and temperature drift do not degrade the gain accuracy of the instrumentation amplifier. The FET switches = 14 SRT 8K + 10k + 10k are controlled through a 1-of-4 decoder and switch driver, 4k + 2k+2k by the logic levels applied at the digital input terminals D1 =5 Schematic Diagram v Vint) om® 1 > ut M iii bela | tes - Sox’ sa hl Lit | - om -}-4 Lo | ” | re | | R10 we I -fr4 w fox ! wm | | 0 not a orarraL ‘AND t wNPUT 6 swiTcH 8
00 DRIVER 10 Vour
4 ° © ifthe) DIGITAL ot -t- | GNO | Pr] | | 1° -t-4 RNY | es | jo 3561 l ne = sw 2 | A a ies " ts | -t-7 i fm | ne Dee | No cw Vint) 2 J & é é was WF TLH/s651-6 FIGURE 4 6-30
1 P 5 7-10, 12-GND 20
through R15, converts the voltage difference at the output Proper power supply connections are shown in Figure 5. Ree Riae Rt ne 3s fese0ck rsitor for a. ape ratios of #F ceramic disc in parallel with a 1 pF electrolytic capacitor. i AVQ)=Fo—vi avoid CMAR degradation. | To preserve the high common-mode rejection ratio of the the digital ground pin and the V~ pin as shown in Figure 5. FIGURE 5. Power Supply Connections
3 Applications Information (continued)
3 kept as small as possible. the LH0084 to ground. sense in order to minimize lead resistance and parasitic ca- b) Set the input stage gain to 10 (pull D1 and DO high). all gain settings. ; voltage is equal to the voltage calculated in Equation (4).
- The output stage offset (Voos) is ideally adjusted at a voltage Is zero.
FIGURE 6. Signal Connections FIGURE 7. Offset Adjust Circult
drift and common-mode voltage error contributions. subsequent gain stage. resistance (Figure 10).
3 Polypropylene Dielectric
FIGURE 8. Auto Zero Circuit FIGURE 9. Typical Microprocessor Interface FIGURE 10. Remote Sense Connection
8 Applications Information (continues)
S| __ pability as shown in Figure 17. Figure 13. FIGURE 11. Buffered Output Connection FIGURE 12. Output Offset Connection | A software offset and gain error correction scheme is shown matically by solving a simple first-order equation in software. FIGURE 14. Typical Data Acquisition System
FIGURE 15. Software System Offset and Gain Calibration Circuit ‘OV. Viog can be calculated by measuring Vog (RTO) at in- percent of full-scale (10V for operation with +15V supply). 2 analog input terminals at OV. input voltage change producing it.
LS) 8 | Definition of Terms (continues) x Output Voltage Swing, Vo: The peak output voltage swing Average Gain Temperature Coefficient, AA,/AT: The ra- > | referenced to ground into specified load. tio of change in gain from 25°C to either temperature ex- P= Output Short-Circult Current, Ig: The current supplied by _tfeme divided by the temperature range. © | the device with the output connected directly to ground. ‘Small Signal Bandwidth, BW: The frequency at which the 5 Output Resistance, ro: The ratio of change in output volt-__ device gain changes from the low frequency gain by a spec- age to change in output current around zero output. ified amount. Supply Voltage Range, Vg: The supply voltage range for Power Bandwidth, PBW: Maximum frequency for which which the device is operational. the output swing is a large signal sinewave without notice- Supply Current, Ig: The current required from the supply to 201e distortion. ; ; operate the device with zero load and with the analog as Slew Rate, SR: The internally limited rate of change in out- well as the digital inputs at OV. put voltage with a large amplitude step function applied at Power Dissipation, Pp: The power dissipated in the device te input. ; a ; with zero load and with the analog as well as the digital Settling Time, ts: The time between the initiation of an input inputs at OV. step function and the time when the output voltage has set- Digital “1” Input Voltage, Vig Minimum voltage required _ 6d to within a specified error band of the final output volt- at the digital input to guarantee a high logic state. age. Digital “0” Input Voltage, Viz: Maximum voltage required Gain Switching Time: The time between the initiation of a vn s MIL? " gain logic change and the time when the final gain switches at the digital input to guarantee a tow logic state. re closed. It includes overdrive recovery time, but not set- cia 1 input Current, Iw: The current into a digital ing to final value. pat al Speck ad logic level. . nn Equivalent Input Noise Voltage, Ey: The rms of peak Digital “0” input Current, Ii,: The current into a digital in- poise voltage referred to the input (RTI) over a specified put at specified logic level. frequency band. Average Input Offset Voltage Drift, AVios/AT: The ratio Equivatent Input Noise Current, Iy: The rms of peak noise of input offset voltage change from 25°C to either tempera- current referred to the input (RTI) over a specified frequency ture extreme divided by the temperature range. band. Average Output Offset Voltage Drift, AVoos/AT: The ra- tio of output offset voltage change from 25°C to either tem- perature extreme divided by the temperature range. 6-36