LF6197

LF6197 NSC | Alldatasheet

Document overview

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Technical content

Features

Y Operates with supply voltages from g5V to g18V Y CMOS, TTL and ECL compatible logic input Y Adjustable inverting or non-inverting gain Y Internal hold capacitor Y High power-supply rejection in both sample and hold modes Key Specifications Y Acquisition time (10V step to 0.01%) 160 ns Y Hold mode settling time (10V step to 0.01%) 50 ns Y Droop rate 0.6 mV/ms Y Hold step 10 mV Y Aperture jitter 8 ps rms Y Feedthrough attenuation at DC 83 dB Y Small signal bandwidth 25 MHz

Applications

Y High-speed data acquisition systems Y Automatic test equipment Y High-speed instrumentation Y Replaces expensive hybrid sample-and-hold amplifiers Block Diagram TL/H/11381–1 Connection Diagram TL/H/11381–2 Top View

Ordering Information

Industrial Package(0§C k TAk a70§C) LF6197CCJ J14A Ceramic DIP C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1, 2) Positive Supply Voltage (V a) a18V Negative Supply Voltage (V b) b18V Analog Input Voltage V a or V b or g12.5V, whichever is less Logic Input to LR1 Differential Voltage g5V Power Dissipation (Note 3) 1.2W Duration of Output Short Circuit to GND (Note 4) ESD Susceptibility All Pins except Pin 13 (Note 5) 2000V Pin 13 only (Note 5) 1500V Lead Temperature (Soldering, 10 sec.) J Package 300 Storage Temperature b65§Ct o a150§C Operating Ratings (Notes 1, 2) Temperature Range T MIN s TA s TMAX LF6197CCJ 0 §C s TA s a70§C Positive Supply Voltage a4.75V s Va s a15.75V Negative Supply Voltage b15.75V s Vb s b4.75V

Electrical Characteristics

Unless otherwise specified, the following specifications apply for V a ea 15V, V b eb 15V, b12V s VIN s a12V, RL l 1k X,C L s 40 pF, Logic Reference 2 (LR2) voltage e 0V and Logic Input Voltage k 1.4V threshold, (Unit is in ‘‘sample’’ mode). V S refers to the supply voltages, V a and V b. Boldface limits apply for T A e TJ from T MIN to T MAX; all other limits TA e TJ e 25§C. Symbol Parameter Conditions Typical Limit Units (Note 6) (Note 7) (Limit) INPUT CHARACTERISTICS VOS Input Offset Voltage g3.0 g6.0 mV (max) VS e g5V, (Note 8) g3.0 mV (max) DVOS/DT Input Offset Drift 15 mV/§C RIN, com Input Resistance (common mode) 10 M X RIN, dif Input Resistance (differential) 300 k X CMRR Common Mode Rejection Ratio V CM e g10V 100 80 dB (min) IBa Positive Input Bias Current 7 17 mA (max) IBb Negative Input Bias Current 1 7.5 mA (max) TRANSFER CHARACTERISTICS DC Open Loop Gain V OUT e g12V, R L e 1k X 70 65 dB (min) DC Open Loop Gain (Note 8) V S e g5V, V OUT e g2.5V 55 49 dB (min) Gain Error (Note 9) 0.03 % (max) Gain Linearity Error V OUT e g10V 0.003 0.0045 % (max) fu Gain Bandwidth Product 25 14 MHz (min) OUTPUT CHARACTERISTICS ROUT Output Resistance 0.02 X SR Slew Rate 145 V/ ms Short Circuit Source Current b63 b25 mA (min) Short Circuit Sink Current 70 25 mA (min) CL Maximum Capacitive Load No Oscillation 200 pF

Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for V a ea 15V, V b eb 15V, b12V s VIN s a12V, RL l 1k X,C L s 40 pF, Logic Reference 2 (LR2) voltage e 0V and Logic Input Voltage k 1.4V threshold, (Unit is in ‘‘sample’’ mode). V S refers to the supply voltages, V a and V b. Boldface limits apply for T A e TJ from T MIN to T MAX; all other limits TA e TJ e 25§C. Symbol Parameter Conditions Typical Limit Units (Note 6) (Note 7) (Limit) SAMPLE/HOLD CHARACTERISTICS tACQ Acquisition Time to 0.1% (Note 10) 10V step 130 ns to 0.01% (Note 10) a10V step 145 240 ns (max) 260 ns (max) b10V step 160 240 ns (max) 260 ns (max) tAD Aperture Delay Time 4 ns tAJ Aperture Jitter 8 ps rms Droop Rate 0.6 10 mV/ms (max) VHS Hold Step (Note 11) g10 mV (max) tHMS Hold Mode Settling Time to 0.01% 10V step 50 ns Feedthrough Attenuation (Note 12) f e 1 kHz, V IN e 20 V p-p 83 80 dB (min) f e 100 kHz, V IN e 20 V p-p 77 dB DYNAMIC CHARACTERISTICS THD Total Harmonic Distortion f e 10 kHz, V IN e 20 V p-p b83 dB f e 150 kHz, V IN e 20 V p-p b78 dB FPBW Full Power Bandwidth (Note 13) V IN e 20 V p–p 2.3 MHz Small Signal Bandwidth 25 MHz DIGITAL LOGIC CHARACTERISTICS VIN(1) Logical ‘‘1’’ Input Voltage 2.0 V (min) VIN(0) Logical ‘‘0’’ Input Voltage 0.8 V (max) Logic Input Current 6 20 mA (max) Logic Reference 2 Input Current 3 5 mA (max) Differential Logic Threshold 1.4 1.1 V(min) (Logic Input to LR1) 1.6 V(max) POWER SUPPLY CHARACTERISTICS ISa Positive Supply Current 20 30 mA (max) ISa Positive Supply Current V S e g5V (Note 8) 18.2 27 mA (max) ISb Negative Supply Current 20 30 mA (max) ISb Negative Supply Current V S e g5V (Note 8) 17.5 27 mA (max) PSRR Power Supply Rejection Ratio V S e g12V to g16V 84 74 dB (min)

Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T Jmax, HJA, and the ambient temperature T A. The maximum allowable power dissipation is P D e (TJmax b TA)/HJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T Jmax e 150§C and iJA e 125§C/W. The Power Derating Curve shows the safe thermal operating area for this device. Note 4: Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150 §C. Note 5: Human body model, 100 pF capacitor discharged through a 1.5 k X resistor. Note 6: Typicals are at T A e 25§C and represent the most likely parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Operation at g5V requires that pin 14 be forced to 2.5V. Note 9: Gain error is calculated from the measured open loop gain. Note 10: The acquisition time of the LF6197 has been measured when the device has been configured as an inverting amplifier with a gain of b1, feedback resistor of 2 k X, feedback capacitor of 1 pF, and a total load resistor of 1 k X. Note 11: Hold step is measured with the LF6197 configured as a unity gain follower and input connected to ground. A TTL pulse with 4 ns rise and fall times is applied to the logic input; the hold step is dependent on the slew rate of the logic input pulse. Note 12: See test circuit, Figure 1 . Note 13: Full power bandwidth is calculated using FPBW e SR/(2qVP); where SR is the measured slew rate and V P is the peak voltage.

Typical Performance Characteristics vs Capacitive Load Acquisition Time (to 0.01%) vs Capacitive Load Acquisition Time (to 0.01%) vs Temperature Acquisition Time (to 0.01%) vs Supply Voltage Acquisition Time (to 0.01%) vs Frequency Signal Feedthrough vs Frequency Signal Feedthrough Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Common Mode Rejection Ratio vs Frequency Common Mode Rejection vs Frequency Input Noise Voltage Response Open Loop Frequency TL/H/11381–3

Typical Performance Characteristics (Continued) Hold Step vs Logic Input Rise Time TL/H/11381–15 Power Derating Curve TL/H/11381–16

FIGURE 1. Circuit configuration for the measurement of feedthrough attenuation. Input is connected to ground in sample mode and is connected to 20 V PP, 100 kHz sine wave in hold mode. familiar op amp feedback topologies. driven from a low impedance source. this pin should remain unconnected. connected or connected to pin 10.

one end of the hold capacitor to a low impedance ground. FIGURE 2. Simplified Block Diagram of LF6197 Sample-and-Hold Amplifier, Connected for Unity Gain and TTL Logic

1.0 LOGIC CONFIGURATIONS

1.1 TTL Logic

1.2 CMOS Logic

1.3 ECL Logic

bypass LR1 with a 0.01 mF capacitor (Figure 7) .

2.0 ZENER REFERENCE OUTPUT

FIGURE 3. Biasing Pin 14 to 2.5V

3.0 ADJUSTING GAIN

diodes when the device is in the hold mode.

4.0 POWER SUPPLY SEQUENCING

FIGURE 4. TTL Logic FIGURE 5. CMOS Logic

LF6197 160 ns Monolithic Sample-and-Hold Amplifier Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number LF6197CCJ LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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