LF451

LF451 NSC | Alldatasheet

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Y Internally trimmed offset voltage 5.0 mV (max) Y Low input bias current 50 pA (typ) Y Low input noise current 0.01 pA/ 0Hz (typ) Y Wide gain bandwidth 4 MHz (typ) Y High slew rate 13 V/ ms (typ) Y Low supply current 3.4 mA (max) Y High input impedance 10 12X (typ) Y Low total harmonic distortion A V e 10, k0.02% (typ) RL e 10k, V O e 20 V p–p ,f e 20 Hz–20 kHz Y Low 1/f noise corner 50 Hz (typ) Y Fast settling time to 0.01% 2 ms (typ) Connection Diagram S.O. Package TL/H/9660–2 Top View Order Number LF451CM See NS Package Number M08A Typical Connection TL/H/9660–1 Simplified Schematic TL/H/9660–3 BI-FETTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V a b Vb) 36V Input Voltage Range V b s VIN s Va Differential Input Voltage (Note 2) g30V Junction Temperature (T J MAX) 150 §C Output Short Circuit Duration Continuous Power Dissipation (Note 3) 500 mW ESD Tolerance TBD Soldering Information (Note 5) Infrared (15 sec) 220 §C Operating Ratings (Note 1) Temperature Range T MIN s TA s TMAX LF451CM 0 §C s TA s a70§C Junction Temperature (T J max ) 125 §C Supply Voltage (V a b Vb) 10V to 32V face limits apply for T MIN to T MAX; all other limits T A e TJ e 25§C. LF451CM Symbol Parameter Conditions Typical Tested Design Units (Note 6) Limit Limit (Note 7) (Note 8) VOS Maximum Input Offset Voltage R S e 10 k X, (Note 10) 0.3 5 mV IOS Maximum Input Offset Current (Notes 9, 10) T J e 25§C 25 100 pA TJ e 70§C 2 nA IB Maximum Input Bias Current (Notes 9, 10) T J e 25§C 50 200 pA TJ e 70§C 4 nA RIN Input Resistance T J e 25§C1 0 12 X AVOL Minimum Large Signal V O e g10V, R L e 2k X 200 50 25 V/mVVoltage Gain (Note 10) VO Minimum Output Voltage Swing R L e 10k g13.5 g12 g12 V VCM Minimum Input Common Mode a14.5 a11 a11 V Voltage Range b11.5 b11 b11 V CMRR Minimum Common-Mode R S s 10 k X 100 80 80 dBRejection Ratio PSRR Minimum Supply Voltage (Note 11) 100 80 80 dBRejection Ratio IS Maximum Supply Current 3.4 3.4 mA face limits apply for T MIN to T MAX; all other limits T A e TJ e 25§C. LF451CM Symbol Parameter Conditions Typical Tested Design Units (Note 6) Limit Limit (Note 7) (Note 8) SR Slew Rate A V ea 11 3 8 V / ms GBW Minimum Gain-Bandwidth Product f e 100 kHz 4 2.7 MHz en Equivalent Input Noise Voltage R S e 100X,f e 1 kHz 25 nV/ 0Hz in Equivalent Input Noise Current R S e 100X,f e 1 kHz 0.01 pA/ 0Hz Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating ratings. Note 2: When the input voltage exceeds the power supplies, the current should be limited to 1 mA. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T J MAX, iJA and the ambient temperature, T A. The maximum allowable power dissipation at any temperature is P D e (TJ MAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For guaranteed operation T J max e 125§C. The typical thermal resistance ( iJA) of the LF451CM when board-mounted is 170 §C/W. Note 5: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ (Appendix D) for other methods of soldering surface mount devices. Note 6: Typicals are at T J e 25§C and represent most likely parametric norm.

Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Design limits are guaranteed to National’s AOQL, but not 100% tested. Note 9: The input bias currents are junction leakage currents which approximately double for every 10 §C increase in the junction temperature T J. Due to limited production test time, the input bias currents are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, P D.T J e TA a iJAPD where iJA is the thermal resistance from junction to ambient. Note 10: VOS,I B, AVOL, and I OS are measured at V CM e 0V. Note 11: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. Typical Performance Characteristics Distortion vs Frequency Voltage Swing Undistorted Output Response Open Loop Frequency Rejection Ratio Common-Mode Rejection Ratio Power Supply Noise Voltage Equivalent Input Gain (V/V) Open Loop Voltage Output Impedance Inverter Settling Time TL/H/9660–5

Typical Performance Characteristics (Continued) Input Bias Current Input Bias Current Supply Current Input Voltage Limit Positive Common-Mode Input Voltage Limit Negative Common-Mode Positive Current Limit Negative Current Limit Voltage Swing Output Voltage Swing Gain Bandwidth Bode Plot Slew Rate TL/H/9660–4

TL/H/9660–6 Small Signal Non-Inverting TL/H/9660–7 Large Signal Inverting TL/H/9660–8 Large Signal Non-Inverting TL/H/9660–9 Current Limit (R L e 100X) TL/H/9660–10 Application Hints The LF451CM is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit with the non-in- verting input, or with both inputs, will force the output to a high state, potentially causing a reversal of phase to the output. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode.

Application Hints (Continued) Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifier will operate with a common-mode input volt- age equal to the positive supply; however, the gain band- width and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. The LF451 is biased by a zener reference which allows nor- mal circuit operation on g4V power supplies. Supply volt- ages less than these may result in lower gain bandwidth and slew rate. The LF451 will driv ea2k X load resistance to g10V over the full temperature range of 0 §Ct o a70§C. If the amplifier is forced to drive heavier load currents, however, an in- crease in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power sup- ply for the integrated circuit never becomes reversed in po- larity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the result- ing forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in or- der to ensure stability. For example, resistors from the out- put to an input should be placed with the body close to the input to minimize ‘‘pick-up’’ and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capaci- tance from the input of the device (usually the inverting in- put) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. The benefit of the S.O. package results from its very small size. It follows, however, that the die inside the S.O. pack- age is less protected from external physical forces than a die in a standard DIP would be, because there is so much less plastic in the S.O. Therefore, not following certain pre- cautions when board mounting the LF451CM can put me- chanical stress on the die, lead frame, and/or bond wires. This can cause shifts in the LF451CM’s parameters, even causing them to exceed limits specified in the Electrical Characteristics. For recommended practices in LF451CM surface mounting refer to Application Note AN-450 ‘‘Sur- face Mounting Methods and Their Effect on Product Reli- ability’’ and to Section 6 ‘‘Surface Mount’’ found in any Rev. 1 Linear Databook volume. Detailed Schematic TL/H/9660–11

LF451 Wide-Bandwidth JFET-Input Operational Amplifier Physical Dimensions inches (millimeters) Lit. Ý 106161 Small Outline Package (M) Order Number LF451CM LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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