LF441 TI1 | Alldatasheet
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LF441 Low Power JFET Input Operational Amplifier Literature Number: SNOSC14A
LF441 Low Power JFET Input Operational Amplifier February 1995 LF441 Low Power JFET Input Operational Amplifier General Description The LF441 low power operational amplifier provides many of the same AC characteristics as the industry standard LM741 while greatly improving the DC characteristics of the LM741. The amplifier has the same bandwidth, slew rate, and gain (10 k X load) as the LM741 and only draws one tenth the supply current of the LM741. In addition, the well matched high voltage JFET input devices of the LF441 re- duce the input bias and offset currents by a factor of 10,000 over the LM741. A combination of careful layout design and internal trimming guarantees very low input offset voltage and voltage drift. The LF441 also has a very low equivalent input noise voltage for a low power amplifier. The LF441 is pin compatible with the LM741, allowing an immediate 10 times reduction in power drain in many appli- cations. The LF441 should be used where low power dissipation and good electrical characteristics are the major considerations.
Features
Y 1/10 supply current of a LM741 200 mA (max) Y Low input bias current 50 pA (max) Y Low input offset voltage 0.5 mV (max) Y Low input offset voltage drift 10 mV/§C (max) Y High gain bandwidth 1 MHz Y High slew rate 1 V/ ms Y Low noise voltage for low power 35 nV/ SHz Y Low input noise current 0.01 pA/ SHz Y High input impedance 1012X Y High gain V O e g10V, R L e 10k 50k (min) Typical Connection TL/H/9297–1
Ordering Information
X indicates electrical grade Y indicates temperature range ‘‘M’’ for military, ‘‘C’’ for commercial Z indicates package type ‘‘H’’ or ‘‘N’’ Connection Diagrams Metal Can Package TL/H/9297–2 Top View Note: Pin 4 connected to case. Order Number LF441MH/883 See NS Package Number H08A Dual-In-Line Package TL/H/9297–4 Top View Order Number LF441ACN, LF441CM or LF441CN See NS Package Number M08A or N08E BI-FETTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A. Obsolete
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. LF441A LF441 Supply Voltage g22V g18V Differential Input Voltage g38V g30V LF441A LF441 Input Voltage Range (Note 1) g19V g15V Output Short Circuit Duration Continuous Continuous H Package N Package M Package Power Dissipation 670 mW 670 mW(Notes 2 and 9) Tj max 150§C 115§C ijA(Typical) 130§C/W 185§C/W Board Mount in still air 165 §C/W Board Mount in 400 LF/ 65 §C/W min air flow ijC 25§C/W Operating Temp. Range (Note 3) (Note 3) Storage Temp. Range b65§C s TA s 150§C b65§C s TA s 150§C Lead Temperature 300 §C 260§C (Soldering, 10 seconds) LF441A LF441 Soldering Information Dual-In-Line Package Soldering (10 sec.) 260§C 260 §C Small Outline Package Vapor Phase (60 sec.) 215 §C 215 §C Infrared (15 sec.) 220 §C 220 §C See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering sur- face mount devices. ESD Tolerance (Note 10) Rating to be DeterminedDC Electrical Characteristics (Note 4) Symbol Parameter Conditions LF441A LF441 Units Min Typ Max Min Typ Max VOS Input Offset Voltage R S e 10 k X,T A e 25§C 0.3 0.5 1 5 mV Over Temperature 7.5 mV DVOS/DT Average TC of Input R S e 10 k X (Note 5) 71 0 1 0 mV/§COffset Voltage IOS Input Offset Current V S e g15V T j e 25§C 5 25 5 50 pA (Notes 4 and 6) Tj e 70§C 1.5 1.5 nA Tj e 125§C1 0 n A IB Input Bias Current V S e g15V T j e 25§C 10 50 10 100 pA (Notes 4 and 6) Tj e 70§C3 3 nA Tj e 125§C2 0 n A RIN Input Resistance T j e 25§C1 012 1012 X AVOL Large Signal Voltage V S e g15V, V O e g10V, 50 100 25 100 V/mVGain RL e 10 k X,T A e 25§C Over Temperature 25 15 V/mV VO Output Voltage Swing V S e g15V, R L e 10 k X g12 g13 g12 g13 V VCM Input Common-Mode g16 a18, b17 g11 a14, b12 VVoltage Range CMRR Common-Mode R S s 10 k X 80 100 70 95 dBRejection Ratio Obsolete
Symbol Parameter Conditions LF441A LF441 Units Min Typ Max Min Typ Max PSRR Supply Voltage (Note 7) 80 100 70 90 dBRejection Ratio IS Supply Current 150 200 150 250 mA Symbol Parameter Conditions LF441A LF441 Units Min Typ Max Min Typ Max SR Slew Rate VS e g15V, T A e 25§C 0.8 1 0.6 1 V/ms GBW Gain-Bandwidth Product V S e g15V, T A e 25§C 0.8 1 0.6 1 MHz en Equivalent Input Noise Voltage T A e 25§C, R S e 100X, 35 35 nV/0Hzf e 1 kHz in Equivalent Input Noise Current T A e 25§C, f e 1 kHz 0.01 0.01 pA/0Hz Note 1: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 2: For operating at elevated temperature, these devices must be derated based on a thermal resistance of ijA. Note 3: The temperature range is designated by the position just before the package type in the device number. A ‘‘C’’ indicates the commercial temperature range and an ‘‘M’’ indicates the military temperature range. The military temperature range is available in ‘‘H’’ package only. Note 4: Unless otherwise specified the specifications apply over the full temperature range and for V S e g20V for the LF441A and for V S e g15V for the LF441. VOS,I B, and I OS are measured at V CM e 0. Note 5: The LF441A is 100% tested to this specification. Note 6: The input bias currents are junction leakage currents which approximately double for every 10 §C increase in the junction temperature, T j. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, P D.T j e TA a ijA PD where ijA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. From g15V to g5V for the LF441 and from g20V to g5V for the LF441A. Note 8: Refer to RETS441X for LF441MH military specifications. Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. Note 10: Human body model, 1.5 k X in series with 100 pF. Typical Performance Characteristics Input Bias Current Input Bias Current Supply Current Input Voltage Limit Positive Common-Mode Input Voltage Limit Negative Common-Mode Positive Current Limit TL/H/9297–5 Obsolete
Typical Performance Characteristics (Continued) Negative Current Limit Output Voltage Swing Output Voltage Swing Gain Bandwidth Bode Plot Slew Rate Distortion vs Frequency Voltage Swing Undistorted Output Open Loop Frequency Response Common-Mode Rejection Ratio Power Supply Rejection Ratio Equivalent Input Noise Voltage TL/H/9297–6 Obsolete
Typical Performance Characteristics (Continued) Open Loop Voltage Gain Output Impedance Inverter Settling Time TL/H/9297–7 Simplified Schematic TL/H/9297–3 Pulse Response RL e 10 k X,C L e 10 pF Small Signal Inverting TL/H/9297–8 Obsolete
Pulse Response RL e 10 k X,C L e 10 pF (Continued) Small Signal Non-Inverting TL/H/9297–9 Large Signal Inverting TL/H/9297–10 Large Signal Non-Inverting TL/H/9297–11 Obsolete
This device is a low power op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain, eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, nei- ther of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifier will operate with a common-mode input volt- age equal to the positive supply; however, the gain band- width and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. The amplifier is biased to allow normal circuit operation with power supplies of g3V. Supply voltages less than these may degrade the common-mode rejection and restrict the output voltage swing. The amplifier will drive a 10 k X load resistance to g10V over the full temperature range. Precautions should be taken to ensure that the power sup- ply for the integrated circuit never becomes reversed in po- larity or that the unit is not inadvertently installed backwards in a socket, as an unlimited current surge through the result- ing forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in or- der to ensure stability. For example, resistors from the out- put to an input should be placed with the body close to the input to minimize ‘‘pick-up’’ and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capaci- tance from the input of the device (usually the inverting input to AC ground) set the frequency of this pole. In many in- stances the frequency of this pole is much greater than the expected 3 dB frequency, of the closed loop gain and con- sequently there is negligible effect on stability margin. How- ever, if the feedback pole is less than approximately 6 times the expected 3 dB frequency, a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time con- stant. Detailed Schematic TL/H/9297–13 Obsolete
Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number LF441MH/883 Dual-In-Line Package(M) Order Number LF441CM Obsolete
LF441 Low Power JFET Input Operational Amplifier Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number LF441ACN or LF441CN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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