LF412QML TI | Alldatasheet
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www.ti.com SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 LF412QMLLowOffset,LowDriftDualJFETInputOperationalAmplifier Check forSamples: LF412QML 1FEATURES DESCRIPTION This deviceis a low cost,high speed, JFET input 23• InputOffsetVoltageDrift:20 μV/°C (Max) operationalamplifierwithverylow inputoffsetvoltage• Low InputBias Current:50 pA (Typ) and ensuredinputoffsetvoltagedrift.Itrequireslow
- Low InputNoise Current:0.01pA/√Hz (Typ) supplycurrentyetmaintainsa largegainbandwidth productand fastslew rate.Inaddition,wellmatched• Wide Gain Bandwidth: 2.7MHz (Min) high voltageJFET inputdevicesprovidevery low• High Slew Rate:8V/μs (Min) inputbiasand offsetcurrents.The LF412 dualispin
- High InputImpedance: 1012Ω compatiblewiththe LM1558, allowingdesignersto immediatelyupgrade the overallperformance of• Low TotalHarmonic Distortion<0.02% existingdesigns.• Low 1/fNoise Corner:50 Hz This amplifiermay be used in applicationssuch as• FastSettlingTime to0.01%:2 μs high speed integrators,fastD/A converters,sample and holdcircuitsand many othercircuitsrequiringlow inputoffsetvoltageand drift,low inputbiascurrent, high input impedance, high slew rate and wide bandwidth. Connection Diagram Figure1. TO-99 Package Figure2.CDIP Package Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2BI-FETIIisa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 www.ti.com SimplifiedSchematic Figure3. 1/2Dual DetailedSchematic These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.
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www.ti.com SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 AbsoluteMaximum Ratings(1) SupplyVoltage ±18V DifferentialInputVoltage ±30V InputvoltageRange (2) ±15V OutputShortCircuitDuration(3) Continuous Power Dissipation(4) TJmax 150°C θJA ThermalResistance θJC SupplyvoltageRange ±5V to±15V OperatingTemperatureRange −55°C ≤ TA ≤ 125°C StorageTemperatureRange −65°C ≤ TA ≤ 150°C Lead TemperatureSoldering(10Sec) 260°C ESD Tolerance(5) 1,700V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Unlessotherwisespecifiedtheabsolutemaximum negativeinputvoltageisequaltothenegativepower supplyvoltage. (3) Any oftheamplifieroutputscan be shortedtogroundindefinitely,however,more thanone shouldnotbe simultaneouslyshortedas the maximum junctiontemperaturewillbe exceeded. (4) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby TJmax (maximum junctiontemperature), θJA (packagejunctiontoambientthermalresistance),and TA (ambienttemperature).The maximum allowablepower dissipationatany temperatureisPDmax = (TJmax -TA)/θJA orthenumber givenintheAbsoluteMaximum Ratings,whicheverislower. (5) Human body model,1.5kΩ inserieswith100 pF. QualityConformance Inspection Table1.Mil-Std-883,Method 5005 -Group A Subgroup Description Temp (°C)
1 Statictestsat +25
2 Statictestsat +125
3 Statictestsat -55
4 Dynamic testsat +25
5 Dynamic testsat +125
6 Dynamic testsat -55
7 Functionaltestsat +25
9 Switchingtestsat +25
10 Switchingtestsat +125
11 Switchingtestsat -55
12 Settlingtimeat +25
13 Settlingtimeat +125
14 Settlingtimeat -55
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SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 www.ti.com ElectricalCharacteristicsDC parameters The followingconditionsapply,unlessotherwisespecified.VCC = ±15V,VCM = 0V,R S = 0Ω Sub-Symbol Parameter Conditions Notes Min Max Unit group -3.0 3.0 mV 1 VIO InputoffsetVoltage R S = 10KΩ -5.0 5.0 mV 2,3 R S = 10KΩ, See (1) -20 20 µV/°C 225°C ≤ TA ≤ 125°CTemperatureCoefficientofInputΔVIO /ΔT OffsetVoltage R S = 10KΩ, See (1) -20 20 µV/°C 3-55°C ≤ TA ≤ 25°C -0.1 0.1 nA 1 IIO InputOffsetCurrent See (2) -25 25 nA 2 0.2 nA 1 ±IIB InputBiasCurrent See (2) 50 nA 2 CMRR Common Mode RejectionRatio R S ≤ 10KΩ,VCM = ±11V 70 dB 1,2,3 6V ≤ +VCC ≤ 15V,+PSRR SupplyVoltageRejectionRatio 70 dB 1,2,3-VCC = -15V +VCC = 15V,-PSRR SupplyVoltageRejectionRatio 70 dB 1,2,3-15V ≤ -VCC ≤ -6V IS SupplyCurrent 6.5 mA 1,2,3 13 45 mA 1 -IOS OutputShortCircuitCurrent 6.0 45 mA 2,3 -45 -13 mA 1 +IOS OutputShortCircuitCurrent -45 -6.0 mA 2,3 VO = 0 to10V, 25 V/mV 4 +AVS LargeSignalVoltageGain See (3) R L = 2KΩ 15 V/mV 5,6 VO = 0 to-10V, 25 V/mV 4 -AVS LargeSignalVoltageGain See (3) R L = 2KΩ 15 V/mV 5,6 R L = 10KΩ,+VI= 11V,+VO OutputVoltageSwing 12 V 4,5,6-VI= -11V R L = 10KΩ,+VI= -11V,-VO OutputVoltageSwing -12 V 4,5,6-VI= 11V InputCommon Mode VoltageVCM See (4) −11 11 V 1,2,3Range (1) Specifiedparameter,nottested. (3) DatalogreadinginK = V/mV. (4) Specifiedby CMRR.
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www.ti.com SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 ElectricalCharacteristicsAC Parameters The followingconditionsapply,unlessotherwisespecified.VCC = ±15V,VCM = 0V,R S = 0Ω Sub-Symbol Parameter Conditions Notes Min Max Unit group SR+ Slew Rate VO = -5V to5V 8.0 V/µs 7 SR- Slew Rate VO = 5V to-5V 8.0 V/µs 7 GBW Gain BandwidthProduct 2.7 MHz 7 TypicalConnection Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LF412QML
SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics InputBias Current InputBias Current Figure4. Figure5. PositiveCommon-Mode Supply Current InputVoltageLimit Figure6. Figure7. NegativeCommon-Mode InputVoltageLimit PositiveCurrentLimit Figure8. Figure9.
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www.ti.com SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) NegativeCurrentLimit Output VoltageSwing Figure10. Figure11. Output VoltageSwing Gain Bandwidth Figure12. Figure13. Bode Plot Slew Rate Figure14. Figure. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LF412QML
SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) UndistortedOutput Voltage Distortionvs Frequency Swing Figure15. Figure16. Open Loop Frequency Common-Mode Rejection Response Ratio Figure17. Figure18. Power Supply Rejection EquivalentInputNoise Ratio Voltage Figure19. Figure20.
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www.ti.com SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) Open Loop VoltageGain Output Impedance Figure21. Figure22. InverterSettlingTime Figure23. Pulse Response R L=2 kΩ,C L=10 pF Figure24.Small SignalInverting Figure25.Small SignalNon-Inverting Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LF412QML
SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 www.ti.com Pulse Response (continued) R L=2 kΩ,C L=10 pF Figure26.Large SignalInverting Figure27.Large SignalNon-Inverting Figure28.CurrentLimit(RL=100Ω)
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www.ti.com SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 APPLICATION HINTS The LF412 JFET inputdualop amp isinternallytrimmed(BI-FET II™ ) providingverylow inputoffsetvoltages and ensuredinputoffsetvoltagedrift.These JFETs have largereversebreakdown voltagesfromgatetosource and draineliminatingtheneed forclamps acrosstheinputs.Therefore,largedifferentialinputvoltagescan easily be accommodated withouta largeincreasein inputcurrent.The maximum differentialinputvoltageis independentof the supplyvoltages.However, neitherof the inputvoltagesshouldbe allowedto exceed the negativesupplyas thiswillcause largecurrentstoflowwhichcan resultina destroyedunit. Exceedingthenegativecommon-mode limiton eitherinputwillcause a reversalofthephase totheoutputand forcetheamplifieroutputtothecorrespondinghighorlowstate. Exceeding the negativecommon-mode limiton both inputswillforcethe amplifieroutputto a high state.In neithercase does a latchoccursinceraisingtheinputback withinthecommon-mode rangeagainputstheinput stageand thustheamplifierina normaloperatingmode. Exceedingthepositivecommon-mode limiton a singleinputwillnotchange thephase oftheoutput,however,if bothinputsexceed thelimit,theoutputoftheamplifiermay be forcedtoa highstate. The amplifierswilloperatewitha common-mode inputvoltageequaltothepositivesupply;however,thegain bandwidthand slewratemay be decreasedinthiscondition.When thenegativecommon-mode voltageswings towithin3V ofthenegativesupply,an increaseininputoffsetvoltagemay occur. Each amplifierisindividuallybiasedby a zenerreferencewhichallowsnormalcircuitoperationon ±6.0V power supplies.Supplyvoltageslessthanthesemay resultinlowergainbandwidthand slewrate. The amplifierswilldrivea 2 kΩ loadresistanceto±10V overthefulltemperaturerange.Iftheamplifierisforced todriveheavierloadcurrents,however,an increaseininputoffsetvoltagemay occuron thenegativevoltage swingand finallyreachan activecurrentlimiton bothpositiveand negativeswings. Precautionsshouldbe takentoensurethatthepower supplyfortheintegratedcircuitneverbecomes reversedin polarityorthattheunitisnotinadvertentlyinstalledbackwardsina socketas an unlimitedcurrentsurgethrough theresultingforwarddiodewithintheIC couldcause fusingoftheinternalconductorsand resultina destroyed unit. As withmost amplifiers,careshouldbe takenwithleaddress,component placementand supplydecouplingin ordertoensurestability.For example,resistorsfromtheoutputtoan inputshouldbe placedwiththebody close to the inputto minimize“pick-up” and maximize the frequencyof the feedback pole by minimizingthe capacitancefromtheinputtoground. A feedbackpoleiscreatedwhen the feedbackaround any amplifierisresistive.The parallelresistanceand capacitancefromtheinputofthedevice(usuallytheinvertinginput)toAC groundsetthefrequencyofthepole. Inmany instancesthefrequencyofthispoleismuch greaterthantheexpected3 dB frequencyoftheclosed loopgainand consequentlythereisnegligibleeffecton stabilitymargin.However, ifthefeedbackpoleisless thanapproximately6 timestheexpected3 dB frequencya leadcapacitorshouldbe placedfromtheoutputtothe inputoftheop amp. The valueoftheadded capacitorshouldbe such thattheRC timeconstantofthiscapacitor and theresistanceitparallelsisgreaterthanorequaltotheoriginalfeedbackpoletimeconstant. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LF412QML
SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 www.ti.com TypicalApplication Figure29. SingleSupply Sample and Hold
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www.ti.com SNOSAO7A –DECEMBER 2010–REVISED MARCH 2013 Table2.RevisionHistory Date Released Revision Section Changes 12/08/2010 A New ReleasetoCorporateformat 1 MDS datasheetconvertedintoCorporatedatasheet format.MNLF412-X Rev 0C1 willbe archived. 03/26/2013 A AllSections Changed layoutofNationalData SheettoTIformat Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LF412QML
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LF412 MD8 Active Production DIESALE (Y) | 0 154 | JEDEC TRAY (5+1) Yes Call TI Level-1-NA-UNLIM -55 to 125 LF412MH/883 Active Production TO-99 (LMC) | 8 20 | JEDEC TRAY (5+1) Yes Call TI Level-1-NA-UNLIM -55 to 125 LF412MH/883 Q ACO LF412MH/883 Q >T LF412MJ/883 Active Production CDIP (NAB) | 8 40 | TUBE No SNPB Level-1-NA-UNLIM -55 to 125 LF412MJ /883 Q ACO /883 Q >T (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LF412MJ/883 NAB CDIP 8 40 506.98 15.24 13440 NA Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) Pack Materials-Page 2
www.ti.com J08A (Rev M)
www.ti.com PACKAGE OUTLINE C .305-.335 [7.75-8.51] .165-.185 [4.19-4.70] .010-.040 [0.25-1.02] SEATING PLANE .040 MAX [1.02] .335-.370 [8.51-9.40] .110-.160 [2.79-4.06] .028-.034 [0.71-0.86] .500 MIN [12.7] .225 [5.72] 8X .016-.021 [0.41-0.53] .200 [5.08] .100 [2.54] UNCONTROLLED LEAD DIA .055[1.397] MAX .029-.045 [0.74-1.14]
45 TYP
TO-CAN - 5.72 mm max heightLMC0008A TRANSISTOR OUTLINE 4220610/B 09/2024 NOTES: 1. All linear dimensions are in inches [millimeters]. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pin numbers shown for reference only. Numbers may not be marked on package. 4. Reference JEDEC registration MO-002/TO-99. MAX .010 [0.25] C A A
www.ti.com EXAMPLE BOARD LAYOUT (45 ) TYP .003 MAX [0.07] ALL AROUND 7X .003 MAX [0.07] ALL AROUND ( .200 ) [5.08] ( .055) [1.4] 7X ( .055) [1.4] METAL 8X ( .031) VIA [0.8] (R.002 ) TYP [0.05] TO-CAN - 5.72 mm max heightLMC0008A TRANSISTOR OUTLINE 4220610/B 09/2024 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 12X 7X SOLDER MASK OPENING SOLDER MASK OPENING METAL
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