LF412QML TI1 | Alldatasheet
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LF412QML Low Offset, Low Drift Dual JFET Input Operational Amplifier Literature Number: SNOSAO7
December 8, 2010 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description This device is a low cost, high speed, JFET input operational amplifier with very low input offset voltage and guaranteed input offset voltage drift. It requires low supply current yet maintains a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF412 dual is pin compatible with the LM1558, allowing designers to immediately upgrade the overall performance of existing de- signs. This amplifier may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage and drift, low input bias current, high input impedance, high slew rate and wide bandwidth.
Features
■ Input offset voltage drift: 20 μV/°C (max) ■ Low input bias current: 50 pA (Typ) ■ Low input noise current: (Typ) ■ Wide gain bandwidth: 2.7 MHz (min) ■ High slew rate: 8V/ μs (min) ■ High input impedance: 10 12Ω ■ Low total harmonic distortion <0.02% ■ Low 1/f noise corner: 50 Hz ■ Fast settling time to 0.01%: 2 μs
Ordering Information
NS Part Number Part Number NS Package Number Package Description LF412MH/883 H08A 8LD Metal Can LF412MJ/883 J08A 8LD CERDIP LF412 MD8 (Note 1) Bare Die Note 1: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die Connection Diagrams Metal Can Package 20149342 See NS Package Number H08A Dual-In-Line Package 20149344 See NS Package Number J08A BI-FET II™ is a trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 201493 www.national.com LF412QML Low Offset, Low Drift Dual JFET Input Operational Amplifier
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Absolute Maximum Ratings (Note 2) Supply Voltage ±18V Differential Input Voltage ±30V Input voltage Range(Note 4) ±15V Output Short Circuit Duration (Note 5) Continuous Power Dissipation(Note 3) Metal Can Package 800mW TJmax 150°C Thermal Resistance θJA Metal Can Package (Still Air) 160°C/W Metal Can Package (500 LF/Min Air Flow) 83°C/W θJC Metal Can Package 38°C/W Supply voltage Range ±5V to ±15V Operating Temperature Range −55°C ≤ TA ≤ 125°C Storage Temperature Range −65°C ≤ TA ≤ 150°C Lead Temperature Soldering (10 Sec) 260°C ESD Tolerance(Note 6) 1,700V Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp (°C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125 8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
12 Settling time at +25
13 Settling time at +125
14 Settling time at -55
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Electrical Characteristics
The following conditions apply, unless otherwise specified. V CC = ±15V, VCM = 0V, RS = 0Ω Symbol Parameter Conditions Notes Min Max Unit Sub- group VIO Input offset Voltage RS = 10KΩ -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 ΔVIO / ΔT Temperature Coefficient of Input Offset Voltage RS = 10KΩ, 25°C ≤ TA ≤ 125°C (Note 8) -20 20 µV/°C 2 RS = 10KΩ, -55°C ≤ TA ≤ 25°C (Note 8) -20 20 µV/°C 3 IIO Input Offset Current (Note 10) -0.1 0.1 nA 1 -25 25 nA 2 ±IIB Input Bias Current (Note 10) 0.2 nA 1 50 nA 2 CMRR Common Mode Rejection Ratio RS ≤ 10KΩ, VCM = ±11V 70 dB 1, 2, 3 +PSRR Supply Voltage Rejection Ratio 6V ≤ +VCC ≤ 15V, -VCC = -15V 70 dB 1, 2, 3 -PSRR Supply Voltage Rejection Ratio +VCC = 15V, -15V ≤ -VCC ≤ -6V 70 dB 1, 2, 3 IS Supply Current 6.5 mA 1, 2, 3 -IOS Output Short Circuit Current 13 45 mA 1 6.0 45 mA 2, 3 +IOS Output Short Circuit Current -45 -13 mA 1 -45 -6.0 mA 2, 3 +AVS Large Signal Voltage Gain VO = 0 to 10V, RL = 2KΩ (Note 9)
25 V/mV 4
15 V/mV 5, 6
-AVS Large Signal Voltage Gain VO = 0 to -10V, RL = 2KΩ (Note 9) +VO Output Voltage Swing RL = 10KΩ, +VI = 11V, -VI = -11V
12 V 4, 5, 6
-VO Output Voltage Swing RL = 10KΩ, +VI = -11V, -VI = 11V -12 V 4, 5, 6 VCM Input Common Mode Voltage Range (Note 7) −11 11 V 1, 2, 3 AC Parameters The following conditions apply, unless otherwise specified. V CC = ±15V, VCM = 0V, RS = 0Ω Symbol Parameter Conditions Notes Min Max Unit Sub- group SR+ Slew Rate VO = -5V to 5V 8.0 V/µs 7 SR- Slew Rate VO = 5V to -5V 8.0 V/µs 7 GBW Gain Bandwidth Product 2.7 MHz 7 www.national.com 4 LF412QML
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 4: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 5: Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. Note 6: Human body model, 1.5 kΩ in series with 100 pF. Note 7: Guaranteed by CMRR. Note 8: Guaranteed parameter, not tested. Note 9: Datalog reading in K = V/mV. Note 10: RS = 10KΩ @ +125°C Typical Connection 20149341 5 www.national.com LF412QML
Typical Performance Characteristics Input Bias Current 20149310 Input Bias Current 20149311 Supply Current 20149312 Positive Common-Mode Input Voltage Limit 20149313 Negative Common-Mode Input Voltage Limit 20149314 Positive Current Limit 20149315 www.national.com 6 LF412QML
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Undistorted Output Voltage Swing 20149323 Open Loop Frequency Response 20149324 Common-Mode Rejection Ratio 20149325 Power Supply Rejection Ratio 20149326 Equivalent Input Noise Voltage 20149327 www.national.com 8 LF412QML
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RL=2 kΩ, CL=10 pF Small Signal Inverting 20149336 Small Signal Non-Inverting 20149337 Large Signal Inverting 20149338 Large Signal Non-Inverting 20149339 Current Limit (RL=100Ω) 20149340 www.national.com 10 LF412QML
The LF412 JFET input dual op amp is internally trimmed (BI- FET II™) providing very low input offset voltages and guar- anteed input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum dif- ferential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output, however, if both inputs exceed the limit, the output of the amplifier may be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the neg- ative common-mode voltage swings to within 3V of the neg- ative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±6.0V power sup- plies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kΩ load resistance to ±10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to en- sure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feed- back pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Typical Application Single Supply Sample and Hold 20149331 11 www.national.com LF412QML
Revision History
Date Released Revision Section Changes 12/08/2010 A New Release to Corporate format 1 MDS datasheet converted into Corporate datasheet format. MNLF412-X Rev 0C1 will be archived. www.national.com 12 LF412QML
Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) 13 www.national.com LF412QML
Dual-In-Line Package (J) www.national.com 14 LF412QML
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