LF412-N TI | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community LF412-N SNOSBH7F –APRIL 1999–REVISED SEPTEMBER 2014 LF412-NLowOffset,LowDriftDualJFETInputOperationalAmplifier
1 Features 3 Description
These devices are low cost, high speed, JFET input 1• Internally Trimmed Offset Voltage: 1 mV (Max) operational amplifiers with very low input offset• Input Offset Voltage Drift: 7 µV/°C (Typ) voltage and input offset voltage drift. They require low
- Low Input Bias Current: 50 pA supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched• Low Input Noise Current: 0.01 pA / √Hz high voltage JFET input devices provide very low• Wide Gain Bandwidth: 3 MHz (Min) input bias and offset currents. The LF412-N dual is• High Slew Rate: 10V/µs (Min) pin compatible with the LM1558, allowing designers to immediately upgrade the overall performance of• Low Supply Current: 1.8 mA/Amplifier existing designs.• High Input Impedance: 1012Ω These amplifiers may be used in applications such as• Low Total Harmonic Distortion: ≤0.02% high speed integrators, fast D/A converters, sample• Low 1/f Noise Corner: 50 Hz and hold circuits and many other circuits requiring low• Fast Settling Time to 0.01%: 2 µs input offset voltage and drift, low input bias current, high input impedance, high slew rate and wide 2 Applications bandwidth.
- High Speed Integrators Device Information(1)
- Fast D/A Converters PART NUMBER PACKAGE BODY SIZE (NOM)
- Sample and Hold Circuits LF412ACN PDIP 9.59 mm x 6.35 mm LF412CN PDIP 9.59 mm x 6.35 mm LF412MH TO 9.14 mm diameter (1) For all available packages, see the orderable addendum at the end of the datasheet. Inverting Amplifier An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNOSBH7F –APRIL 1999–REVISED SEPTEMBER 2014 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2014) to Revision F Page Changes from Revision D (March 2013) to Revision E Page
5 Pin Configuration and Functions
See Package Number NEV0008A Top View
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Product Folder Links: LF412-N
www.ti.com SNOSBH7F –APRIL 1999–REVISED SEPTEMBER 2014 PDIP/CDIP Package See Package Number P0008E or NAB0008A Top View Pin Functions PIN I/O DESCRIPTION NAME NO. Output A 1 O Amplifier A Output Inverting 2 I Amplifier A Inverting InputInput A Non-Inverting 3 I Amplifier A Non-Inverting InputInput A V- 4 P Negative Supply Non-Inverting 5 I Amplifier B Non-Inverting InputInput B Inverting 6 I Amplifier B Inverting InputInput B Output B 7 O Amplifier B Output V+ 8 P Positive Supply Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LF412-N
SNOSBH7F –APRIL 1999–REVISED SEPTEMBER 2014 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2) LF412A LF412 UNIT MIN MAX MIN MAX Supply Voltage –22 22 –18 18 V Differential Input Voltage –38 38 –30 30 V Input voltage Range(3) Output Short Circuit Duration(4) Continuous Continuous Power Dissipation(5) See (6) 670 mW Tj max 150 115 °C Operating Temp. Range See (7) See (7) Lead Temp. (Soldering, 10 sec.) 260 260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Refer to RETS412X for LF412MH and LF412MJ military specifications. (3) Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. (4) Any of the amplifier outputs can be shorted to ground indefintely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. (5) Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. (6) For operating at elevated temperature, these devices must be derated based on a thermal resistance of θjA. (7) These devices are available in both the commercial temperature range 0°C≤TA≤70°C and the military temperature range −55°C≤TA≤125°C. The temperature range is designated by the position just before the package type in the device number. A “C” indicates the commercial temperature range and an “M”indicates the military temperature range. The military temperature range is available in TO package only. In all cases the maximum operating temperature is limited by internal junction temperature Tj max.
6.2 Handling Ratings
Tstg Storage temperature range −65 150 °C Human body model (HBM), -1700 1700(2) per ANSI/ESDA/JEDEC JS-001, all pins(1) V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) Human body model, 1.5 kΩ in series with 100 pF. (3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply Voltage LF412A ±20 V Supply Voltage LF412 ±15 V
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Product Folder Links: LF412-N
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6.4 Thermal Information
THERMAL METRIC(1) TO Package PDIP Package UNIT RθJA Junction-to-ambient thermal resistance (Typical) 152 115 RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance °C/W ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) LF412A(1) LF412(1) PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX VOS Input Offset Voltage RS=10 kΩ, TA=25°C 0.5 1.0 1.0 3.0 mV ΔVOS/Δ Average TC of Input RS=10 kΩ 7 7 μV/°CT Offset Voltage Tj=25°C 25 100 25 100 pA IOS Input Offset Current VS=±15V(1)(2) Tj=70°C 2 2 nA Tj=125°C 25 25 nA Tj=25°C 50 200 50 200 pA IB Input Bias Current VS=±15V(1)(2) Tj=70°C 4 4 nA Tj=125°C 50 50 nA RIN Input Resistance Tj=25°C 1012 1012 Ω RL=2k, TA=25°C, VS=±15V, 50 200 25 200Large Signal VO=±10VAVOL V/mVVoltage Gain Over Temperature 25 200 15 200 VO Output Voltage Swing VS=±15V, RL=10k ±12 ±13.5 ±12 ±13.5 V ±16 +19.5 ±11 +14.5 VInput Common-ModeVCM Voltage Range −16.5 −11.5 V Common-ModeCMRR RS≤10k 80 100 70 100 dBRejection Ratio Supply VoltagePSRR See(3) 80 100 70 100 dBRejection Ratio IS Supply Current VO = 0V, RL = ∞ 3.6 5.6 3.6 6.5 mA (1) Unless otherwise specified, the specifications apply over the full temperature range and for VS=±20V for the LF412A and for VS=±15V for the LF412. VOS, IB, and IOS are measured at VCM=0. (2) The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. (3) Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = ±6V to ±15V.
6.6 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) LF412A(1) LF412(1) PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Amplifier to TA=25°C, f=1 Hz-20 kHz −120 −120 dBAmplifier Coupling (Input Referred) (1) Unless otherwise specified, the specifications apply over the full temperature range and for VS=±20V for the LF412A and for VS=±15V for the LF412. VOS, IB, and IOS are measured at VCM=0. Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LF412-N
SNOSBH7F –APRIL 1999–REVISED SEPTEMBER 2014 www.ti.com over operating free-air temperature range (unless otherwise noted) LF412A(1) LF412(1) PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX SR Slew Rate VS=±15V, TA=25°C 10 15 8 15 V/μs GBW Gain-Bandwidth Product VS=±15V, TA=25°C 3 4 2.7 4 MHz AV=+10, RL=10k, THD Total Harmonic Dist VO=20 Vp-p, ≤0.02% ≤0.02% BW=20 Hz-20 kHz Equivalent Input TA=25°C, RS=100Ω, nV /en 25 25Noise Voltage f=1 kHz √Hz Equivalent Input pA /in TA=25°C, f=1 kHz 0.01 0.01Noise Current √Hz
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Product Folder Links: LF412-N
6.7 Typical Characteristics
Figure 2. Input Bias Current Figure 1. Input Bias Current Figure 4. Positive Common-Mode Figure 3. Supply Current Input Voltage Limit Figure 5. Negative Common-Mode Figure 6. Positive Current LimitInput Voltage Limit
Figure 7. Negative Current Limit Figure 8. Output Voltage Swing Figure 10. Gain BandwidthFigure 9. Output Voltage Swing Figure 11. Bode Plot Figure 12. Slew Rate
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Figure 19. Open Loop Voltage Gain Figure 20. Output Impedance Figure 22. Small Signal Inverting Figure 21. Inverter Settling Time (RL = 2 kΩ, CL = 10 pF) Figure 23. Small Signal Non-Inverting Figure 24. Large Signal Inverting
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Figure 26. Current Limit (RL=100Ω)Figure 25. Large Signal Non-Inverting
7 Detailed Description
7.1 Overview
overall performance of existing designs. impedance, high slew rate and wide bandwidth.
7.2 Functional Block Diagram
Figure 27. Each Amplifier
7.3 Feature Description
output voltage of the op-amp VOUT is given by the equation VOUT = AOL(IN+ - IN-).
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7.4 Device Functional Modes
7.4.1 Input and Output Stage
Figure 28. 1/2 Dual LF412
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
negative supply as this will cause large currents to flow which can result in a destroyed unit.
8.2 Typical Application
Figure 29. Single Supply Sample and Hold
8.2.1 Design Requirements
8.2.2 Detailed Design Procedure
force the amplifier output to the corresponding high or low state. stage and thus the amplifier in a normal operating mode. to within 3V of the negative supply, an increase in input offset voltage may occur. supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. swing and finally reach an active current limit on both positive and negative swings.
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capacitance from the input to ground. capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. and the resistance it parallels is greater than or equal to the original feedback pole time constant.
8.2.3 Application Curves
Figure 30. Sample and Hold Waveforms
9 Power Supply Recommendations
power supply voltage is ±5V.
10 Layout
10.1 Layout Guidelines
capacitance from the input to ground.
10.2 Layout Example
Figure 31. LF412 Layout
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www.ti.com SNOSBH7F –APRIL 1999–REVISED SEPTEMBER 2014
11 Device and Documentation Support
11.1 Trademarks
BI-FET II is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LF412-N
www.ti.com 14-Jul-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LF412ACN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412ACN LF412ACN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412ACN LF412ACN/NOPBG4 Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412ACN LF412ACN/NOPBG4.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412ACN LF412CN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412CN LF412CN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412CN LF412CN/NOPBG4 Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412CN LF412CN/NOPBG4.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 412CN (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1
www.ti.com 14-Jul-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LF412ACN/NOPB P PDIP 8 40 502 14 11938 4.32 LF412ACN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LF412ACN/NOPBG4 P PDIP 8 40 502 14 11938 4.32 LF412ACN/NOPBG4.B P PDIP 8 40 502 14 11938 4.32 LF412CN/NOPB P PDIP 8 40 502 14 11938 4.32 LF412CN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LF412CN/NOPBG4 P PDIP 8 40 502 14 11938 4.32 LF412CN/NOPBG4.B P PDIP 8 40 502 14 11938 4.32 Pack Materials-Page 1
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