LF411 TI | Alldatasheet
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JFET-INPUT OPERATIONAL AMPLIFIER SLOS011C – MARCH 1987 – REVISED OCTOBER 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Input Bias Current, 50 pA Typ /C0068Low Input Noise Current, 0.01 pA/√Hz Typ /C0068Low Supply Current, 2 mA Typ /C0068High Input impedance, 1012 Ω Typ /C0068Low Total Harmonic Distortion /C0068Low 1/f Noise Corner, 50 Hz Typ /C0068Package Options Include Plastic Small-Outline (D) and Standard (P) DIPs
description
This device is a low-cost, high-speed, JFET-input operational amplifier with very low input offset voltage and a maximum input offset voltage drift. It requires low supply current, yet maintains a large gain-bandwidth product and a fast slew rate. In addition, the matched high-voltage JFET input provides very low input bias and offset currents. The LF411 can be used in applications such as high-speed integrators, digital-to-analog converters, sample-and-hold circuits, and many other circuits. The LF411C is characterized for operation from 0°C to 70°C. The LF411I is characterized for operation from –40°C to 85°C. symbol IN – IN + OUT BAL1 BAL2 AVAILABLE OPTIONS VIOmax PACKAGE TA VIOmax AT 25°C SMALL OUTLINE (D) PLASTIC DIP (P) 0°C to 70°C 2 mV LF411CD LF411CP –40°C to 85°C 2 mV LF411ID LF411IP The D packages are available taped and reeled. Add the suffix R to the device type (i.e., LF411CDR). Copyright 1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. BAL1 IN– IN+ VCC– NC V CC+ OUT BAL2 D OR P PACKAGE (TOP VIEW) NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
JFET-INPUT OPERATIONAL AMPLIFIER SLOS011C – MARCH 1987 – REVISED OCTOBER 1997
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) NOTES: 1. Unless otherwise specified, the absolute maximum negative input voltage is equal to the negative power supply voltage. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions C SUFFIX I SUFFIX UNITMIN MAX MIN MAX UNIT Supply voltage, VCC + 3.5 18 3.5 18 V Supply voltage, VCC – –3.5 –18 –3.5 –18 V Operating free-air temperature, TA 0 70 –40 –85 °C electrical characteristics over operating free-air temperature range, VCC ± = ±15 V (unless otherwise specified) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNITPARAMETER TEST CONDITIONS LF411C LF411I MIN TYP MAX UNIT VIO Input offset voltage VIC = 0, R S = 10 kΩ 25°C 25°C 0.8 2 mV α VIO Average temperature coeffi- cient of input offset voltageVIC = 0, R S = 10 kΩ 10 20† µV/°C IIO Inp t offset c rrent‡ VIC =0 25°C 25°C 25 100 pA IIO Input offset current‡ VIC = 0 70°C 85°C 2 nA IIB Inp t bias c rrent‡ VIC =0 25°C 25°C 50 200 pA IIB Input bias current‡ VIC = 0 70°C 85°C 4 nA VICR Common-mode input voltage range ± 11 –11.5 to 14.5 V VOM Maximum peak output-voltage swing R L = 10 kΩ ± 12 ± 13.5 V AVD Large-signal differential VO = ± 10 V R L =2k Ω 25°C 25°C 25 200 V/mVAVD gg voltage VO = ± 10 V, R L = 2 kΩ 0°C to 70°C –40°C to 85°C 15 200 V/mV ri Input resistance TJ = 25°C 1012 Ω CMR R Common-mode rejection ratioR S ≤ 10 kΩ 70 100 dB kSVR Supply-voltage rejection ratioSee Note 3 70 100 dB ICC Supply current 2 3.4 mA † At least 90% of the devices meet this limit for α VIO. ‡ Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive. Pulse techniques must be used that will maintain the junction temperatures as close to the ambient temperature as possible. NOTE 3: Supply-voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously.
JFET-INPUT OPERATIONAL AMPLIFIER SLOS011C – MARCH 1987 – REVISED OCTOBER 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics, VCC ± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate 8 13 V/µs B1 Unity-gain bandwidth 2.7 3 MHz Vn Equivalent input noise voltage f = 1 kHz, R S = 20 Ω 18 nV/√Hz In Equivalent input noise current f = 1 kHz 0.01 pA/√Hz
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LF411CD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 LF411C LF411CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LF411C LF411CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LF411C LF411CDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI 0 to 70 LF411CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LF411CP LF411CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LF411CP LF411CPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 23-May-2025 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LF411CDR SOIC D 8 2500 356.0 356.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LF411CP P PDIP 8 50 506 13.97 11230 4.32 LF411CP.A P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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