LF398AN8

LF198A LINER | Alldatasheet

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TECHNOLOGY Precision Sample and Hold Amplifier FEATURES DESCRIPTION ® Guaranteed 6us Max. Acquisition Time The LF198 is a precision sample and hold amplifier which ® Guaranteed 0.005% Max. Gain Error uses a combination of bipolar and junction FET transis- = Guaranteed 1mV Max. Offset Voltage tors to provide precision, high speed, and long hold = Guaranteed 1mV Max. Hold Step times. A typical offset voltage of 1mV and gain error of m Very Low Feedthrough 86dB Min. 0.002% allow this sample and hold amplifier to be used in = High Input Impedance under All Conditions 12-bit systems. Dynamic performance can be optimized = Logic Inputs Compatible with All Logic Families by proper selection of the external hold capacitor. Acqui- sition times can be as low as 4ys for small capacitors while hold step and droop errors can be held below APPLICATIONS 0.1mV and 30,V/sec respectively when using larger capacitors. = 12-Bit Data Acquisition Systems a , . = Ramp Generators The LF198 is fixed at unity gain with 101°C input im- ® Analog Switches pedance independent of sample /hold mode. The logic in- = Staircase Generators puts are high impedance differential to allow easy inter- = Sample and Difference Circuits facing to any logic family without ground loop problems. A separate offset adjust pin can be used to zero the offset voltage in either the sample or hold mode. Additionally, the hold capacitor can be driven with an external signal to provide precision level shifting or ‘‘differencing’’ opera- tion. The device will operate over a wide supply voltage range from +: 5V to + 18V with very little change in per- formance, and key parameters are specified over this full supply range. The LF198A version offers tightened electrical specifica- tions for key parameters. 9 | TS Basic Sample and Hold Acquisition Time ‘ee ve i Cont ty. Sees sat 3 q gs NH a 2 Se Ne 0 === ae wv— Nt Se eee as aes ee eee

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ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION Logic to Logic Reference Differential vv ORDER Power Dissipation (Package Limitation) input %3) CS) output LF398AH v Operating Temperature Range a paocace orrecr PE ione LF398J8 WNPUT Ch i [5] oureut LF398N8 ‘JB PACKAGE HERMETIC DIP NB PACKAGE PLASTIC DUAL IN LINE ee ELECTRICAL CHARACTERISTICS (note 3) wanoes [TT irs mv Feedthrough Attenuation Rati C,=0.01 86 96 86 96 dB a de A a “WOU ep Waa | Gye Vaed [| Supply Current (Note 6) [mec Sma isition Time to 0.1% Vout =10V, Ch=1 F 6 Hold Capacitor Charging Current | Viy=Vour=2V 0 [fa Supply Voltage Rejection Ratio | Vour=0 | OO Differential Logic Threstold [| eae 9.98 owen

ELECTRICAL CHARACTERISTICS (note 3) LF198 LF398 Input Offset Voltage (Note 6) 1 3 2 7 mv 5 10 mV Input Bias Current (Note 6) 5 25 10 50 nA 75 100 nA 0.02 0,02 % Feedthrough Attenuation Ratio Cy =0.01 pF 86 96 80 96 dB at 1kHz a “HOD” Sep ows) | Gh=OORVarmd [| oe) Supp Curent Woes) [Tease |S TCS | mA Logic and Logic Reference Inout vA Current Leakage Current into Hold “HOLD'’ Mode (Note 5) pA Capacitor (Note 6) Acquisition Time to 0.1% AVoyt = 10V, Cy = 1000pF 4 4 us Cy=0.01 pF 16 16 us Holt Capac Charging Curent_| V—Vour=®V ‘|| ss SS Supply Votage Rejection Rao | Vour=0 =| Od Difeental ogo Twesiad [|Site Cf OSA | The @ denotes the specifications which apply over the full operating Note 4: The hold step is sensitive to stray capacitance coupling between in- temperature range. put logic signals and the hold capacitor. 1pF, for instance, will create an ad- Note 1: 7) max for the LF198/LF19BA is 150°C; Tj max for the ditional 0.5mV step with a SV logic swing and a 0.01yF hold capacitor. LF398/LF398A is 100°C. Magnitude of the hold step is inversely proportional to hold capacitor value. Note 2: The logic inputs are protected to + 30V differential as long as the Note 5: Leakage current is measured at a junction temperature of 25°C. voltage on both pins does not exceed the supply voltage. For proper opera- The effects of junction temperature rise due to power dissipation or elevated tion, however, both logic and logic reference pins must be atleast 2V below ambient can be calculated by doubling the 25°C value for each 11°C in- the positive supply and one of these pins must be at least 3V above the crease in chip temperature. Leakage is guaranteed over full input signal negative supply. range. Note 3: Uniess otherwise noted, Vs = + 15V, Tj=25°C, —11.5VsVys ‘Note 6: These parameters are guaranteed over a supply voltage range of 19 | +11.5V, Cy =0.01pF, Ry =10k@and unitis in “‘sample” mode. Logicref- SV to + 18V. erence =OV and logic voltage =2.5V. a FUNCTIONAL DIAGRAM === _-— ee rc = 7 { | WF SI weur—2 / | ! / ! toate al / 1500 15 sa WA CAPACITOR tosic_7! I ‘REFERENCE 1 Lo LLL a

TYPICAL PERFORMANCE CHARACTERISTICS Aperture Time* Dynamic Sampling Error* “Hold’’ Settling Time* 500 100 S55 mes 751: EEE SET: 2 . Sastst a Cir Scrat Tan sii sseiiiiimmnni il xo CT cry a ‘ HEAR ae ee 8 Aer ett SCC 2 mn ere | SRM TB eer "A Re SE 9 3 aunenion TEMPERATURE (ob) ms 180 “ INPUT SLEW ARTE quinsety ‘0 a crn TEMPERATURE (°C) vs tse “See Definition of Terms “See Definition of Terms *See Definition of Terms Hold Step Hold Step vs Input Voltage Hold Step vs Logic Slew Rate aes ee ere

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TYPICAL PERFORMANCE CHARACTERISTICS Output Short Circuit Current Output Noise Gain Error NS SS oo vHeNee 4 St Hen Kt ttt ee Se 0 E ttt eS 2 UM TIT) 6& “] 7 Pe] EEE SSS GNU pve oa a | 0 i Bae Sanne (OEE CLUE TM TIT TMM, JUNCTION TEMPERATURE (°C) FREQUENCY (Hz) OUTPUT VOLTAGE (V) Output, Small Sire " Feedthrough Rejection Ratio Power Supply Rejection a: es) ea a-s as eee ill ay Oe La ye 2 mu A of 2 qa TMNT & ve RST Th | CIEE: | EERE) ESR : Ly wo 2 5 w i ! ti 0 TaN i He AIP 2° CCCs Hr ° est a fe 2 @ TT) LTT Lid eA Avene (ITH SS CUTIE TIO TT EITM ULTRA FREQUENCY (Hz) m ana FREIWENGY 82) “om ™ " REQUENGY (2) “ " 9 | Capacitor Dielectric Absorption Capacitor Dielectric Absorption ™ eee = ol "ST [eee ESErHiHnS Sey peer teouicnd SS LI Witee 9-101

TYPICAL PERFORMANCE CHARACTERISTICS Output Transient at Start of Hold Output Transient at Start of Mode Sample Period ALL VALUES OF C; wPPTE TT hla "CAN CCE pe 5 \\E VW SEUNG 0.83 3. | V2 NEGATIVE NPUT SLE (CR SAMPLE = -5v s, i= 04 ) Cy = 1000p F : {1/1 B26 [jf 2 : 12 Pitt ttt Wes PEE TEE TY | “rea 0 02 04 06 08 10 12 14 16 “0 1 2 3 4 5 TIME (us) TIME (ys) APPLICATIONS INFORMATION Hold Capacitor | For fast sample and hold applications, the size of the hold Tolal Hold Capacitor ran aan ge ‘quivalent Circuit capacitor is critical. A low value will give fast acquisition, but will also increase errors due to hold step, and droop caused by amplifier bias current. The capacitor should be made as large as possible, consistent with acquisition 4 3" Ay time and dynamic sampling error requirements. Capaci- c, ey tors larger than 0.14F have an additional problem. They are generally not available in the low loss dielectrics like Teflon, Polystyrene, and NPO, at least not ata reasonable Ma a cen re viMt CONSTANTS price and size. Mylar, even with its poor dielectric OF 0.1-50 MILLISECONDS WITH C, Cy, absorption properties, may be a reasonable choice where very long sample times are used and low droop rates are —_' One can see that rapid changes in capacitor voltage will needed. not be tracked by the internal parasitic capacitors because of the resistance in series with them. This leads Dielectric absorption in the hold capacitor can often be the to a ‘‘sag’’ effect in the hold capacitor after a sudden major source of error ina sample and hold. The equivalent change in voltage followed by rapid switch to the hold “circuit’’ of a typical capacitor is shown below with mode. The capacitor remembers its previous state via the parallel RC networks used to model dielectric absorption. charge on the internal parasitic capacitance and sags SS UU EIR REE 9-102 A Were

back slightly toward the previous voltage. The magnitude © The switch opening delay is obvious and leads to a ‘‘held’’ of the sag depends on the voltage change and the time —_ output error of (dv/dt) x (Tu), where dv/dtis the slew rate spent sampling the new voltage. Several time constants of the input signal and Tg is switch delay. In the case of the are typically evident in the sag, although some capacitors LF198, Tq is approximately 150ns, giving a 4.5mV error tend to exhibit a single time constant, while others showa when sampling the zero crossing of a 5V (peak) sine wave sag that indicates a blending of many time constants. The at 1kHz (dv/dt =A*2arf =5*22r°10%). The analog delay is curves labeled CAPACITOR DIELECTRIC ABSORPTION __ the difference between input signal and capacitor voltage. It show the amount of sag found after a 10V step with sam- is determined by the RC product of the hold capacitor and ple time at the new voltage and hold time at the new _the effective series resistance, which in the case of the voltage as variables. It is obvious that sag problems are / LF198 is about 1500. This analog delay with a 0.01 uF hold minimized by long sample times and short hold times. capacitor is ReC = 150 x 10-8 =1.5ys, or about ten times This is often in conflict with basic sampling requirements, the delay of the switch. The sign of the analog delay is but one point should be made: if at all possible, keep the negative—the held output is related in time to the input sample and hold amplifier in the ‘‘tracking’’, or sam- voltage before the hold command was given. The overall pling, mode as much as possible to maximize the time the dynamic sampling error is the sum of the digital and analog , hold capacitor spends near the voltage at which it will errors. The curve labeled Dynamic Sampling Error will be eventually ‘‘hold’’. helpful in estimating these errors as a function of input slew The best capacitor for sample and hold applications is rate and hold capacitor size. Teflon. It is clearly superior with regard to dielectric ab- namic sampling error can be reduced by a factor of ten sorption and operates over the full —55°C to 125°C gr more by inserting a delay in the logic input so that the temperature range. If size or price becomes a problem, “‘hold’’ command is delayed by an amount equal to the the second choice for full temperature range operation is RC time constant of the LF198 and external hold capaci- ““NPO"’, or “COG” ceramic units. Some care must be tor. For a 0.01uF hold capacitor and the 1500 resistor in- used here—not all NPO capacitors use the low dielectric ternal to the LF198, this is 1.5ys. A simple RC network constant ceramic necessary for low dielectric absorption. can be used in front of the logic input for delays up to For lower temperatures (= 70°C), Polystyrene hastradi- = 44s, Longer delays require the addition of a logic gate tionally been the best hold capacitor. The best units are to speed up the rise time of the delayed signal. See LOGIC cylindrical and fairly large—there seems to be a strong RISE TIME in this section for further details. correlation between small size and poorer dielectric per- 19 | formance. Polypropylene has nearly the same absorption properties as polystyrene and offers 85°C operation. It Hold Step also tends to be smaller. Again, stay with cylindrically Hold step is the small voltage step (after settling) seen at wrapped units. Other standard dielectrics such as mica, the output of a sample and hold amplifier when it is glass, mylar, and ordinary ceramic are much worse with switched from the sample mode to the hold mode with a regard to dielectric absorption. Mylar is sometimes used steady DC input. Hold step is typically the result of, or can for large values when the ratio of sample to hold time is be modeled as, a fixed quantity of charge transferred to large and extremely low droop is required. the hold capacitor as a result of the internal switching that occurs during the hold command. In the case of the Dynamic Sampling Error LF198, that charge is about 5 picocoulombs, giving a A significant sampling error can occur in any sample and hold step of 0.5mV for a 0.01yF hold capacitor and SmV hold if the input is moving when the unit is put intothe hold for a 1000pF hold capacitor. (V=Q/C.) Hold step is mode. The two major causes for this error are digital delay in Teasonably independent of logic amplitude if care is taken switch opening and analog delay across the hold capacitor. to minimize the stray capacitance between the logic input LY ee 9-103

and the hold capacitor. With thoughtful layout, including Offset Zeroing the guarding technique shown below, stray capacitance A sample and hold amplifier has two distinct offset volt- should be under 0.3pF, limiting charge variations to less ages. The first is just the DC offset of the amplifier while in than 0.3 picocoulombs per volt. the sample or ‘‘tracking’’ mode. It is identical to the input offset of any operational amplifier. The second offset voltage is the sum of the DC offset plus a dynamic term Guarding Technique called hold step. Hold step is a change in output voltage when the amplifier is switched from sample mode to hold ve Mode, with the input held steady. This second offset is OFFSET ADWUST often called hold mode offset. It can be less than or much ne oO) greater than the DC offset, depending on the magnitude ©, and sign of hold step. Losic 1 5 INPUT A fairly accurate model for hold step is a fixed charge injected into the hold capacitor by the switch turn-off cir- Cuitry. The magnitude of the charge is reasonably inde- rao) @—_ pendent of logic input amplitude. The resulting change in AEFERENCE ‘ hold capacitor voltage is Q/Cp. The charge, Q, is typically O () 5 picocoulombs, giving a 0.5mV hold step with a 0.01 ,F OT ARD TOF AND “ (2 hold capacitor. Since most sample and hold amplifiers are i “‘used,”’ i.e., have their outputs read by an A to D con- ~~ verter, etc., during the hold mode, hold mode offset is vo 7 aN oureut arguably Much more important than sample mode DC capacioa” =} ot set. BOTTOM VIEW OC offset adjustment is accomplished with a 1k low TC cermet potentiometer tied to V+ with 0.6mA flowing Use 10-pin layout. Guard around Cy Is tied to output. through it and the wiper tied to pin 2. This allows pin 2 to be moved +: 300mV around its nominal voltage (0.3V below V+). Offset adjustment range is + 9mV, and the * — Hold step varies slightly with analog input voltage (see adjustment procedure nominally improves offset drift curves). A typical unit will change at 0.4 picocoulombs per when the DC offset is reduced to zero. This offset volt. This manifests itself as a gain error when the amplifier method can be used to zero out hold mode offset, but at is switched to the hold mode. With a 0.01F capacitor, the the expense of some induced offset drift. Each millivolt of resulting gain error will be (0.4 PC/V)/0.01pF =0.004%. hold step offset that is corrected by this method intro- This gain error is in the opposite direction of DC (sample duces 3.3uV/°C drift. For 0.002uF or larger hold mode) gain error. At high values of hold capacitor, DC gain Capacitors where hold step is a few millivolts or less, this error will dominate and gain will be slightly below unity is a practical solution to hold mode offset. In precision (0.002%). For low value capacitors (<0.01,F), hold step wide temperature range applications, or where Cp is less induced gain error will dominate and hold mode gain will than 0.002uF, a separate hold mode zeroing method be slightly above unity. Zeroing out hold step does not should be used. The circuit shown in the application sec- change the variation of hold step with regard to input tion using a logic inverter and a 5pF capacitor is recom- voltage. mended (DC AND AC ZEROING). rn 9-104 LY WAR

Hold step is independent of logic input fall time only for 1ps will have a large effect on hold step. If longer delays fall times faster than 10V/ys. For instance, as logic fall are required, they should be followed by several inverter time changes from 10V/ys to 1V/ps, hold step with a stages or a Schmitt trigger to increase slew rate. 0.01,F hold capacitor will typically increase from 0.25mV to 1.0mV. See the curve labeled HOLD STEP vs LOGIC Adding Delay to Logic Input SLEW RATE for further data points. If logic slew rate is not ve constant, use the value at the threshold point (1.5V with Fi respect to logic reference). An RC network will have a Be v discharge slew rate of V_/RC, where Vi is the logic ANALOG _3 S_ourpur threshold of the LF198. The delay generated by the net- mn fee work will be RC*in(V+/V,), where V+ is logic ampli- me J NON to" tude. For a 1ys delay, with 5V logic, an RC time constant eu [>-->° ad of 0.8us is needed. This has a slew rate of 2V/ys at ¢ threshold, which will slightly degrade hold step. It is ob- T _—oo vious that an RC delay network significantly longer then = SEE LOGIC INPUT CONFIGURATIONS * TTL and CMOS cmos 3V-sV, (Hi State) <10V TV sV_ (Hi State) <15V Op Amp Drive ve 7 a 7 sampie [8 = sampte ~]8 nu oe s = = —13V: HOLD Ak THRESHOLD =1.4V THRESHOLD =0.6 (V+) +1.4V THRESHOLD = +4V > we ve i RY nen 20k ba 2 HOLD 7 2.8 HOLD 7 n18 J Lem 3k J Lim am “| {- om “SELECT FOR 26 AT PIN : THRESHOLD =O (W+}—1.09 . -13V) ‘SAMPLE 4.7K THRESHOLD = —4¥ > “The logic input signal high state must be at least 2V below the positive supply voltage of the LF198. SS AT White 9-105

Sample and Difference Circuit (Output Follows Input in Hold Mode X1000 Sample and Hold and Resets to Vg in Sample Mode) 15 ‘ + "a 6 100k ™ . one, 4 Vour=Vu + Vy (HOLD MODE) OFFSET E> y on 15¥ * 3 > a Your ia - be RESET = Le 7 =e, j | ‘TRACK vin JL as “THIS RESISTOR PROTECTS INPUT - FROM SURGE CURRENTS, BUT INCREASES “FOR LOWER GAINS, THE LT1008 MUST BE FREQUENCY COMPENSATED SAMPLE TINE. 7 Oa USE = oF FROM COMP 2 TO GROUND Ramp Generator with Variable Reset Level Integrator with Programmable Reset Level ve ee v- -15¥ 15V ax RESET vq 3 Lo lt 5 Reser 3h : . 12 an RESET —, ak % Pinon, Rt RESET _ ft = DIFFERENTIAL a Vv . n wv T" INTEgRATING | zt 2 > RAMP 1 4 ; ™ “ar FOR RAMP RATE AY = wey Re 200k Your wou mo0e= [rte J vw] + [vs] ES 9-106 LT Wee

Output Holds at Average of Sampled Input Fast Acquisition, Low Droop Sample and Hold 15 15V v+ u -15V Dw —15V INPUT: & Sourpur “ey a iy 7 T ‘ TT” ‘ 7 Ay 0 = = = = +5V Tr" 0.0248 mk TL SELECT (Ry)(Ch) >> “arte Min) mo mss sms—+| be DC and AC Zeroing 2-Channel Switch oC 1V Vos 15y 24k 1k ZERO : 1 _isy 9 |

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Van > Vout ue T Sa “AN SELECT _ + S3ix 7 ‘Sv = 8 Ch ‘Spr og att! L "B" INPUT + AC (HOLD STEP) ZERO Gain 100% 10% | ow | ae) Bw = 1MHz = 400kHZ rq Crosstalk = —900B 9048 > o @ikhz Offset stv sTSmV re LY Were 9-107

A TYPICAL APPLICATIONS Staircase Generator : 15v as -15v RESET at = 3% OUT wv 4.7% a1 Orr t ov. (2N2222 es q 7 Hie 1 wv ‘50k Tu 1N914 x zt oy “Wad a7 I 4.7K 15v Eh ak Capacitor Hysteresis Compensation Differential Hold ve wwur, ea, £ ourPuT al ce WHEN fs Sal HOLD MODE 200K = | Loaic. = ze 7 IL a “SELECT FOR TIME CONSTANT C1 = sg + ** ADJUST FOR AMPLITUDE ne Y 9-108 LT Wee

a TYPICAL APPLICATIONS Isolated Temperature Sensor Ag joon* 7116 RI t y % “ | = psn, 03 20k 3 15 <e mre mM -t80 = 24k wot aul tony a 8 r ro aes au 3 -15v “COMPENSATES FOR TRANSFORMER RESISTANCE. SELECT FOR FLAT OUTPUT FROM LF198 WHILE 1M SAMPLE MODE. Pulse Width to Voltage Converter o tT1004 Smt a1 1.235V, 1.24k 2N3906 7 \\ ATO D CONVERTOR" a2 3 —15v Rie FY 3 45 2N3904 20 19 | ‘OVM OUTPUT ste on 1000pF J me e ZT rovsrynene 8 TF 3k > 1000pF POLY- [| Pd ‘STYRENE a3 2N3906 12k . _ sv i RE sy mauiat nee REF T RT “READ = 1ys AFTER f= ca ed 0 GOES LOW ~” = ‘FOR REPETITIVE PULSES 02-05 1N914 10009 ONLY INCREASE C5 FOR SE! LINEAR 9-109

Motor Speed Controller Needs No Tachometer* 15V R12 A13 7 | tk Ile = ty 14 = ie Chad A li: | i ‘1N914 16 ‘SPEED [Pope FF hf | = RS ~ ne: 3.9 ee is |e Be = are | ~ 0.03.F “BACK EMF OF MOTOR IS SAMPLED ‘tD1 IS USED FOR START-UP. IT > AND USED TO CONTROL SPEED. UMITS DUTY CYCLE TO ~75% **SELECT FOR OPTIMUM LOOP STABILITY. C3 1S NON POLARIZED LS DEFINITION OF TERMS Hold Step: The voltage step at the output of the amplifier Hold Settling Time: The time required for the output to ‘when switching from sample mode to hold mode with a settle within 1mV of final value after a hold command is constant analog input voltage and a logic swing of 5V. initiated. Acquisition Time: The time required to acquire, within a Dynamic Sampling Error: The error introduced into the defined error, a new analog input voltage with an output held output voltage due to a changing analog input at the change of 10V. Acquisition time includes output settling time the hold command is given. Error is expressed in mV time and includes the time required for all internal nodes with a given hold capacitor value and input slew rate. to settle so that the output is at the proper value when Note that this error term occurs even for long sample switched to the hold mode. times. Gain Error: The ratio of output voltage swing to input Aperture Time: The delay required between ‘‘Hold’’ voltage swing in the sample mode expressed as a percent command and an input analog transition, so that the tran- difference. sition does not affect the held output. 9-110 y @ Ab hiss

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PACKAGE DESCRIPTION pimensions in inches (millimeters) unless otherwise noted. H Package J8 Package Metal Can 8 Lead Hermetic DIP asso noon pans) : t Tas 7 == ie ue A esto ne ‘a woos = 1 we (e159 Se att 526 a an ae oozt—o0u #\\Y (0.686— 1.143) a0, i h is aus aus | a i A , “| |e 4 Sry) ies) a - ow a0e0) mone “LEADS WIT 0.007 OF TUE POSTON (7) AT GAUGE PANE INSULATING Ssanoore [rsa [ voo-c [ 100°c7w | re ee a Ee ee N8 Package :

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a 8000. oe) (am | aes res | “" et eusseas ama | ontam P)( aston } i nai eou-ten 0200-0310 “LEADS WITHIN 0.007 OF TRUE POSITION (TP) AT GAUGE PLANE Co On 9-112 7 @ Aa iio