LF198-N_16 TI1 | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3B –JULY 2000–REVISED NOVEMBER 2015 LF298,LFx98xMonolithicSample-and-HoldCircuits
1 Features 3 Description
The LF298 and LFx98x devices are monolithic 1• Operates from ±5-V to ±18-V Supplies sample-and-hold circuits that use BI-FET technology• Less than 10-μs Acquisition Time to obtain ultrahigh DC accuracy with fast acquisition
- Logic Input Compatible With TTL, PMOS, CMOS of signal and low droop rate. Operating as a unity- gain follower, DC gain accuracy is 0.002% typical and• 0.5-mV Typical Hold Step at Ch = 0.01 µF acquisition time is as low as 6 µs to 0.01%. A bipolar• Low Input Offset input stage is used to achieve low offset voltage and• 0.002% Gain Accuracy wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset• Low Output Noise in Hold Mode drift. The wide bandwidth allows the LF198-N to be• Input Characteristics Do Not Change During Hold included inside the feedback loop of 1-MHzMode operational amplifiers without having stability• High Supply Rejection Ratio in Sample or Hold problems. Input impedance of 1010 Ω allows high-
- Wide Bandwidth source impedances to be used without degrading accuracy.• Space Qualified, JM38510 P-channel junction FETs are combined with bipolar
2 Applications devices in the output amplifier to give droop rates as
low as 5 mV/min with a 1-µF hold capacitor. The• Ramp Generators With Variable Reset Level JFETs have much lower noise than MOS devices• Integrators With Programmable Reset Level used in previous designs and do not exhibit high
- Synchronous Correlators temperature instabilities. The overall design ensures no feedthrough from input to output in the hold mode,• 2-Channel Switches even for input signals equal to the supply voltages.• DC and AC Zeroing Logic inputs on the LF198-N are fully differential with• Staircase Generators low input current, allowing for direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4 V. The LF198-N will operate from ±5-V to ±18-V supplies. An A version is available with tightened electrical specifications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SOIC (14) 8.65 mm × 3.91 mm LF298, LFx98x TO-99 (8) 9.08 mm × 9.08 mm PDIP (8) 9.81 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Connection Acquisition Time An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3B –JULY 2000–REVISED NOVEMBER 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2000) to Revision B Page
- Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
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5 Pin Configuration and Functions
P Package D Package8-Pin PDIP 14-Pin SOICTop View Top View 8-Pin TO-99 Top View A military RETS electrical test specification is available on request. The LF198-N may also be procured to Standard Military Drawing #5962-8760801GA or to MIL-STD-38510 part ID JM38510/12501SGA. Pin Functions PIN TYPE(1) DESCRIPTION NAME SOIC TO-99 PDIP V+ 12 1 1 P Positive supply OFFSET ADJUST 14 2 2 A DC offset compensation pin INPUT 1 3 3 A Analog Input V– 3 4 4 P Negative supply OUTPUT 7 5 5 O Output Ch 8 6 6 A Hold capacitor LOGIC REFERENCE 10 7 7 I Reference for LOGIC input LOGIC 11 8 8 I Logic input for Sample and Hold modes NC 2, 4, 5, 6, 9, 13 — — NA No connect (1) P = Power, G = Ground, I = Input, O = Output, A = Analog Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Supply voltage ±18 V Power dissipation (Package limitation, see (3)) 500 mW LF198-N, LF198A-N –55 125 °C Operating ambient temperature LF298 –25 85 °C LF398-N, LF398A-N 0 70 °C Input voltage ±18 V Logic-to-logic reference differential voltage (see (4)) 7 −30 V Output short circuit duration Indefinite Hold capacitor short circuit duration 10 sec H package (soldering, 10 sec.) 260 °C N package (soldering, 10 sec.) 260 °C Lead temperature M package: vapor phase (60 sec.) 215 °C Infrared (15 sec.) 220 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. (3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA) / RθJA, or the number given in the for the LF298, 115°C; and for the LF398-N and LF398A-N, 100°C. (4) Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2 V below the positive supply and 3 V above the negative supply.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage ±15 V LF198-N, LF198A-N –55 125 TJ Ambient temperature LF298 –25 85 °C LF398-N, LF398A-N 0 70
6.3 Thermal Information
LF398-N LF298, LF398-N LFx98x THERMAL METRIC(1) P (PDIP) D (SOIC) LMC (TO-99) UNIT
8 PINS 14 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 48.9 80.6 85(2) °C/W RθJC(top) Junction-to-case (top) thermal resistance 37.3 38.1 20 °C/W RθJB Junction-to-board thermal resistance 26.2 35.4 — °C/W ψJT Junction-to-top characterization parameter 14.3 5.8 — °C/W ψJB Junction-to-board characterization parameter 26.0 35.1 — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Board mount in 400 LF/min air flow.
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6.4 Electrical Characteristics, LF198-N and LF298
The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ = 25°C 1 3 mV Input offset voltage(1) Full temperature range 5 mV TJ = 25°C 5 25 nA Input bias current(1) Full temperature range 75 nA Input impedance TJ = 25°C 10 GΩ TJ = 25°C, RL= 10k 0.002% 0.005% Gain error Full temperature range 0.02% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 96 dB Tj = 25°C, “HOLD”mode 0.5 2 Ω Output impedance Full temperature range 4 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 0.5 2 mV Supply current(1) TJ ≥ 25°C 4.5 5.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C(3), hold mode 30 100 pA ΔVOUT = 10 V, Ch = 1000 pF 4 µs Acquisition time to 0.1% CH = 0.01 µF 20 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 80 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V TJ = 25°C 1 1 mV Input offset voltage(1) Full temperature range 2 mV TJ = 25°C 5 25 nA Input bias current(1) Full temperature range 75 nA Input impedance TJ = 25°C 10 GΩ TJ = 25°C, RL = 10 k 0.002% 0.005% Gain error Full temperature range 0.01% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 96 dB TJ = 25°C, “HOLD”mode 0.5 1 Ω Output impedance Full temperature range 4 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 0.5 1 mV Supply current(1) TJ ≥ 25°C 4.5 5.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C(3), hold mode 30 100 pA ΔVOUT = 10 V, Ch = 1000 pF 4 6 µs Acquisition time to 0.1% CH = 0.01 µF 20 25 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 90 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V (1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V. (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. (3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
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6.5 Electrical Characteristics, LF398-N
The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ = 25°C 2 7 mV Input offset voltage(1) Full temperature range 10 mV TJ = 25°C 10 50 nA Input bias current(1) Full temperature range 100 nA Input impedance TJ = 25°C 10 GΩ TJ = 25°C, RL= 10 k 0.004% 0.01% Gain error Full temperature range 0.02% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 80 90 dB TJ = 25°C, “HOLD”mode 0.5 4 Ω Output impedance Full temperature range 6 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 1 2.5 mV Supply current(1) TJ ≥ 25°C 4.5 6.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C(3), hold mode 30 200 pA ΔVOUT = 10 V, Ch = 1000 pF 4 µs Acquisition time to 0.1% CH = 0.01 µF 20 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 80 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V TJ = 25°C 2 2 mV Input offset voltage(1) Full temperature range 3 mV TJ = 25°C 10 25 nA Input bias current(1) Full temperature range 50 nA Input impedance TJ = 25°C 10 GΩ TJ = 25°C, RL = 10 k 0.004% 0.005% Gain error Full temperature range 0.01% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 90 dB TJ = 25°C, “HOLD”mode 0.5 1 Ω Output impedance Full temperature range 6 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 1 1 mV Supply current(1) TJ ≥ 25°C 4.5 6.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C(3), hold mode 30 100 pA ΔVOUT = 10 V, Ch = 1000 pF 4 6 µs Acquisition time to 0.1% CH = 0.01 µF 20 25 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 90 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V (1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V. (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. (3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range.
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6.6 Typical Characteristics
Figure 1. Aperture Time Figure 2. Dielectric Absorption Error in Hold Capacitor Figure 3. Dynamic Sampling Error Figure 4. Output Droop Rate Figure 5. Hold Step Figure 6. Hold Settling Time
Figure 7. Leakage Current into Hold Capacitor Figure 8. Phase and Gain (Input to Output, Small Signal) Figure 10. Power Supply RejectionFigure 9. Gain Error Figure 11. Output Short Circuit Current Figure 12. Output Noise
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7 Parameter Measurement Information
7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
Figure 18. Sample When Logic High With TTL and CMOS Biasing Figure 19. Sample When Logic Low With TTL and CMOS Biasing
7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
Figure 20. Sample When Logic High With CMOS Biasing
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Figure 21. Sample When Logic Low With CMOS Biasing
7.3 Operational Amplifier Drive
Figure 22. Sample When Logic High With Operational Amplifier Biasing Figure 23. Sample When Logic Low With Operational Amplifier Biasing
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8 Detailed Description
8.1 Overview
The LF298 and LFx98x devices are monolithic sample-and-hold circuits that utilize BI-FET technology to obtain ultrahigh DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity-gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198-N to be included inside the feedback loop of 1-MHz operational amplifier without having stability problems. Input impedance of 1010 Ω allows high-source impedances to be used without degrading accuracy.
8.2 Functional Block Diagram
8.3 Feature Description
The LF298 and LFx98x OUTPUT tracks the INPUT signal by charging and discharging the hold capacitor. The OUTPUT can be held at any given time by pulling the LOGIC input low relative to the LOGIC REFERENCE voltage and resume sampling when LOGIC returns high. Additionally, the OFFSET pin can be used to zero the offset voltage present at the INPUT.
8.4 Device Functional Modes
The LF298 and LFx98x devices have a sample mode and hold mode controlled by the LOGIC voltage relative to the LOGIC REFERENCE voltage. The device is in sample mode when the LOGIC input is pulled high relative to the LOGIC REFERENCE voltage and in hold mode when the LOGIC input is pulled low relative to the LOGIC REFERENCE. In sample mode, the output is tracking the input signal by charging and discharging the hold capacitor. Smaller values of hold capacitance will allow the output to track faster signals. In hold mode the input signal is disconnected from the signal path and the output retains the value on the hold capacitor. Larger values of capacitance will have a smaller droop rate as shown in Figure 4.
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9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Hold Capacitor
Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size and cost may also become important for larger values. Use of the curves included with this data sheet should be helpful in selecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast signals, the capacitor drive currents may cause a significant temperature rise in the LF198-N. A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A mylar cap, for instance, may sag back up to 0.2% after a quick change in voltage. A long sample time is required before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not nearly as good. The advantage of polypropylene over polystyrene is that it extends the maximum ambient temperature from 85°C to 100°C. Most ceramic capacitors are unusable with > 1% hysteresis. Ceramic NPO or COG capacitors are now available for 125°C operation and also have low dielectric absorption. For more exact data, see Figure 2. The hysteresis numbers on the curve are final values, taken after full relaxation. The hysteresis error can be significantly reduced if the output of the LF198-N is digitized quickly after the hold mode is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10 to 50 ms. If A-to-D conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten.
9.1.2 DC and AC Zeroing
DC zeroing is accomplished by connecting the offset adjust pin to the wiper of a 1-kΩ potentiometer, which has one end tied to V+ and the other end tied through a resistor to ground. The resistor should be selected to give approximately 0.6 mA through the 1-kΩ potentiometer. AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output. A 10-pF capacitor from the wiper to the hold capacitor will give ±4-mV hold step adjustment with a 0.01-µF hold capacitor and 5-V logic supply. For larger logic swings, a smaller capacitor (< 10 pF) may be used.
9.1.3 Logic Rise Time
For proper operation, logic signals into the LF198-N must have a minimum dV/dt of 1.0 V/µs. Slower signals will cause excessive hold step. If a R/C network is used in front of the logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least 1.0 V/µs.
9.1.4 Sampling Dynamic Signals
Sample error to moving input signals probably causes more confusion among sample-and-hold users than any other parameter. The primary reason for this is that many users make the assumption that the sample and hold amplifier is truly locked on to the input signal while in the sample mode. In actuality, there are finite phase delays through the circuit creating an input-output differential for fast moving signals. In addition, although the output may have settled, the hold capacitor has an additional lag due to the 300-Ω series resistor on the chip. This means that at the moment the hold command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic which switches the circuit from sample to hold. For example, consider an analog input of 20 Vp–p at 10 kHz. Maximum dV/dt is 0.6 V/µs. With no analog phase delay and 100-ns logic delay, one could expect up to (0.1 µs) (0.6V/µs) = 60 mVerror if the hold signal arrived near maximum dV/dt of the input. A positive-going input would give a Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
(dynamic sampling error) is included to help estimate errors. Figure 6 indicates the time required for the output to settle to 1 mV after the hold command.
9.1.5 Digital Feedthrough
Use 10-pin layout. Guard around CH is tied to output. Figure 24. Guarding Technique
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9.2 Typical Applications
9.2.1 X1000 Sample and Hold
the appropriate value of capacitance for the COMP 2 pin capacitance of the LM108. Figure 25. X1000 Sample and Hold
9.2.1.1 Design Requirements
that the maximum dynamic range is used by the 1-Vpp data converter.
9.2.1.2 Detailed Design Procedure
C1 is 0.1 pF according to Equation 1, which is negligibly small and may be left off of the design.
9.2.1.3 Application Curves
and would be ready to sample as shown in Figure 27. Figure 26. Feedthrough Rejection Ratio (Hold Mode) Figure 27. Output Transient at Start of Hold Mode
9.2.2 Sample and Difference Circuit
Figure 28. Sample and Difference Circuit
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9.2.3 Ramp Generator With Variable Reset Level
time may be computed by Equation 2. Figure 29. Ramp Generator With Variable Reset Level
9.2.4 Integrator With Programmable Reset Level
Figure 30. The integrated output voltage in hold mode is computed with Equation 3. Figure 30. Integrator With Programmable Reset Level
9.2.5 Output Holds at Average of Sampled Input
Figure 31. Output Holds at Average of Sampled Input
9.2.6 Increased Slew Current
Figure 32. Increased Slew Current
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9.2.7 Reset Stabilized Amplifier
Figure 33. Reset Stabilized Amplifier
9.2.8 Fast Acquisition, Low Droop Sample and Hold
and hold circuit as shown in Figure 34. Figure 34. Fast Acquisition, Low Droop Sample and Hold
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9.2.9 Synchronous Correlator for Recovering Signals Below Noise Level
signals below noise level as shown in Figure 35. Figure 35. Synchronous Correlator for Recovering Signals Below Noise Level Figure 36. 2-Channel Switch In the configuration of Figure 36, input signal A and input signal B have the characteristics listed in Table 1.
Table 1. 2-Channel Switch Characteristics
9.2.11 DC and AC Zeroing
pin to create a DC- and AC-zeroing circuit as shown in Figure 37. Figure 37. DC and AC Zeroing
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9.2.12 Staircase Generator
The LF368 can be connected as shown in Figure 38 to create a staircase generator. *Select for step height: 50 kΩ → 1-V Step. Figure 38. Staircase Generator
9.2.13 Differential Hold
Two LF198-N devices may be connected as shown in Figure 39 to create a differential hold circuit. Figure 39. Differential Hold
9.2.14 Capacitor Hysteresis Compensation
The LF298 and LFx98x devices may be used for capacitor hysteresis compensation as shown in Figure 40. Figure 40. Capacitor Hysteresis Compensation
10 Power Supply Recommendations
operation for most loading conditions.
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11 Layout
11.1 Layout Guidelines
as close to the device as possible to minimize stray parasitics.
11.2 Layout Example
Figure 41 shows an example schematic and layout for the LFx98x 8-pin PDIP package. Figure 41. Schematic Example Figure 42. Layout Example
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
- Hold Step: The voltage step at the output of the sample and hold when switching from sample mode to hold mode with a steady (DC) analog input voltage. Logic swing is 5 V.
- Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10 V. Acquisition time is not just the time required for the output to settle, but also includes the time required for all internal nodes to settle so that the output assumes the proper value when switched to the hold mode.
- Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent difference.
- Hold Settling Time: The time required for the output to settle within 1 mV of final value after the hold logic command.
- Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. This error term occurs even for long sample times.
- Aperture Time: The delay required between hold command and an input analog transition, so that the transition does not affect the held output.
12.2 Related Links
resources, tools and software, and quick access to sample or buy. Table 2. Related Links
12.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
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12.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
www.ti.com 7-Mar-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LF198AH ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -55 to 125 ( LF198AH ~ LF198AH) LF198AH/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 ( LF198AH ~ LF198AH) LF198H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -55 to 125 ( LF198H ~ LF198H) LF198H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 ( LF198H ~ LF198H) LF298H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -25 to 85 ( LF298H ~ LF298H) LF298H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -25 to 85 ( LF298H ~ LF298H) LF298M NRND SOIC D 14 55 TBD Call TI Call TI -25 to 85 LF298M LF298M/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -25 to 85 LF298M LF298MX NRND SOIC D 14 2500 TBD Call TI Call TI -25 to 85 LF298M LF298MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -25 to 85 LF298M LF398AN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LF 398AN LF398H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI 0 to 70 LF398H LF398H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM 0 to 70 ( LF398H ~ LF398H) LF398M NRND SOIC D 14 55 TBD Call TI Call TI 0 to 70 LF398M LF398M/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LF398M LF398MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LF398M LF398N/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LF 398N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
www.ti.com 7-Mar-2016 Addendum-Page 2 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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