LF357D

LF155-LF255-LF355 STMICROELECTRONICS | Alldatasheet

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Technical content

8 - N.C. WIDE BANDWIDTH SINGLE J-FET OPERATIONAL AMPLIFIERS .HIGH INPUT IMPEDANCE J-FET INPUT STAGE .HIGH SPEED J-FET OP-AMPs : up to 20MHz, 50V/µs .OFFSET VOLTAGEADJUSTMENT DOES NOT DEGRADE DRIFT OR COMMON-MODE REJECTION AS IN MOST OF MONOLITHIC AMPLIFIERS .INTERNAL COMPENSATION AND LARGE DIFFERENTIAL INPUTVOLTAGECAPABILITY (UP TO VCC +) TYPICAL APPLICATIONS .PRECISION HIGH SPEED INTEGRATORS .FAST D/A AND CONVERTERS .HIGH IMPEDANCE BUFFERS .WIDEBAND, LOW NOISE, LOW DRIFT AMPLIFIERS .LOGARITHIMIC AMPLIFIERS .PHOTOCELL AMPLIFIERS .SAMPLE AND HOLD CIRCUITS N DIP8 (Plastic Package) 1 - Offset Null 1 2 - Inverting input 3 - Non-inverting input 4-V CC PIN CONNECTIONS (top view)

DESCRIPTION

These circuits are monolithic J-FET input operational amplifiers incorporating well matched, high voltage J-FET on the same chip with standard bipolar transis- tors. This amplifiers feature low input bias and offset cur- rents, low input offset voltage and input offset voltage drift,coupledwith offsetadjust which doesnot degrade drift or common-mode rejection. The devicesare also designed for high slew rate, wide bandwidth,extremelyfastsettlingtime, lowvoltageand current noise and a low 1/f noise level. LF155-LF255-LF355 LF156-LF256-LF356 LF157-LF257-LF357 July 1998 D SO8 (Plastic Micropackage) ORDER CODES Part Number Temperature Range Package ND LF355, LF356, LF357 0 oC, +70oC •• LF255, LF256, LF257 –40 oC, +105oC •• LF155, LF156, LF157 –55 oC, +125oC •• Example : LF355N

Symbol Parameter Value Unit VCC Supply Voltage ±22 V Vi Input Voltage - (note 1) ±20 V Vid Differential Input Voltage ±40 V Ptot Power Dissipation 570 mW Output Short-circuit Duration Infinite Toper Operating Free Air Temperature Range LF155-LF156-LF157 LF255-LF256-LF257 LF355-LF356-LF357 -55 to +125 –40 to +105 0t o7 0 oC Tstg Storage Temperature Range –65 to 150 oC SCHEMATIC DIAGRAM V io ADJUSTMENT LF155 - LF156 - LF157

ELECTRICAL CHARACTERISTICS

LF155, LF156, LF157 -55oC ≤ Tamb ≤ +125oC ±5V ≤ VCC ≤ ±20V LF255, LF256, LF257 -40oC ≤ Tamb ≤ +105oC ±5V ≤ VCC ≤ ±20V (unless otherwise specified) Symbol Parameter LF155 - LF156 - LF157 LF255 - LF256 - LF257 Unit Min. Typ. Max. Vio Input Offset Voltage (RS =5 0Ω ) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. LF155, LF156, LF157 LF255, LF256, LF257 6.2 mV Iio Input Offset Current - (note 3) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. LF155, LF156, LF157 LF255, LF256, LF257 32 0 pA nA nA I ib Input Bias Current - (note 3) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. LF155, LF156, LF157 LF255, LF256, LF257 20 100 pA nA nA Avd Large Signal Voltage Gain (RL =2 kΩ ,V O = ±10V, VCC = ±15V) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. 200 V/mV SVR Supply Voltage Rejection Ratio - (note 4) 85 100 dB ICC Supply Current (VCC = ±15V, no load) Tamb =2 5oC LF155, LF255 LF156, LF256 LF157, LF257 mA DV io Input Offset Voltage Drift (RS =5 0Ω )5 µV/oC DV io/Vio Change in Average Temperature Coefficient with Vioadjust (RS =5 0Ω ) - (note 2) 0.5 µV/oC Vicm Input Common Mode Voltage Range (VCC = ±15V, Tamb =2 5oC) ±11 +15.1 -12 V CMR Common Mode Rejection Ratio 85 100 dB ±VOPP Output Voltage Swing (VCC = ±15V) R L = 10kΩ R L =2 kΩ ±12 ±10 ±13 ±12 V GBP Gain Bandwidth Product (V CC = ±15V, Tamb =2 5oC) LF155, LF255 LF156, LF256 LF157, LF257 2.5 MHz SR Slew Rate (V CC = ±15V, Tamb =2 5oC) AV = 1 LF155, LF255 LF156, LF256 AV = 5 LF157, LF257 7.5 V/µs R i Input Resistance (Tamb =2 5oC) 10 12 Ω C i Input Capacitance (VCC = ±15V, Tamb =2 5oC) 3 pF en Equivalent Input Noise Voltage (VCC = ±15V, Tamb =2 5oC, RS = 100Ω ) f = 1000Hz LF155, LF255 LF156, LF256 LF157, LF257 f = 100Hz LF155, LF255 LF156, LF256 LF157, LF257 nV √Hz i n Equivalent Input Noise Current (VCC = ±15V, Tamb =2 5oC, f = 100Hz or f = 1000Hz) 0.01 pA √Hz ts Settling Time (VCC = ±15V, Tamb =2 5oC) - (note 5) LF155, LF255 LF156, LF256 LF157, LF257 1.5 1.5 µs LF155 - LF156 - LF157

Notes : 1. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. 2. The temperature coefficient of the adjusted input offset voltage changes only a small amount (0.5µV/oC typically) for each mV of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are alsounaffected by offset adjustment. 3. The input bias currents are junction leakage currents which approx imately double for every 10oC increase in the junction temperature Tamb . Due to limited produc tion test time, the input bias current measured is correlated to junction temperature. In a normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, P tot-Tamb =Tamb +R th(j-a)xPtotwhere Rth(j-a)is the thermal resistance from junction to ambient. Use of a heatsink is recommended f input currents are to be kept to a minimum. 4. Supply voltage rejection is measured for both supply magnitudes increasing or decreasing simultaneou sly, in accordance with common practise. 5. Settling time is defined here, for a unity gain inverter connection using 2kΩ resistors for the LF155, LF156 series. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF157 series AV = -5, the feedback resistor from output to input is 2kΩ and the output step is 10V. LF355, LF356, LF357 0oC ≤ Tamb ≤ +70oCV CC = ±15V, (unless otherwise specified) Symbol Parameter LF355 - LF356 - LF357 UnitMin. Typ. Max. Vio Input Offset Voltage (RS =5 0Ω ) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. 31 0 mV Iio Input Offset Current - (note 3) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. 35 0 pA nA Iib Input Bias Current - (note 3) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. 20 200 pA nA Avd Large Signal Voltage Gain (RL =2 kΩ ,V O = ±10V) Tamb =2 5oC Tmin.≤ Tamb ≤ Tmax. 200 V/mV SVR Supply Voltage Rejection Ratio - (note 4) 80 100 dB ICC Supply Current (no load) Tamb =2 5oC LF355 LF356, LF357 mA DV io Input Offset Voltage Drift (RS =5 0Ω ) - (note 2) 5 µV/oC DV io/Vio Change in Average Temperature Coefficient with Vioadjust (RS =5 0Ω ) 0.5 µV/oC per mV Vicm Input Common Mode Voltage Range (Tamb =2 5oC) ±10 +15.1 -12 V CMR Common Mode Rejection Ratio 80 100 dB ±VOPP Output Voltage Swing R L = 10kΩ R L =2 kΩ ±12 ±10 ±13 ±12 V GBP Gain Bandwidth Product T amb =2 5oC) LF355 LF356 LF357 2.5 MHz SR Slew Rate (T amb =2 5oC) AV = 1 LF355 LF356 AV = 5 LF357 V/µs R i Input Resistance (Tamb =2 5oC) 10 12 Ω C i Input Capacitance (Tamb = 25oC) 3 pF en Equivalent Input Noise Voltage (Tamb =2 5oC, RS = 100Ω ) f = 1000Hz LF355 LF356, LF357 f = 100Hz LF355 LF356, LF357 nV √Hz i n Equivalent Input Noise Current (Tamb =2 5oC, f = 100Hz or f = 1000Hz) 0.01 pA √Hz ts Settling Time (Tamb =2 5oC) - (note 5) LF355 LF356, LF357 1.5 µs LF155 - LF156 - LF157

The LF155, LF156, LF157 series are op amps with J- FETinput transistors. TheseJFETs havelarge reverse breakdown voltagesfromgatetosource or drain elimi- natingtheneed of clamps acrossthe inputs.Therefore large differential input voltages can easily be accom- modatedwithoutalarge increaseof inputcurrents. The maximum differential input voltage is independent of the supplyvoltage. However, neitherof thenegativein- put voltagesshouldbe allowed to exceedthe negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-modelimit on either inputwill causeareversal of thephasetotheoutputandforce the amplifier output to the correspondinghigh or lowstate. Exceedingthe negativecommon-mode limit on bothinputs will force the amplifier outputto a highstate.In neithercasedoes a latch occur since raising the input back within the common-mode range again puts the input stage and thustheamplifierin a normal operatingmode. Exceed- ingthepositive common-modelimit on asingle input will not changethephase of the output however, if bothin- putsexceedthe limit, theoutput of theamplifier will be forcedto ahighstate.Theseamplifierswill operatewith the common-mode input voltage equal to the positive supply. In fact, the common-modevoltagecanex- ceedthepositivesupplyby approximately100mV inde- pendentof supply volt-age and over thefull operat- ingtemperaturerange.The positive suplly can there- forebe used asa referenceonaninput as, forexample, in a supply current monitor and/orlimiter. Precautions- shouldbe taken to ensurethat thepowersupplyforthe integrated circuit never becomes re-versed in polarity or that the unit is not inadvertentlyin-stalledbackwards in a socket as an unilimited current surge throughthe resulting forward diode within the IC couldcausefusin- goftheinternalconductorsandresultin a destroyedunit. Because these amplifiers are JFET rather than MOS- FET input op amps they do not require special han- dling. Allof thebiascurrentsintheseamplifiersareset byFET current sources. The drain currents for the amplifiers are therefore essentially independent of supply volt- ages. As with most amplifiers, care should betakenwith lead dress, components placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to theinput to minimiz ”pickup”and maximize the frequencyof the feedbackpole by minimizing the ca- pacitancefromthe input to ground. A feedback pole is createdwhen the feedbackaround any amplifier is resistive. The parallel resistance and capacitancefromthe input of thedevice(usuallythe in- vertinginput)toacgroundsetthefrequencyofthepole.In many instances the frequency of this pole is much greaterthanthe expected3 dBfrequencyof the closed loopgain and consequentlythereisnegligible effect on stability margin. However, if the feedback pole is less than approximately six time the expected 3 dB fre- quencyaleadcapacitor should be placed from the out- put to the input of the op amp. The value of that added capacitorshould be such that the RC time constant of this capacitorand the resistance it parallels is greater than or equal to the original feedback pole time con- stant. APPLICATION HINTS LF155 - LF156 - LF157

PM-DIP8.EPS PACKAGE MECHANICAL DATA

8 PINS - PLASTIC DIP

Dimensions Millimeters Inches A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D 10.92 0.430 E 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0260 i 5.08 0.200 L 3.18 3.81 0.125 0.150 Z 1.52 0.060 DIP8.TBL LF155 - LF156 - LF157

PM-SO8.EPS PACKAGE MECHANICAL DATA

8 PINS - PLASTIC MICROPACKAGE (SO)

Dimensions Millimeters Inches A 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45 o (typ.) D 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.150 0.157 L 0.4 1.27 0.016 0.050 M 0.6 0.024 S8 o (max.) SO8.TBL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifi- cations mentioned in this publication are subject to change without notice. This publication supersedes and replaces all infor- mation previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  The ST logo is a trademark of STMicroelectronics  1998 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdo m - U.S.A. ORDER CODE : LF155 - LF156 - LF157