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Sample & Buy T echnical Documents Tools & Software Support & Community LF155, LF156, LF256, LF257 LF355, LF356, LF357 SNOSBH0D –MAY 2000–REVISED NOVEMBER 2015 LFx5xJFETInputOperationalAmplifiers

1 Features 2 Applications

1• Advantages • Precision High-Speed Integrators

  • Fast D/A and A/D Converters– Replace Expensive Hybrid and Module FET Op Amps • High Impedance Buffers – Rugged JFETs Allow Blow-Out Free Handling • Wideband, Low Noise, Low Drift Amplifiers Compared With MOSFET Input Devices • Logarithmic Amplifiers – Excellent for Low Noise Applications Using • Photocell Amplifiers Either High or Low Source Impedance— Very • Sample and Hold CircuitsLow 1/f Corner – Offset Adjust Does Not Degrade Drift or 3 Description Common-Mode Rejection as in Most The LFx5x devices are the first monolithic JFET inputMonolithic Amplifiers operational amplifiers to incorporate well-matched, – New Output Stage Allows Use of Large high-voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). TheseCapacitive Loads (5,000 pF) Without Stability amplifiers feature low input bias and offsetProblems currents/low offset voltage and offset voltage drift,– Internal Compensation and Large Differential coupled with offset adjust, which does not degradeInput Voltage Capability drift or common-mode rejection. The devices are also
  • Common Features designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current– Low Input Bias Current: 30 pA noise and a low 1/f noise corner.– Low Input Offset Current: 3 pA – High Input Impedance: 1012 Ω Device Information(1) – Low Input Noise Current: 0.01 pA/√Hz PART NUMBER PACKAGE BODY SIZE (NOM) – High Common-Mode Rejection Ratio: 100 dB SOIC (8) 4.90 mm × 3.91 mm LFx5x TO-CAN (8) 9.08 mm × 9.08 mm– Large DC Voltage Gain: 106 dB PDIP (8) 9.81 mm × 6.35 mm• Uncommon Features (1) For all available packages, see the orderable addendum at– Extremely Fast Settling Time to 0.01%: the end of the data sheet. – 4 μs for the LFx55 devices – 1.5 μs for the LFx56 Simplified Schematic – 1.5 μs for the LFx57 (AV = 5) – Fast Slew Rate: – 5 V/µs for the LFx55 – 12 V/µs for the LFx56 – 50 V/µs for the LFx57 (AV = 5) – Wide Gain Bandwidth: – 2.5 MHz for the LFx55 devices – 5 MHz for the LFx56 – 20 MHz for the LFx57 (AV = 5) – Low Input Noise Voltage: – 20 nV/√Hz for the LFx55 3 pF in LF357 series– 12 nV/√Hz for the LFx56 – 12 nV/√Hz for the LFx57 (AV = 5) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LF155, LF156, LF256, LF257 LF355, LF356, LF357 SNOSBH0D –MAY 2000–REVISED NOVEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D Page

  • Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Changes from Revision B (March 2013) to Revision C Page

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5 Pin Configuration and Functions

Available per JM38510/11401 or JM38510/11402 Pin Functions PIN I/O DESCRIPTION NAME NO. BALANCE 1, 5 I Balance for input offset voltage +INPUT 3 I Noninverting input –INPUT 2 I Inverting input NC 8 — No connection OUTPUT 6 O Output V+ 7 — Positive power supply V– 4 — Negative power supply Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 LF156 LF256 LF356

LF155, LF156, LF256, LF257 LF355, LF356, LF357 SNOSBH0D –MAY 2000–REVISED NOVEMBER 2015 www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3) MIN MAX UNIT LF155x, LF256x, LF356B ±22 Supply voltage V LF35x ±18 LF15x, LF25x, LF356B ±40 Differential input voltage V LF35x ±30 LF15x, LF25x, LF356B ±20 Input voltage(4) V LF35x ±16 Output short circuit duration Continuous — LF15x 150 LMC package LF25x, LF356B, LF35x 115 TJMAX °C P package LF25x, LF356B, LF35x 100 D package LF25x, LF356B, LF35x 100 TO-99 package Soldering (10 sec.) 300Soldering PDIP package Soldering (10 sec.) 260information °C(lead temp.) Vapor phase (60 sec.) LF25x, LF356B, LF35x 215 SOIC package Infrared (15 sec.) LF25x, LF356B, LF35x 220 Storage temperature, Tstg −65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD = (TJMAX − TA) / θJA or the 25°C PdMAX, whichever is less. (3) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications. (4) Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±1000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) 100 pF discharged through 1.5-kΩ resistor

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT LF15x ±15 VS ±20 LF25x ±15 VS ±20 Supply voltage, VS V LF356B ±15 VS ±20 LF35x ±15 LF15x –55 TA 125 LF25x –25 TA 85 TA °C LF356B 0 TA 70 LF35x 0 TA 70

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6.4 Thermal Information

LF155, LF156, LF355, LF357 LF356 DTHERMAL METRIC(1) P (PDIP) LMC (TO-99) P (PDIP) UNIT(SOIC)

8 PINS 8 PINS 8 PINS 8 PINS

Junction-to-ambient thermal resistance 130 195 — 55.2 RθJA Still Air — — 160 — °C/W

400 LF/Min Air Flow — — 65 —

RθJC(top) Junction-to-case (top) thermal resistance — — 23 44.5 °C/W RθJB Junction-to-board thermal resistance — — — 32.4 °C/W ψJT Junction-to-top characterization parameter — — — 21.7 °C/W ψJB Junction-to-board characterization parameter — — — 32.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 AC Electrical Characteristics, TA = TJ = 25°C, VS = ±15 V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LFx55 5 LF15x: AV = 1 LFx56, LF356B 7.5 SR Slew Rate V/μs LFx56, LF356B 12 LF357: AV = 5 LFx57 50 LFx55 2.5 Gain BandwidthGBW LFx56, LF356B 5 MHzProduct LFx57 20 LFx55 4 Settling Time tots LFx56, LF356B 1.5 μs0.01%(1) LFx57 1.5 LFx55 25 f = 100 Hz LFx56, LF356B 15 nV/√Hz LFx57 15Equivalent Inputen RS = 100 ΩNoise Voltage LFx55 20 f = 1000 Hz LFx56, LF356B 12 nV/√Hz LFx57 12 LFx55 f = 100 Hz LFx56, LF356B 0.01 pA/√Hz LFx57Equivalent Inputin Current Noise LFx55 f = 1000 Hz LFx56, LF356B 0.01 pA/√Hz LFx57 LFx55 InputCIN LFx56, LF356B 3 pFCapacitance LFx57 (1) Settling time is defined here, for a unity gain inverter connection using 2-kΩ resistors for the LF15x. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10-V step input is applied to the inverter. For the LF357, AV = −5, the feedback resistor from output to input is 2 kΩ and the output step is 10 V (See Settling Time Test Circuit). Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 LF156 LF256 LF356

LF155, LF156, LF256, LF257 LF355, LF356, LF357 SNOSBH0D –MAY 2000–REVISED NOVEMBER 2015 www.ti.com

6.6 DC Electrical Characteristics, TA = TJ = 25°C, VS = ±15 V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LF155 2 4 LF355 2 4 Supply current LFx56, LF356B 5 7 mA LF356 5 10 LF357 5 10

6.7 DC Electrical Characteristics

See (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LF15x, LF25x, LF356B 3 5 TA = 25°C LF35x 3 10 VOS Input offset voltage RS = 50 Ω LF15x 7 mV Over LF25x, LF356B 6.5temperature LF35x 13 Average TC of inputΔVOS/ΔT RS = 50 Ω LF15x, LF25x, LF356B, LF35x 5 μV/°Coffset voltage Change in average TC μV/°CΔTC/ΔVOS RS = 50 Ω(2) LF15x, LF25x, LF356B, LF35x 0.5with VOS adjust per mV LF15x, LF25x, LF356B 3 20 TJ = 25°C(1) (3) pA LF35x 3 50 IOS Input offset current LF15x 20 TJ ≤ THIGH LF25x, LF356B 1 nA LF35x 2 LF15x, LF25x, LF356B 30 100 TJ = 25°C(1) (3) pA LF35x 30 200 IB Input bias current LF15x 50 TJ ≤ THIGH LF25x, LF356B 5 nA LF35x 8 RIN Input resistance TJ = 25°C LF15x, LF25x, LF356B, LF35x Ω1012 LF15x, LF25x, LF356B 50 200 TA = 25°CVS = ±15 V, LF35x 25 200 AVOL Large signal voltage gain VO = ±10 V, V/mV LF15x, LF25x, LF356B 25OverRL = 2 kΩ temperature LF35x 15 VS = ±15 V, RL = 10 kΩ LF15x, LF25x, LF356B, LF35x ±12 ±13 VO Output voltage swing V VS = ±15 V, RL= 2 kΩ LF15x, LF25x, LF356B, LF35x ±10 ±12 (1) Unless otherwise stated, these test conditions apply: LF15x LF25x LF356B LF35x Supply Voltage, VS ±15 V ≤ VS ≤ ±20 V ±15 V ≤ VS ≤ ±20 V ±15 V ≤ VS ≤ ±20 V VS = ±15 V THIGH +125°C +85°C +70°C +70°C and VOS, IB and IOS are measured at VCM = 0. (2) The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5 μV/°C typically) for each mV of adjustment from its original unadjusted value. Common-mode rejection and open-loop voltage gain are also unaffected by offset adjustment. (3) The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + θJA Pd where θJA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.

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LF155, LF156, LF256, LF257 LF355, LF356, LF357 www.ti.com SNOSBH0D –MAY 2000–REVISED NOVEMBER 2015 See (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LF15x, LF25x, LF356B 11 15.1 VCM, High LF35x 10 15.1Input common-modeVCM VS = ±15 V Vvoltage range LF15x, LF25x, LF356B −12 –11 VCM, Low LF35x −12 –10 LF15x, LF25x, LF356B 85 100Common-mode rejectionCMRR dBratio LF35x 80 100 LF15x, LF25x, LF356B 85 100Supply voltage rejectionPSRR dBratio(4) LF35x 80 100 (4) Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.

6.8 Power Dissipation Ratings

LF25x, LF356B, LF35x 400 LF15x 1200Power Dissipation at LMC Package mWTA = 25°C (1) (2) (400 LF/Min Air Flow) LF25x, LF356B, LF35x 1000 P Package LF25x, LF356B, LF35x 670 D Package LF25x, LF356B, LF35x 380 (1) The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD = (TJMAX − TA) / θJA or the 25°C PdMAX, whichever is less. (2) Maximum power dissipation is defined by the package characteristics. Operating the part near the maximum power dissipation may cause the part to operate outside specified limits. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 LF156 LF256 LF356

6.9 Typical Characteristics

6.9.1 Typical DC Performance Characteristics

Curves are for LF155 and LF156 unless otherwise specified. Figure 2. Input Bias CurrentFigure 1. Input Bias Current Figure 4. Voltage SwingFigure 3. Input Bias Current Figure 5. Supply Current Figure 6. Supply Current

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6.9.2 Typical AC Performance Characteristics

Figure 14. Gain BandwidthFigure 13. Gain Bandwidth Figure 16. Output ImpedanceFigure 15. Normalized Slew Rate Figure 18. LF155 Small Signal Pulse Response, AV = +1Figure 17. Output Impedance

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Figure 25. Bode Plot Figure 26. Bode Plot Figure 27. Bode Plot Figure 28. Common-Mode Rejection Ratio Figure 29. Power Supply Rejection Ratio Figure 30. Power Supply Rejection Ratio

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LF155, LF156, LF256, LF257 LF355, LF356, LF357 SNOSBH0D –MAY 2000–REVISED NOVEMBER 2015 www.ti.com

7 Detailed Description

7.1 Overview

These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET Technology). These amplifiers feature low input bias and offset currents, as well as low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. These devices can replace expensive hybrid and module FET operational amplifiers. Designed for low voltage and current noise and a low 1/f noise corner, these devices are excellent for low noise applications using either high or low source impedance.

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7.2 Functional Block Diagram

Figure 34. Detailed Schematic

LF155, LF156, LF256, LF257 LF355, LF356, LF357 SNOSBH0D –MAY 2000–REVISED NOVEMBER 2015 www.ti.com

7.3 Feature Description

7.3.1 Large Differential Input Voltage

These are operational amplifiers with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit.

7.3.2 Large Common-Mode Input Voltage

These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter.

7.4 Device Functional Modes

The LFx5x has a single functional mode and operates according to the conditions listed in the Recommended Operating Conditions.

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize pick-up and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3-dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3-dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 LF156 LF256 LF356

8.2 Typical Application

Figure 35. Settling Time Test Circuit

8.2.1 Design Requirements

8.2.2 Detailed Design Procedure

Connect the circuit components as shown in Figure 35. In particular, use FET to isolate the probe capacitance. Apply a 10-V step function to the input. Use an oscilloscope to probe the circuit as shown in Figure 35.

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8.2.3 Application Curves

Figure 36. LF355 Figure 37. LF356 Figure 38. LF357

8.3 System Examples

Figure 39. Low Drift Adjustable Voltage Reference

  • ΔVOUT / ΔT = ±0.002%/°C
  • All resistors and potentiometers should be wire-wound
  • P1: drift adjust
  • P2: VOUT adjust
  • Use LF155 for – Low IB – Low drift – Low supply current

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Figure 40. Fast Logarithmic Converter

  • Dynamic range: 100 μA ≤ Ii ≤ 1 mA (5 decades), |VO| = 1 V/decade
  • Transient response: 3 μs for ΔIi = 1 decade
  • C1, C2, R2, R3: added dynamic compensation
  • VOS adjust the LF156 to minimize quiescent error
  • RT: Tel Labs type Q81 + 0.3%/°C (1) Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 LF156 LF256 LF356

Figure 41. Precision Current Monitor

  • VO = 5 R1/R2 (V/mA of IS)
  • R1, R2, R3: 0.1% resistors
  • Use LF155 for – Common-mode range to supply range – Low IB – Low VOS – Low Supply Current

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Figure 44. Boosting the LF156 With a Current Amplifier

  • IOUT(MAX) ≃ 150 mA (will drive RL ≥ 100 Ω) (3)
  • No additional phase shift added by the current amplifier

Figure 45. Decades VCO

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Figure 48. Noninverting Unity Gain Operation for LF157 Figure 49. Inverting Unity Gain for LF157

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Figure 50. High Impedance, Low Drift Instrumentation Amplifier

  • System VOS adjusted via A2 VOS adjust
  • Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift (8) Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 LF156 LF256 LF356

Figure 51. Fast Sample and Hold

  • Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)
  • Acquisition time TA, estimated by: (9)
  • LF156 develops full Sr output capability for VIN ≥ 1 V
  • Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop
  • Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2

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Figure 52. High Accuracy Sample and Hold

  • By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1. – No VOS adjust required for A2.
  • TA can be estimated by same considerations as previously but, because of the added – propagation delay in the feedback loop (A2) the overshoot is not negligible.
  • Overall system slower than fast sample and hold
  • R1, CC: additional compensation
  • Use LF156 for – Fast settling time – Low VOS Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 29 LF156 LF256 LF356

Figure 53. High Q Band Pass Filter

  • By adding positive feedback (R2)
  • Q increases to 40
  • fBP = 100 kHz (10)
  • Clean layout recommended
  • Response to a 1-Vp-p tone burst: 300 μs

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Figure 56. Driving Capacitive Loads

  • *LF15x R = 5k, LF357 R = 1.25 k
  • Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) ≃ 0.01 μF.
  • Overshoot ≤ 20%, Settling time (ts) ≃ 5 μs

Figure 57. LF357 - A Large Power BW Amplifier For distortion ≤ 1% and a 20 Vp-p VOUT swing, power bandwidth is: 500 kHz.

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9 Power Supply Recommendations

and operating junction temperature.

10 Layout

10.1 Layout Guidelines

10.1.1 Printed-Circuit-Board Layout For High-Impedance Work

surface leakage will be appreciable. the amplifier inputs, it will significantly reduce this leakage current. Figure 58. Inverting Amplifier Figure 59. Noninverting Amplifier

Figure 60. Typical Connections Of Guard Rings are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 61. (Input pins are lifted out of PCB and soldered directly to components. All other pins connected to PCB). Figure 61. Air Wiring adhered to, during all phases of inspection, test and assembly.

10.2 Layout Example

Figure 62. Examples Of Guard

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11 Device and Documentation Support

11.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

11.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.3 Trademarks

BI-FET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 19-Jul-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LF156 MD8 ACTIVE DIESALE Y 0 204 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LF156H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -55 to 125 ( LF156H ~ LF156H) LF156H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 ( LF156H ~ LF156H) LF256H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -25 to 85 ( LF256H ~ LF256H) LF256H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -25 to 85 ( LF256H ~ LF256H) LF356 MWC ACTIVE WAFERSALE YS 0 1 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 LF356H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI 0 to 70 ( LF356H ~ LF356H) LF356H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM 0 to 70 ( LF356H ~ LF356H) LF356M NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LF356 M LF356M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LF356 M LF356MX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LF356 M LF356MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LF356 M LF356N/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LF 356N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

www.ti.com 19-Jul-2016 Addendum-Page 2 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LF356MX SOIC D 8 2500 367.0 367.0 35.0 LF356MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2015 Pack Materials-Page 2

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