Amplifier

LF356BH

National Semiconductor ...

Series Monolithic JFET Input Operational Amplifiers

Manufacturer: National Semiconductor ...

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5 . g GA National = Semiconductor o . . . 5 | LF155/LF156/LF157 Series Monolithic & JFET Input Operational Amplifiers

5 LF155/LF155A/LF255/LF355/LF355A/

4 | LF355B Low Supply Current aq | LF156/LF156A/LF256/LF356/LF356A/ is | LF356B Wide Band np | LF157/LF157A/LF257/LF357/LF357A/ = | LF357B Wide Band Decompensated (Ayn = 5) a General Description {2 | These are the first monolithic JFET input operational ampli- @ Photocell amplifiers 4 | fiers to incorporate well matched, high voltage JFETs on the ™ Sample and Hold circuits & | same chip with standard bipolar transistors (BI-FET™ Tech- Pr nology). These amplifiers feature low input bias and offset Common Features 9 | currents/low offset voltage and offset voltage drift, coupled £2 | with offset adjust which does not degrade drift or common- (LF 155A, LF156A, LF157A) — | mode rejection. The devices are also designed for high slew | ™ Low input bias current 30 pA © | rate, wide bandwidth, extremely fast settling time, low volt- ™@ Low Input Offset Current 3 pA @& | age and current noise and a low 1/f noise corner. @ High input impedance 10120 bar @ Low input offset voltage 1 mV 3 Advantages 1m Low input offset voltage temp. drift 3 pvc 9 | m Replace expensive hybrid and module FET op amps @ Low input noise current 0.01 pA/VHz iS | m Rugged JFETs allow biow-out free handling compared — ™ High common-mode rejection ratio 100 dB En with MOSFET input devices l® Large de voltage gain 106 dB s ™ Excellent for low noise applications using either high or {© | low source impedance—vary low 1/f corner Uncommon Features & | m Offset adjust does not degrade drift or common-mode LFIS7A 8 rejection as in most monolithic amplifiers LFI55A LFI56A (Ay=5) Units iL | # New output stage allows use of large capacitive loads Extremely 4 15 1.5 us a (10,000 pF) without stability problems fast settling (0 | m Internal compensation and large differential input volt- time to 9 age capability 0.01% oO S sae @ Fast slew < Applications rate 5 12 50 V/us 9 | ™ Precision high speed integrators = Wide gain © | m Fast D/A and A/D converters bandwidth 25 5 20. MHz 1B | m High impedance butfers Low input & | = Wideband, low noise, low drift amplifiers noise voltage 20 12 12 nVAz | m Logarithmic amplifiers wy | a 4; | Simplified Schematic a, vee z ) ey J 3 5 in 7b aur i uml ot yy et 4 if rt w “3 pF in “F157 series. o-VEE TL/H/5646-1 3-24

c . un Absolute Maximum Ratings a if Milltary/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for a availability and specifications. n (Note 8) s LF3558/6B/7B LF355/6/7 LFISSA/6A/7A LP185/6/7 LF255/6/7 LFSSSA/6A/7A | = Supply Voltage £22V +22V +22V +18V v Differential Input Voltage +40V +40V +40V +30V g Input Voltage Range (Note 2) £20V +20V +20V £16V e Output Short Circuit Duration Continuous Continuous Continuous Continuous 2 Timax a H-Package 150°C 150°C 115°C 115°C Pry N-Package 100°C 100°C 2 J-Package 150°C 115°C 115°C Fy M-Package 100°C 100°C 3 Power Dissipation at Ta = 25°C (Notes t and 9) a H-Package (Still Air) ‘560 mW 560 mW 400 mw 400 mw o H-Package (400 LF/Min Air Flow) 1200 mw 1200 mW 1000 mw 1000 mw Ss N-Package 670 mW 670 mW La J-Package 1260 mw 900 mw 900 mw = M-Package 380 mw 380 mW $ Thermal Resistance (Typical) 8 ya, = H-Package (Still Air) 160°C/W 160°C/W 160°C/W 160°C/W g H-Package (400 LF/Min Air Flow) 65°C/W 65°C/W 65°C/W 65°C/W Pd N-Package 130°C/W 130°C/W Ps J-Package 100°C/W 100°C/W 100°C/W bl M-Package 195°C/W 195°C/W x (Typical) @4c S H-Package 2a°C/Ww 23°C/W 23°C/W 23°C/W So Storage Temperature Range —65°Cto + 150°C 9 —-65°Cto+ 150°C 9 —-65°Cto + 150°C 9 -65°C to + 150°C e ' ‘Soldering Information (Lead Temp.) 3 | Metal Can Package ce | Soldering (10 sec.) 300°C 300°C 300°C 300°C a i Dual-In-Line Package a : Soldering (10 sec.) 260°C 260°C 260°C 4 | Small Outline Package nN i Vapor Phase (60 sec.) 215°C 215°C g | Infrared (15 sec.) 220°C 220°C ! See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface. g i mount devices. = | ESD tolerance ~ | (100 pF discharged through 1.5 kf) 1200V 1200V 1200V 1200V A] j ~ | DC Electrical Characteristics (note 3), = 7, = 25°¢ a LFISSA/6A/7A z | win [ typ [ max [ win | Typ | Max | a i Vos Input Offset Voltage Rs=500, Ta= 25°C mv a Over Temperature mV 2 AVos/AT Average TC of Input Rsg=502 Nie} a 3 i Offset Voltage » g ATC/AVog | Change in Average TC | Rg=502, (Note 4) pve 2 with Vog Adjust permV 8 . los input Offset Current T\\= 25°C, (Notes 3, 5) 10 pA > Tj<THigH 10 m5 ip Input Bias Current T/=25°C, (Notes 3, 5) pA g T\\STHIGH nA a Avot Large Signal Voltage | Vs= +15V, Ta=25°C vimV Gain Vo= +10V, RL=2k Wmv Over Temperature Vo Output Voltage Swing | Vg=+15V,RL=10k | +12 | +13 +12 | +13 v 3-25

‘8| DC Electrical Characteristics (ote) tT, = 7; = 25°C (Continued) < LFISSA/6A/7A 3 [win [typ | max | win | typ | Max | nm] Yom Input Common-Mode = +151 +151 Vv

5 Voltage Range Vg= + 15V 211 ~12 a 12 Vv

ar] CMRR- Common-Mode Rejection 4B ~ Ratio & | PsAR Supply Voltage Rejection | (Note 6) 400 3B x Ratio a aj| AC Electrical Characteristics 1, = 1; = 25°C, vs= +15v S = | Symbol Units Z| sr Slew Rate LF155A/6A; Ay=1, V/ps a LFI57A; Ay=5 V/ps | GBw | Gain Bandwidth eyo [emer | test fetes) et || $\\s (Note 7) pepe ft fast fT fest os 8 | en Equivalent Input Noise | Rg— 1002 o Voltage £=100 Hz 15 nVAz 4 =1000 Hz 12 nV/VHZ PS in Equivalent input f= 100 Hz 0.01 0.01 0.01 pA/WHz o Noise Current f= 1000 Hz 0.01 0.01 0.01 pA/VHz u , | Gu ipucapactance | * tet | ls, | [el | ow wo | DC Electrical Characteristics (notes)

5 LF255/6/7

c LF155A/155, 3

4 LF156A/156, LF157A/157

LF255, ’ | LF356A/356 LF357A/387 g Parameter LF355A/355B | ue | LF256/356B ul LF257/357B Units kd re | tye _[ Max [typ [max| typ [ mex | typ [Max [typ | Max | Typ | Max | a suppycurent| 2 | 4 [avalos [7 [is [wl os | 7 {[s | 0 [m/s g e . a LF155/255/ | LF156/256, | LF156/256/ | LF157/257, | LF157/257/ g Symbol Conditions | 355/355B | LF356B | 356/356B | LF357B_| 357/957B | Units | | tye | Min [typ | win [typ | s SR Slew Rate LF155/6: Ay=1, 75 Vis | LF157: Ay=5 Wyus_| ft GBW | Gain Bandwidth MHz | @ Product ec te ___| Setting Time to 0.01% | (Note 7) a 6 OO en Equivalent Input Noise | Rg= 1009 2 Voltage =100 Hz 15 15 avAAz | > = 1000 Hz 12 12 nVAVHz | Qt in Equivalent Input f=100 Hz 0.01 0.01 0.01 pA/VHz 2 Current Noise f=1000 Hz 0.01 0.01 0.01 pA/VAz 5 Cn __|imputcapactance | Ts Ps 8 tJ . . $s Notes for Electrical Characteristics o Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by Tjwax, 8ja, and the ambient temperature, 8 Ta. The maximum available power dissipation at any temperature is Py= (Tmax —Ta)/0ja or the 25°C Pyyyax, whichever is less. a Note 2: Uniess otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. r Note 3: Uniess otherwise stated, these test conditions apply: a / LFISSA/6A/7A LF255//6/7 LFS5SA/6A/7A | LF355B/6B/7B | LF355//6/7 | > i LF155//6/7 3S | Supply Voltage, Vs | +15V<Vgs+20v | +15V<Vg<+20V | +15V<Vgs+18V | +15V<Vg+20V | Vg= +15V a | Ta TBBTCSTAS +128°C | —25°C<Tax +85°C | O'C<TaS+70°C | O'C<Tas+70°C | O'CsTas+70°C | | THicH +125°C +85°C +70°C +70C +70°C Pa | and Vos, Ip and log are measured at Voyy=0. a Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5uV/"C typically) for each mV of adjustment from its ~“N original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment. = Note 5: The input bias currents are junction leakage currents which approximately double for ‘every 10°C increase in the junction temperature, Ty. Due to limited a Production test time, the input bias currents measured are correlated to junction temperature. in normal operation the Junction temperature rises above the ambient a temperature as a result of internal power dissipation, Pd. T)=Ta+ 6jq Pd where 64 is the thermal resistance from junction to ambient. Use of a heat sink is 2 recommended if input bias current is to be kept to @ minimum. a | Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultanaously, in accordance with common practice. RY | Note 7: Settling time is defined here, for @ unity gain inverter connection using 2 kf resistors for the LF155/6. It is the time required for the error voltage (the g i ‘voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V ‘step input is applied to the inverter. For the LF157, > | ‘Ay= ~5, the feedback resistor from output to input is 2 kM and the output step is 10V (See Settling Time Test Circuit). a K} i Note 8: Refer to RETS155AX for LF155A, RETS155X for LF155, RETSF156AX for LF156A, RETS156X for LF156, RETS157A for LF157A and RETS157X for gs H LF157 military specifications. a q Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate o { ‘outside guaranteed timits. a : N a 3.27

a ‘8| Typical DC Performance Chi isti < Curves are for LF155, LF156 and LF157 Characteristics

2 Input Bias Current

5 _ aan ni Input Bias Current

5 To ime » Input Bias Current

B)oecoeeg tee Ace ry A gon Z “eo g) I:cess7 iba) tee a 3 Ms Fi VS 3 4 | oer coer aebapcony < a an] ae ace Ze 8) AE ee (PEC) 0 ERR Pe cas rewmnarnt cor * etweumaeco oe e us waruaran cnmosaooevacrseeen 5 « Voitage Swing Supply Current , Fi : ooo ‘ Supply Current 8 bit +H CT ; A i eeeeeecd i FERAG i LK s 3 eLLCOv 5 ( [| [ewe] ory A ee 8) corppero i Hoe i rere SEA EES et Cr B= 820 a) ERR) Sri 3 if 3 sur vo.rage on ‘amrverucen u

2 Negative Current Lit

z .* aan nt Limit .* cab Limit | inut Voltage Lt ove

8 Re] ee V

a, NS 5 A 7) LESS LGB Ge PPREE a : cl Bos H a B) coder = Eerie "PATH

8 Negative Common-Mode nae

2 Input Voltage Limit Open Loo;

3 “1 CLUE tm Pt oP Voltage Gain Output Voltage Swing Bl as 4, == * il | g E. 4 SS = fori 2 i = A 2 io gl Bn ~ 3: BS gz] op oo aaSee= eg 8 ge ATT 9 =e ee eed e) PA osue == mel Hi 8 2-H == S=== P A a 7 ZL TTT i] ‘SUPPLY VOLTAGE (:¥) ‘ a ot . UTPUT LOAD Ry (hk) 3-28

Typical AC Performance Characteristics a Gain Bandwidth Gain Bandwidth Normalized Slew Rate Ps us ‘COO ooo uN] |B EB” AL [etter conves roewnicat IN | 2 NE el Ty SC piercrmicoere 1 Pisa Eo] S e PN} f ENEEEE wpm g E : H ‘ ; 2 a PorNeeet] A tooo, ie i hb 3 iS : Coe : COS 3 «tp Sei a i a Ba | 2 Ta g ° COT ESS 2 COT NSO we pod & sCL TT TTT tt COC Ss OTT inn tt 3 secre 8 Os a8 68 WS WE TS eS 6 ew I as : s TEMPERATURE (¢) TEMPERATURE ("C) > TEMPERATURE (°C) runsseu0-a 5 a a a Output Impedance w Output Impedance w Output Impedance g tay Tato fay =e ee es etic = z ; >I 3 sul 2 w CS eT ow Se 8 3 eit ati Pa SF Sah Sra Pa aii ci casiais mea Pe H a awe cai cam 2 Gao 3 Hs aa ° Bae Beis ° pre aes eee: 4 iS sili Sati Sani att art He 3 Fi i i By Weg ati amavis rat ow CHT w HH td |S ra rT TT tte Pa nM lowe FREQUENCY (Hz) a ‘FREQUENCY (Hz) FREQUENCY (Hz) 3 runsees-1e | SF LF155 Small Signal Pulse LF 156 Small Signal Pulse Smal Signal Pulse Response, Ay= +1 Response, Ay= +1 Response, Ay= a z a g { : i 5 2 5 feceeheweef ewer es & jo—f—P—f} tf s > i i H : H 3 2 g ose Seer eee ee a Oa 8 & 2 8 —— 2 FA * 3 5 : aa \\ : A a i ca / 7 5 wa fu. [a 5 2 3 5 : 2 ml : é SN E | E 5 s 6 ) a ° TIME (0.5 pa/DIV) ‘TOME (0.5 ,a/DIV) TIME (0.1 /DIV) > TUN/se48-5 TUNVse46~6 rwsuer |B bul " no LF155 Large Signal Pulse LF156 Large Signal Pulse LF157 rarer Signa Pulse a Response, Ay= +1 Response, Ay= +1 Response, Ay = 3 | _— . fat ; \\ s to 5 a = oes ae ' = a 5 | a! g § 3 \\ = ! z | : S e foi tk s if 4 - 2 | \\ 3 5 ene Ne : - i : > 3 A i \\. : } Ll i = ia ae _ ia g = aan “7 = an ¥ 5 y a s Ss TIME 0 01) Te (OW) TE 05 01V) TU/Hs646-8 TUMis606-9 TUH/5646-10 3-29

a | Typical AC Performance Characteristics (continues) ° yp! = Open Loop Frequency ry Inverter Settling Time Inverter Settling Time i" Response ~ " S Sm OECTMES CORES 2) EF [ta [7 7a z, f = "CNET al & TW AT : Dy 3 yf Ate S| 4 Fi fil Pia an SN tol S| = o_o Ot gE, aif a S) og CUR 3 Ul 37 * COS a) & ris z § OAT ee NNT z, INN Eee a NN Fe ENO Al N 2 OCR || HH ECCT EERE 2 os NSAI En i Jeet nr ’ reer) +’ 10 a ’ 10 18 100 tk 10k 100K mh tom bf SETTLING TIME (us) SETTLING TIME Us) FREQUENCY (H2) es] a Fa Bode Pitot Bode Plot 1 » Bode Plot - w 100 s —— So 7 = ] 2 ‘ Ree Hi " ‘ Psat tron | : i REPT ves °

8 Sl rm : | T Nits IN se s pete Ht s

& east =p CN eg NT 2 a] gf TONE & = Soo & og CTT 8 & 3 5 os es Bg oe Ns BO } COC aE B) pace Nous PSE SONS bP ENN | “s A nw Bs CUNT “7 a pL ChNN 3 ~~ NTT ow Cro <1 " Conn 7% 8 x INU =U COO = 3 CO 8 iM ' . rs h " 1 . - $ FREQUENCY (tts) FREQUENCY (att) FREQUENCY (att) = Common-Mode Rejection

8 Ratio Power Supply Rejection Ratio Power Supply Rejection Ratio

S) EAA 2 LAI : RS ee = gw ~ 1 z* TY Fi KN] OS CONE CIS “SER B| Zo KA : ” KN POSS e} oot Le | LT dh \\ 7 Ss BE CTTINAD ELEN of SSN | 10 100 tk 10k 108k 1M 10 ) 100 tk kM 1 | 3 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) | wo N wu

2 Undistorted Output Voltage Equivalent input Noise Equivalent Input Noise

s a Swing @ Voltage a 1 Voltage (Expanded Scale) wo SS 2 | | w Ao an CT =| sf =| “Ae gts 6) 2 Cmcnmm i 2 oe en ee | eG a 2 = Hoe ae; a a Si) 2 HA cts or tt ao Ce §* 3» ia oo = COM NOC VA, | Td = ESPs mrt ee : bal eee “Wr TT £ Come IN Sin Bo HTT 2 oie ANN: gg - | Comic Fi 5 | Coco tihnerit 2.0 Tw 7] tote 1” ry 2°,» wom om z 1k 1 FREQUENCY (H:) FREQUENCY (Ht) “ FREQUENCY (#2) Tunrsede-11 3-30

g © Mee a | | CS " (g A 5 (— 2 a a P| 5 a ra o k ” a oo LE. a Ean é a rH a a ie, AP g g S cp rat nN CH. oo $ CF EET ELLY 2 "C = 3 pF in LF157 series. Tunssess-13 | Ey Connection Diagrams (top views) 5 eo ! Metal Can Package (H) Dual-in-Line Package (J) Duabin-Line Package (M and N) EA “ g : ‘0. 1 14 ance Pane La i rs 1 1 | wer Yy|> (5) our paLance — ra “ . 5 weet G) (5) savance 5 10 wut ourrut N | 6) input OUTPUT > ' r vt 5 BALANCE v4 P eavance a | TL/H/5646-14 We 7 8 NC x | Order Number TLH/ene-29 3 | LF1S5AH, LF156AH, LF1S7AH, TUnvsese-20 Order Number S | teeth LE eet LE ISTH. Order Number LF355M, LF3S6M, LF57M, a | cai Leseentit eesti LF165J, LF156J, LF157J, LF356BM, LF355BN, LF356BN, & | Heart LESSRAN, LEOETAM, LF356J, LF366J, LF357J, LF357BN, LF355N, LF356N or SS | vipoeett tracer 1 ee LF355BJ, LF356BJ or LF357BJ LF357N PS N | See NS P Number H0sc ‘See NS Package Number J14A SeeNS racaeoe number > a | a 331

a i

8 Application Hints

| the 1F155/6/7 series are op amps with JFET input de- polarity or that the unit is not inadvertently installed back- & | _ vices. These JFETs have large reverse breakdown voltages wards in a socket as an unlimited current surge through the rn from gate to source and drain eliminating the need for resulting forward diode within the IC could cause fusing of {8 | clamps across the inputs. Therefore large differential input the internal conductors and result in a destroyed unit. | voltages can easily be accomodated without a large in- Because these amplifiers are JFET rather than MOSFET s crease in input current Tre ry voltages. Howe input vor input op amps they do not require special handling. age is independent of the supp! jes. However, ni er Be, 6 ' All of the bias currents in these amplifiers are set by FET g ne input voltages should De alowed fo excooa ne neo current sources. The drain currents for the amplifiers are a} te supely as doatevodunt large cu therefore essentially independent of supply voltage. | Exceeding the negativ monemode limit on ether input As with most amplifiers, care should be taken with lead S xe ing negative common-mode on either inp dress, component placement and supply decoupling in or- =- will force the output to a high state, potentially causing a der to ensure stability, For example, resistors from the out- rT | of phase to the output. Exceeding the negative or su lity. ple, 5 reversal Pie init on both fonts will fore th if put to an input should be placed with the body close to the id cutput to va nigh stale. in neither nee dooe a late ot input to minimize “pickup” and maximize the frequency of | since raising the input back within the common-mode range the feedback pole by minimizing the capacitance from the ~ * . a input to ground. a again puts the input stage and thus the amplifier in a normal S| operating mode. A feedback pole is created when the feedback around any 3 - “ _ . amplifier is resistive. The parallel resistance and capaci- & | Exceeding the positive common-mode limit on a single input tance from the input of the device (usually the inverting in- << | will not change the phase of the output however, if both d set the fr of the pole. | $ | _ inputs exceed the limit, the output of the amplifier will be Put) to ac ground set the frequency of the pole. In many © | forced toa high state,” instances the frequency of this pole is much greater than ber lorced to a high state. - - the expected 3 dB frequency of the closed toop gain and S| These amplifiers will operate with the common-mode input consequently there is negligible effect on stability margin. {8 | _ voltage equal to the positive supply. In fact, the common- However, if the feedback pole is less than approximately six © | mode voltage can exceed the positive supply by approxi- times the expected 3 dB frequency a lead capacitor should <i | mately 100 mv independent of supply voltage and over the be placed from the output to the input of the op amp. The < | _ full operating temperature range. The positive supply can value of the added capacitor should be such that the RC 4G | _ therefore be used as a reference on an input as, for exam- time constant of this capacitor and the resistance it parallels i | _ ple, in a supply current monitor and/or limiter. is greater than or equal to the original feedback pole time ~ Precautions should be taken to ensure that the power sup- constant. Ps ply for the integrated circuit never becomes reversed in | Typical Circuit Connections u 3 Vos Adjustment Driving Capacitive Loads LF157. A Large Power BW Amplifier w i wo ¥ g { ‘ ™ ; LC wo oa 9 9 Ss wo B La 1 Pd Me = 4) " Ovo a | ct re oa) Ww 3 9 g ° * al ™ ae aa) T 1 L woe Ss 7 sic | & : Lid S$ * Vos is adjusted with a 25k potenti- TUH/8846-15 < ‘ometer *LF155/6 R=5k For distortion < 1% and @ 20 Vp-p Vout swing, Ea) * The potentiometer wiper is con- LFIS7 R=1.25k power bandwidth is: 500 kHz. = nected to V+ LB | — «For potentiometers with tempera- Dus to a unique output stage design, these am- rr) ture coefficient of 100 ppm/*C or plifiers have the ability ta drive large capacitive iL less the additional drift with adjust loads and still maintain stability. Cyayax) = 0.01 a) is = 0.5 pV/°C/mV of adjustment BF. © Typical overall drift: § wV/°C £(0.5 Overshoot < 20% EV/°C/mvV of adj.) Settling time (t,) = 5 ps 332

r A . z Typical Applications a g Settling Time Test Circult a a 241K ? ny a.0x = mala | | 3 ° o ene "Tr ; © veer a tt as >" ” * Setting time is tested with the LF155/6 connected £ rat + + * as unity gain inverter and LF187 connected for g v0 Ay= 5 g suman x © FET used to isolate the probe capacitance 3 © Output = 10V step a o« © Ay = ~5 for LFI57 Ss oscrsescore Leper Ayo “Sor o © 4 n x = = = - TUH/S646-16 g z be Large Signal inverter Output, Vour (from Settling Time Circuit) no a L355 LF356 LF387 5 y ey s 2| 2 { \\ ’ 2 / \\ 3 S a/v ‘alt ‘adv La TLIH/5646-17 TLH/5646-18 Tunrseae-19 | a Low Drift Adjustable Voltage Reference ia © A Vour/AT= 0.002% /°C 8 pete ‘* All resistors and potentiometers should be wire-wound 2 " + P2: Vour adjust wo ™ © Use LF185 for A] 9 * Low ip 3 © Vour= 10 = Low drift g a CE ann 5 a tome o im a na = 300 o a TLIH/8646-20 3.33

a S

3 Typical Applications (continues)

< Fast Logarithmic Converter 8 S Pd =O Mee ~ a 3 ° =e 4 mal ‘© Dynamic range: 100 HA < | < 1 mA (5 dec- r w ades), [Vol = 1V/decade ra a aN] ‘© Transient response: 3 1s for Alj= 1 decade Ps “oN = ‘ ‘© C1, C2, R2, R3: added dynamic compensation = B © Vog adjust the LF156 to minimize quiescent error < £ " Fir: Tol Labs type O81 + 0.9%/*C oy atv a

5 TL/H/5848-21

i =f 4 2] inv [—P] = og vi re = = a Wout! = [1 + % q Invi [a -| log Vi an R2 = 15.7k, Rr = 1k, 0.3%/*C (for temperature compensation) [oy

8 Precision Current Monitor

g < 4 8 — w re © Vo=5 R1/R2 (V/mA of Is) ~ vo L sd T © Rt, R2, 3: 0.1% resistors 3 - | | = | «thors 2 ®= Common-mode range to supply range = = Low Ip $ + = Low Vos iM meal = Low Supply Current a 5 wo s " Pr bad ‘TUH/5648-31 i 8-Bit D/A Converter with Symmetrical Offset Binary Operation 8 4 < BERBEEBRS RG a a 4 3 + Tan [* 2 Ww nN 8 = bar av ‘TL/H/5646-32 z #1, R2 should be matched within +0.05% ra} ‘© Full-scale responee time: Sus a +9.920/ 1 1 #4 1 #14 = 1 1 = 1 | Positive Full-Scale 4 +0040} 1 0 0 0 0 0 0 0| (+)Zero-Scale -0.040)0 1°74 4 4 4 4 1 (—) Zero-Scale -9.020;0 0 0 0 0 0 O_O | Negative Full-Scale 3-34

c . un Typical Applications (continued) a a Wide BW Low Noise, Low Drift Amplifier Isolating Large Capacitive Loads = a i om a © Vour > “7 KA taro Ms ey w ‘ ” 2 < oy 1. ° ‘ ° ty the g ects | a he & L é 2 == 3 = 4 a v '* Overshoot 6% Tunisess-22 | © Power BW: fax = <SC- = 240 kHz *t 10ns yg 2mVp ‘When driving large G,, the Vour slew rate determined by C_ and a ‘© Parasitic input capacitance C1 = (3 pF for LF155, LF156 and LF157 plus louT(maxy: a any additional layout capacitance) interacts with feedback elements and AVour _ lour _ 0.02 re ‘creates undesirable high frequency pole. To compensate add C2 such TET Gog W/E = 0.04 V/ps (wth Cy shown) La ‘that: R2C2= R1C1. _ Low Drift Peak Detector g Boosting the LF156 with a Current Amplifier mm > 8 a ov so epy He g ° a o— or 6 S 1 ar ad Tr iw c a md Sh, - Tunvsess | = = Oo xe a + -iv $ ae * By adding D1 and Ry, Vp1=0 during hold mode. Leakage of D2 provided a Tt by feedback path through Ry. o © loutaway = 150 mA (wil drive R= 1000) . Leakage of circuit is essentially 1b (LF155, LF156) plus capacitor leakage Fs * NE = sea Wns (th showny * Diode 03 clamps Vout (At) to Vin~Vpa to improve speed and to mit | @S reverse bias of D2. a ‘* No additional phase shift added by the current amplifier '* Maximum input frequency should be << YamrAyCpg where Cop is the 4 ‘shunt capacitance of D2. c

3 Decades VCO =

9 Non-Inverting Unity Gain Operation for LF157 a

N x ta mice = vm, R2 + Rg ry my ‘ n-——8 3 v0 A 4 a ™ ok S vioo) = 1 ‘ im M La : ' © a - | 44 * $ . ae : > ay ~ Inverting Unity Gain for LF157 = od te o ~ Ea mm oy te ¢ a {5 MHz) . Qn ° Ri=— = TLH/5846-24 Ayog) = —1 « Vo (R8+R7) t Bue REA G 05VCS80¥, 10Hest< 10 KH = tea gp = SMHz it, 4 matched. Linearty 0.1% over 2 decades. TUH/5646-25 3-35

a $8 High Impedance, Low Drift instrumentation Amplifier a) aw 5 9 2 + ods : a ‘ a 83 | Re w N a ) 5 9 S Rad = © Vour = 4 ‘ L d a ‘ =" a a 8 f oO a g nana £ ) aw

5 TUn/s640-26

8 . Vour ~ 52 [282 + 1] av.v~ + av < Vin common-mode < V+ bar '* System Vos adjusted via A2 Vos adjust 2 © Trim R3 to boost up CMRA to 120 dB. Instrumentation amplifier 8 resistor array recommended for best accuracy and lowest drift Pr) wm u a a Py Py w rey s i Py a pre a wo wo S x B rr) u a 3-36

c n Typical Applications (continued) a a Fast Sample and Hold = a a gg a na nN a a 9 S a 9 1 1 3 mod \\ g ' L—\\me oe Vsrersurents aR t ‘Lena > om ; © vour S$ a — (s a 3 ‘our % o vmo E Tr d g = “ rc | = inv a tw TUH/s646-23 3 * Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible) = '* Acquisition time Ta, estimated by: $ % t The [Royo =) provided that: Pd Sr rc Vin Ch a Vin < 29S; Ron Ch and Ta > SP, Roy is of SWI fouriman, $ , ty = YING g W inequality not satisfied: Ta = >A Pa * LF156 develops full S, output capability for Vin 1V 3 '* Addition of SW2 improves accuracy by putting the voitage drop across SW1 inside the feedback loop roc) ‘* Overall accuracy of system determined by the accuracy of both amplifiers, At and A2 F un rey High Accuracy Sampie and Hold Ey ez Pry ok $ { = - the 9 n «4 = oa der Ei SWITCHES rT =

2 UFtt333 1 Ovour a

‘ ae, > A 4 0 % r IT 2 RY = -v Nn : y atv S © By closing the loop through A2, the Vour accuracy will be determined uniquely by A1 § No Vos adjust required for A2. x ‘© Ta can be estimated by same considerations as previously but, because of the added S Propagation delay in the feedback loop (A2) the overshoot is not negligible. N ‘© Overall system slower than fast sample and hold > ‘© Ri, Co: additional compensation & © Use LF156 for a = Fast setting time = Low Vos 3-37

8 Typical Applications (Continued)

Ss + By adding positive feedback (R2) xs =) Q increases to 40 ba Cy 5 fap= 100 kHz 5 aa wis Z| wo " ‘en = 108 a ip " * Clean layout recommended i A+ ue © Vour ‘© Response to a 1 Vp-p tone burst: 2 ue oS = a 300 ps c - Cra s m a av = cS 8 > w= gS < TL/H/5646-28 Ps) oO a s High Q Notch Filter Ps) oO a Py ? #21 = R= 10M 8 2C = C1 = 300pF ir ‘* Capacitors should be matched to obtain high Q

2 OVour ‘“tnotoH = 120 Hz, notch = —§5 dB, Q >

8 © Use LF155 for = ” ) = Low I, s * Low supply current 4 a 5 q a Fr) Ps c ¢ TLH/5646-34 Pr] S Py id ig a Ss | wo | 16 ou a wo wo x w w Py u a 3-38

Product Information

LF356BH specifications and overview.

Summary

Series Monolithic JFET Input Operational Amplifiers

Description

Series Monolithic JFET Input Operational Amplifiers

Source title LF356BH Datasheet(PDF) - National Semiconductor (TI)

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