LF253 STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 15

Technical content

Features

■ Low power consumption ■ Wide common-mode (up to VCC +) and differential voltage range ■ Low input bias and offset current ■ Output short-circuit protection ■ High input impedance JFET input stage ■ Internal frequency compensation ■ Latch up free operation ■ High slew rate 16 V/µs (typical)

Description

These circuits are high speed JFET input dual operational amplifiers incorporating well matched, high voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. N DIP8 (Plastic package) D SO-8 (Plastic micro package) Pin connections (top view) /C49 /C50 /C51 /C52 /C53 /C54 /C55 /C56 /C45 /C43 /C45 /C43 1 - Output1 2 - Inverting input 1 3 - Non-inverting input 1 4 - VCC 5 - Non-inverting input 2 6 - Inverting input 2 7 - Output 2 8 - VCC

1 Schematics

Figure 1. Schematic diagram (each amplifier)

2 Absolute maximum ratings and operating conditions

Table 1. Absolute maximum ratings

  1. All voltage values, except differential vo ltage, are with respect to the zero reference level (ground) of the supply voltages
  2. The magnitude of the input voltage must never exceed the magnit ude of the supply voltage or 15 volts, whichever is less.
  3. Differential voltages are the non-inverting input term inal with respect to the inverting input terminal.
  4. Short-circuits can c ause excessive heating and destructive dissipation. Values are typical.
  5. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure
  6. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor

between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.

  1. Machine model: a 200 pF capacitor is charged to the specifie d voltage, then discharged directly between two pins of the

while the other pins are floating.

  1. Charged device model: all pins and the pac kage are charged together to the specified voltage and then discharged directly

to the ground through only one pin. This is done for all pins. Table 2. Operating conditions

3 Electrical characteristics

Table 3. Electrical characteristics at V CC = ±15 V, Tamb = +25°C (unless otherwise specified)

200 V/mV

  1. The input bias currents are junction l eakage currents which approximately double for every 10°C increase in the junction

4 Parameter measurement information

Figure 19. Voltage follower Figure 20. Gain of 10 inverting amplifier

5 Typical application

Figure 21. Quadruple oscillator

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

6.1 DIP8 package information

Figure 22. DIP8 package mechanical drawing Table 4. DIP8 package mechanical data

6.2 SO-8 package information

Figure 23. SO-8 package mechanical drawing Table 5. SO-8 package mechanical data

7 Ordering information

Table 6. Order codes

8 Revision history

Table 7. Document revision history 01-Mar-2001 1 Initial release. and LF353D proposed in tube packing.