LF347N

LF347B TI | Alldatasheet

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IN – IN + OUT Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LF347,LF347B SLOS013C –MARCH 1987–REVISED MARCH 2016 LF347,LF347BJFET-InputQuadOperationalAmplifiers

1 Features

1• Low Input Bias Current: 50 pA Typical

• Low Input Noise Current: 0.01 pA/√Hz Typical
• Low Total Harmonic Distortion
• Low Supply Current: 8 mA Typical
• Gain Bandwidth: 3 MHz Typical
• High Slew Rate: 13 V/ms Typical

2 Applications

• Motor Integrated Systems: UPS
• Drives and Control Solutions: AC Inverters and VF Drives
• Renewables: Solar Inverters
• Pro Audio Mixers
• Oscilloscopes

3 Description

The LF347 and LF347B devices are low-cost, high- speed, JFET-input operational amplifiers. They require low supply current yet maintain a large gain- bandwidth product and a fast slew rate. In addition, their matched high-voltage JFET inputs provide very low input bias and offset current. The LF347 and LF347B can be used in applications such as high-speed integrators, digital-to-analog converters, sample-and-hold circuits, and many other circuits. The LF347 and LF347B devices are characterized for operation from 0°C to 70°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LF347D, LF347BD SOIC (14) 8.65 mm × 3.91 mm LF347N, LF347BN PDIP (14) 19.30 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Symbol (Each Amplifier)

LF347,LF347B SLOS013C –MARCH 1987–REVISED MARCH 2016 www.ti.com Product Folder Links: LF347 LF347B Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated Table of Contents

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (August 1994) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

21IN– 13 4IN– 31IN+ 12 4IN+ 4VCC+ 11 V CC– 52IN+ 10 3IN+ 62IN– 9 3IN– 72OUT 8 3OUT LF347,LF347B www.ti.com SLOS013C –MARCH 1987–REVISED MARCH 2016 Product Folder Links: LF347 LF347B Submit Documentation FeedbackCopyright © 1987–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

NO. NAME 1 1OUT O Output pin of amplifier 1 2 1IN– I Inverting input pin of amplifier 1 3 1IN+ I Noninverting input pin of amplifier 1

4 VCC+ — Positive Supply

5 2IN+ I Noninverting input pin of amplifier 2 6 2IN– I Inverting input pin of amplifier 2 7 2OUT O Output pin of amplifier 2 8 3OUT O Output pin of amplifier 3 9 3IN– I Inverting input pin of amplifier 3 10 3IN+ I Noninverting input pin of amplifier 3

11 VCC– — Negative Supply

12 4IN+ I Noninverting input pin of amplifier 4 13 4IN– I Inverting input pin of amplifier 4 14 4OUT O Output pin of amplifier 4

LF347,LF347B SLOS013C –MARCH 1987–REVISED MARCH 2016 www.ti.com Product Folder Links: LF347 LF347B Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Unless otherwise specified, the absolute maximum negative input voltage is equal to the negative power supply voltage.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC+ Supply voltage 18 V VCC– Supply voltage –18 V VID Differential input voltage –30 30 V VI Input voltage(2) –15 15 V Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C TJ Operating virtual junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA free-air temperature 0 70 °C VCC+ Supply voltage 3.5 18 V VCC– Supply voltage –3.5 –18 V VCM Common-mode voltage VCC– + 4 VCC+ – 4 V TA Operating temperature 0 70 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) LF347, LF347B UNITD (SOIC) N (PDIP)

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 74.4 42.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.5 29.2 °C/W RθJB Junction-to-board thermal resistance 28.9 22.6 °C/W ψJT Junction-to-top characterization parameter 3.7 13.5 °C/W ψJB Junction-to-board characterization parameter 28.6 22.5 °C/W

LF347,LF347B www.ti.com SLOS013C –MARCH 1987–REVISED MARCH 2016 Product Folder Links: LF347 LF347B Submit Documentation FeedbackCopyright © 1987–2016, Texas Instruments Incorporated (1) Full range is 0°C to 70°C. (2) Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive. Pulse techniques must be used that will maintain the junction temperatures as close to the ambient temperature as possible. (3) Supply-voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously.

6.5 Electrical Characteristics: LF347

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VIC = 0, RS = 10 kΩ 25°C 5 10 mV Full range(1) 13 αVIO Average temperature coefficient of input offset voltage VIC = 0, RS = 10 kΩ 18 µV/°C IIO Input offset current(2) VIC = 0 25°C 25 100 pA 70°C 4 nA IIB Input bias current(2) VIC = 0 25°C 50 200 pA 70°C 8 nA VICR Common-mode input voltage Lower limit of range –11 –12 V Upper limit of range 11 15 VOM Maximum peak output voltage swing RL = 10 kΩ ±12 ±13.5 V AVD Large signal differential voltage VO = ±10 V, RL = 2 kΩ 25°C 25 100 V/mV Full range 15 ri Input resistance TA = 25°C 1012 Ω CMRR Common-mode rejection ratio RS ≤ 2 kΩ 70 100 dB kSVR Supply-voltage rejection ratio See (3) 70 100 dB ICC Supply current 8 11 mA (1) Full range is 0°C to 70°C. (2) Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive. Pulse techniques must be used that will maintain the junction temperatures as close to the ambient temperature as possible. (3) Supply-voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously.

6.6 Electrical Characteristics: LF347B

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VIC = 0, RS = 10 kΩ 25°C 3 5 mV Full range(1) 7 αVIO Average temperature coefficient of input offset voltage VIC = 0, RS = 10 kΩ 18 µV/°C IIO Input offset current(2) VIC = 0 25°C 25 100 pA 70°C 4 nA IIB Input bias current(2) VIC = 0 25°C 50 200 pA 70°C 8 nA VICR Common-mode input voltage Lower limit of range –11 –12 V Upper limit of range 11 15 VOM Maximum peak output voltage swing RL = 10 kΩ ±12 ±13.5 V AVD Large signal differential voltage VO = ±10 V, RL = 2 kΩ 25°C 50 100 V/mV Full range 25 ri Input resistance TA = 25°C 1012 Ω CMRR Common-mode rejection ratio RS ≤ 2 kΩ 80 100 dB kSVR Supply-voltage rejection ratio See (3) 80 100 dB ICC Supply current 8 11 mA

6.7 Switching Characteristics

6.8 Typical Characteristics

Figure 1. Input Bias Current vs Free-Air Temperature Figure 2. Maximum Peak Output Voltage vs Frequency Figure 3. Maximum Peak Output Voltage vs Load Figure 4. Large-Signal Differential Voltage Amplification

7 Parameter Measurement Information

Figure 5. Unity-Gain Amplifier

LF347,LF347B SLOS013C –MARCH 1987–REVISED MARCH 2016 www.ti.com Product Folder Links: LF347 LF347B Submit Documentation Feedback Copyright © 1987–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LF347 is a JFET-input operational amplifier with low input bias and offset currents and fast slew rate. Each amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single monolithic chip. The output is protected against shorts due to the resistive 200-Ω output impedance.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. These devices have a 13-V/μs slew rate.

8.4 Device Functional Modes

These devices are powered on when the supply is connected. This device can be operated as a single-supply operational amplifier or dual-supply amplifier depending on the application.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

greater. Output resistance is 200 Ω to protect the device from accidental shorts.

9.2 Typical Application

Figure 6. Inverting Amplifier

9.2.1 Design Requirements

accommodate this application.

9.2.2 Detailed Design Procedure

current. For this example, choose 10 kΩ for RI which means 36 kΩ is used for R, as determined by Equation 3.

9.2.3 Application Curve

Figure 7. Input and Output Voltages of the Inverting Amplifier

10 Power Supply Recommendations

dual-supply can permanently damage the device (see Absolute Maximum Ratings).

11 Layout

11.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see the chapter extract, Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting

input minimizes parasitic capacitance, as shown in Layout Example.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 8. Operational Amplifier Board Layout for Noninverting Configuration Figure 9. Operational Amplifier Schematic for Noninverting Configuration

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 1. Related Links

12.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LF347BD Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 LF347B LF347BDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LF347B LF347BDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LF347B LF347BN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LF347BN LF347BN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LF347BN LF347D Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 LF347 LF347DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LF347 LF347DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LF347 LF347DRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI 0 to 70 LF347N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LF347N LF347N.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LF347N LF347NE4 Active Production PDIP (N) | 14 25 | TUBE - Call TI Call TI 0 to 70 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LF347BDR SOIC D 14 2500 340.5 336.1 32.0 LF347BDR SOIC D 14 2500 356.0 356.0 35.0 LF347DR SOIC D 14 2500 356.0 356.0 35.0 LF347DR SOIC D 14 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LF347BN N PDIP 14 25 506 13.97 11230 4.32 LF347BN N PDIP 14 25 506 13.97 11230 4.32 LF347BN.A N PDIP 14 25 506 13.97 11230 4.32 LF347BN.A N PDIP 14 25 506 13.97 11230 4.32 LF347N N PDIP 14 25 506 13.97 11230 4.32 LF347N N PDIP 14 25 506 13.97 11230 4.32 LF347N.A N PDIP 14 25 506 13.97 11230 4.32 LF347N.A N PDIP 14 25 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

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