LF298M/NOPB.B

LF198-N TI | Alldatasheet

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Technical content

Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 LFx98xMonolithicSample-and-HoldCircuits

1 Features

1• Operates from ±5-V to ±18-V Supplies

• Less than 10-μs Acquisition Time
• Logic Input Compatible With TTL, PMOS, CMOS
• 0.5-mV Typical Hold Step at Ch = 0.01 µF
• Low Input Offset
• 0.002% Gain Accuracy
• Low Output Noise in Hold Mode
• Input Characteristics Do Not Change During Hold Mode
• High Supply Rejection Ratio in Sample or Hold
• Wide Bandwidth
• Space Qualified, JM38510

2 Applications

• Ramp Generators With Variable Reset Level
• Integrators With Programmable Reset Level
• Synchronous Correlators
• 2-Channel Switches
• DC and AC Zeroing
• Staircase Generators

3 Description

The LFx98x devices are monolithic sample-and-hold circuits that use BI-FET technology to obtain ultrahigh DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity-gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the LFx98x to be included inside the feedback loop of 1-MHz operational amplifiers without having stability problems. Input impedance of 1010 Ω allows high-source impedances to be used without degrading accuracy. P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1-µF hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design ensures no feedthrough from input to output in the hold mode, even for input signals equal to the supply voltages. Logic inputs on the LFx98x are fully differential with low input current, allowing for direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4 V. The LFx98x will operate from ±5-V to ±18-V supplies. An A version is available with tightened electrical specifications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LF298, LF398-N SOIC (14) 8.65 mm × 3.91 mm LFx98x TO-99 (8) 9.08 mm × 9.08 mm LF398-N PDIP (8) 9.81 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Connection Acquisition Time

LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 www.ti.com Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation Feedback Copyright © 2000–2018, Texas Instruments Incorporated Table of Contents 6.7 Electrical Characteristics, LF398A-N (OBSOLETE) . 8

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (October 2015) to Revision C Page

• Separated Electrical Characteristics into four tables: LF198-N and LF298; LF198A-N; LF398-N; and LF398A-N Changes from Revision A (July 2000) to Revision B Page
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

LF198-N,LF298,LF398-N LF198A-N,LF398A-N www.ti.com SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation FeedbackCopyright © 2000–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

A military RETS electrical test specification is available on request. The LF198-N may also be procured to Standard Military Drawing #5962-8760801GA or to MIL-STD-38510 part ID JM38510/12501SGA. (1) P = Power, G = Ground, I = Input, O = Output, A = Analog Pin Functions PIN TYPE(1) DESCRIPTION NAME LF298, LF398-N LFx98x LF398-N SOIC-14 TO-99 PDIP-8 V+ 12 1 1 P Positive supply OFFSET ADJUST 14 2 2 A DC offset compensation pin INPUT 1 3 3 A Analog Input V– 3 4 4 P Negative supply OUTPUT 7 5 5 O Output Ch 8 6 6 A Hold capacitor LOGIC REFERENCE 10 7 7 I Reference for LOGIC input LOGIC 11 8 8 I Logic input for Sample and Hold modes NC 2, 4, 5, 6, 9, 13 — — NA No connect

LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 www.ti.com Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation Feedback Copyright © 2000–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. (3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA) / RθJA, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum junction temperature, TJMAX, for the LF198-N and LF198A-N is 150°C; for the LF298, 115°C; and for the LF398-N and LF398A-N, 100°C. (4) Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2 V below the positive supply and 3 V above the negative supply.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Supply voltage ±18 V Power dissipation (Package limitation, see (3)) 500 mW Operating ambient temperature LF198-N, LF198A-N –55 125 °C LF298 –25 85 °C LF398-N, LF398A-N 0 70 °C Input voltage ±18 V Logic-to-logic reference differential voltage (see (4)) 7 −30 V Output short circuit duration Indefinite Hold capacitor short circuit duration 10 sec Lead temperature H package (soldering, 10 sec.) 260 °C N package (soldering, 10 sec.) 260 °C M package: vapor phase (60 sec.) 215 °C Infrared (15 sec.) 220 °C Storage temperature, Tstg –65 150 °C

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage ±15 V TJ Ambient temperature LF198-N, LF198A-N –55 125 °CLF298 –25 85 LF398-N, LF398A-N 0 70 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Board mount in 400 LF/min air flow.

6.3 Thermal Information

THERMAL METRIC(1) LF398-N LF298, LF398-N LFx98x UNITP (PDIP) D (SOIC) LMC (TO-99)

8 PINS 14 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 48.9 80.6 85(2) °C/W RθJC(top) Junction-to-case (top) thermal resistance 37.3 38.1 20 °C/W RθJB Junction-to-board thermal resistance 26.2 35.4 — °C/W ψJT Junction-to-top characterization parameter 14.3 5.8 — °C/W ψJB Junction-to-board characterization parameter 26.0 35.1 — °C/W

LF198-N,LF298,LF398-N LF198A-N,LF398A-N www.ti.com SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation FeedbackCopyright © 2000–2018, Texas Instruments Incorporated (1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V. (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. (3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range.

6.4 Electrical Characteristics, LF198-N and LF298

The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input offset voltage(1) TJ = 25°C 1 3 mV Full temperature range 5 mV Input bias current(1) TJ = 25°C 5 25 nA Full temperature range 75 nA Input impedance TJ = 25°C 10 GΩ Gain error TJ = 25°C, RL = 10 k 0.002% 0.005% Full temperature range 0.02% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 96 dB Output impedance TJ = 25°C, “HOLD”mode 0.5 2 Ω Full temperature range 4 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 0.5 2 mV Supply current(1) TJ ≥ 25°C 4.5 5.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C, hold mode(3) 30 100 pA Acquisition time to 0.1% ΔVOUT = 10 V, Ch = 1000 pF 4 µs CH = 0.01 µF 20 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 80 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V

LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 www.ti.com Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation Feedback Copyright © 2000–2018, Texas Instruments Incorporated (1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V. (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. (3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range.

6.5 Electrical Characteristics, LF198A-N

The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input offset voltage(1) TJ = 25°C 1 1 mV Full temperature range 2 mV Input bias current(1) TJ = 25°C 5 25 nA Full temperature range 75 nA Input impedance TJ = 25°C 10 GΩ Gain error TJ = 25°C, RL = 10 k 0.002% 0.005% Full temperature range 0.01% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 96 dB Output impedance TJ = 25°C, “HOLD”mode 0.5 1 Ω Full temperature range 4 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 0.5 1 mV Supply current(1) TJ ≥ 25°C 4.5 5.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C, hold mode(3) 30 100 pA Acquisition time to 0.1% ΔVOUT = 10 V, Ch = 1000 pF 4 6 µs CH = 0.01 µF 20 25 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 90 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V

LF198-N,LF298,LF398-N LF198A-N,LF398A-N www.ti.com SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation FeedbackCopyright © 2000–2018, Texas Instruments Incorporated (1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V. (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. (3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range.

6.6 Electrical Characteristics, LF398-N

The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input offset voltage(1) TJ = 25°C 2 7 mV Full temperature range 10 mV Input bias current(1) TJ = 25°C 10 50 nA Full temperature range 100 nA Input impedance TJ = 25°C 10 GΩ Gain error TJ = 25°C, RL = 10 k 0.004% 0.01% Full temperature range 0.02% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 80 90 dB Output impedance TJ = 25°C, “HOLD”mode 0.5 4 Ω Full temperature range 6 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 1 2.5 mV Supply current(1) TJ ≥ 25°C 4.5 6.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C, hold mode(3) 30 200 pA Acquisition time to 0.1% ΔVOUT = 10 V, Ch = 1000 pF 4 µs CH = 0.01 µF 20 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 80 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V

LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 www.ti.com Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation Feedback Copyright © 2000–2018, Texas Instruments Incorporated (1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V. (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. (3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range.

6.7 Electrical Characteristics, LF398A-N (OBSOLETE)

The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input offset voltage(1) TJ = 25°C 2 2 mV Full temperature range 3 mV Input bias current(1) TJ = 25°C 10 25 nA Full temperature range 50 nA Input impedance TJ = 25°C 10 GΩ Gain error TJ = 25°C, RL = 10 k 0.004% 0.005% Full temperature range 0.01% Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 90 dB Output impedance TJ = 25°C, “HOLD”mode 0.5 1 Ω Full temperature range 6 Ω HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 1 1 mV Supply current(1) TJ ≥ 25°C 4.5 6.5 mA Logic and logic reference input current TJ = 25°C 2 10 µA Leakage current into hold capacitor(1) TJ = 25°C, hold mode(3) 30 100 pA Acquisition time to 0.1% ΔVOUT = 10 V, Ch = 1000 pF 4 6 µs CH = 0.01 µF 20 25 µs Hold capacitor charging current VIN – VOUT = 2 V 5 mA Supply voltage rejection ratio VOUT = 0 90 110 dB Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V

6.8 Typical Characteristics

Figure 1. Aperture Time Figure 2. Dielectric Absorption Error in Hold Capacitor Figure 3. Dynamic Sampling Error Figure 4. Output Droop Rate Figure 5. Hold Step Figure 6. Hold Settling Time

7 Parameter Measurement Information

7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V

Figure 18. Sample When Logic High With TTL and CMOS Biasing Figure 19. Sample When Logic Low With TTL and CMOS Biasing

7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V

Figure 20. Sample When Logic High With CMOS Biasing

Figure 21. Sample When Logic Low With CMOS Biasing

7.3 Operational Amplifier Drive

Figure 22. Sample When Logic High With Operational Amplifier Biasing Figure 23. Sample When Logic Low With Operational Amplifier Biasing

LF198-N,LF298,LF398-N LF198A-N,LF398A-N SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 www.ti.com Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation Feedback Copyright © 2000–2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LFx98x devices are monolithic sample-and-hold circuits that utilize BI-FET technology to obtain ultrahigh DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity-gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198-N to be included inside the feedback loop of 1-MHz operational amplifier without having stability problems. Input impedance of 1010 Ω allows high-source impedances to be used without degrading accuracy.

8.2 Functional Block Diagram

8.3 Feature Description

The LFx98x OUTPUT tracks the INPUT signal by charging and discharging the hold capacitor. The OUTPUT can be held at any given time by pulling the LOGIC input low relative to the LOGIC REFERENCE voltage and resume sampling when LOGIC returns high. Additionally, the OFFSET pin can be used to zero the offset voltage present at the INPUT.

8.4 Device Functional Modes

The LFx98x devices have a sample mode and hold mode controlled by the LOGIC voltage relative to the LOGIC REFERENCE voltage. The device is in sample mode when the LOGIC input is pulled high relative to the LOGIC REFERENCE voltage and in hold mode when the LOGIC input is pulled low relative to the LOGIC REFERENCE. In sample mode, the output is tracking the input signal by charging and discharging the hold capacitor. Smaller values of hold capacitance will allow the output to track faster signals. In hold mode the input signal is disconnected from the signal path and the output retains the value on the hold capacitor. Larger values of capacitance will have a smaller droop rate as shown in Figure 4.

LF198-N,LF298,LF398-N LF198A-N,LF398A-N www.ti.com SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation FeedbackCopyright © 2000–2018, Texas Instruments Incorporated

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Hold Capacitor

Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size and cost may also become important for larger values. Use of the curves included with this data sheet should be helpful in selecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast signals, the capacitor drive currents may cause a significant temperature rise in the LF198-N. A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A mylar cap, for instance, may sag back up to 0.2% after a quick change in voltage. A long sample time is required before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not nearly as good. The advantage of polypropylene over polystyrene is that it extends the maximum ambient temperature from 85°C to 100°C. Most ceramic capacitors are unusable with > 1% hysteresis. Ceramic NPO or COG capacitors are now available for 125°C operation and also have low dielectric absorption. For more exact data, see Figure 2. The hysteresis numbers on the curve are final values, taken after full relaxation. The hysteresis error can be significantly reduced if the output of the LF198-N is digitized quickly after the hold mode is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10 to 50 ms. If A-to-D conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten.

9.1.2 DC and AC Zeroing

DC zeroing is accomplished by connecting the offset adjust pin to the wiper of a 1-kΩ potentiometer, which has one end tied to V+ and the other end tied through a resistor to ground. The resistor should be selected to give approximately 0.6 mA through the 1-kΩ potentiometer. AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output. A 10-pF capacitor from the wiper to the hold capacitor will give ±4-mV hold step adjustment with a 0.01-µF hold capacitor and 5-V logic supply. For larger logic swings, a smaller capacitor (< 10 pF) may be used.

9.1.3 Logic Rise Time

For proper operation, logic signals into the LF198-N must have a minimum dV/dt of 1.0 V/µs. Slower signals will cause excessive hold step. If a R/C network is used in front of the logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least 1.0 V/µs.

9.1.4 Sampling Dynamic Signals

Sample error to moving input signals probably causes more confusion among sample-and-hold users than any other parameter. The primary reason for this is that many users make the assumption that the sample and hold amplifier is truly locked on to the input signal while in the sample mode. In actuality, there are finite phase delays through the circuit creating an input-output differential for fast moving signals. In addition, although the output may have settled, the hold capacitor has an additional lag due to the 300-Ω series resistor on the chip. This means that at the moment the hold command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic which switches the circuit from sample to hold. For example, consider an analog input of 20 Vp–p at 10 kHz. Maximum dV/dt is 0.6 V/µs. With no analog phase delay and 100-ns logic delay, one could expect up to (0.1 µs) (0.6V/µs) = 60 mVerror if the hold signal arrived near maximum dV/dt of the input. A positive-going input would give a

(dynamic sampling error) is included to help estimate errors. Figure 6 indicates the time required for the output to settle to 1 mV after the hold command.

9.1.5 Digital Feedthrough

Use 10-pin layout. Guard around CH is tied to output. Figure 24. Guarding Technique

9.2 Typical Applications

9.2.1 X1000 Sample and Hold

the appropriate value of capacitance for the COMP 2 pin capacitance of the LM108. Figure 25. X1000 Sample and Hold

9.2.1.1 Design Requirements

that the maximum dynamic range is used by the 1-Vpp data converter.

9.2.1.2 Detailed Design Procedure

is 0.1 pF according to Equation 1, which is negligibly small and may be left off of the design.

9.2.1.3 Application Curves

and would be ready to sample as shown in Figure 27. Figure 26. Feedthrough Rejection Ratio (Hold Mode) Figure 27. Output Transient at Start of Hold Mode

9.2.2 Sample and Difference Circuit

Figure 28. Sample and Difference Circuit

9.2.3 Ramp Generator With Variable Reset Level

time may be computed by Equation 2. Figure 29. Ramp Generator With Variable Reset Level

9.2.4 Integrator With Programmable Reset Level

Figure 30. The integrated output voltage in hold mode is computed with Equation 3. Figure 30. Integrator With Programmable Reset Level

9.2.5 Output Holds at Average of Sampled Input

Figure 31. Output Holds at Average of Sampled Input

9.2.6 Increased Slew Current

Figure 32. Increased Slew Current

9.2.7 Reset Stabilized Amplifier

Figure 33. Reset Stabilized Amplifier

9.2.8 Fast Acquisition, Low Droop Sample and Hold

hold circuit as shown in Figure 34. Figure 34. Fast Acquisition, Low Droop Sample and Hold

9.2.9 Synchronous Correlator for Recovering Signals Below Noise Level

signals below noise level as shown in Figure 35. Figure 35. Synchronous Correlator for Recovering Signals Below Noise Level Figure 36. 2-Channel Switch In the configuration of Figure 36, input signal A and input signal B have the characteristics listed in Table 1.

Table 1. 2-Channel Switch Characteristics

9.2.11 DC and AC Zeroing

pin to create a DC- and AC-zeroing circuit as shown in Figure 37. Figure 37. DC and AC Zeroing

9.2.12 Staircase Generator

The LFx98x can be connected as shown in Figure 38 to create a staircase generator. *Select for step height: 50 kΩ → 1-V Step. Figure 38. Staircase Generator

9.2.13 Differential Hold

Two LFx98x devices may be connected as shown in Figure 39 to create a differential hold circuit. Figure 39. Differential Hold

9.2.14 Capacitor Hysteresis Compensation

The LFx98x devices may be used for capacitor hysteresis compensation as shown in Figure 40. Figure 40. Capacitor Hysteresis Compensation

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

as close to the device as possible to minimize stray parasitics.

11.2 Layout Example

Figure 41 shows an example schematic and layout for the LFx98x 8-pin PDIP package. Figure 41. Schematic Example Figure 42. Layout Example

12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

• Hold Step: The voltage step at the output of the sample and hold when switching from sample mode to hold mode with a steady (DC) analog input voltage. Logic swing is 5 V.
• Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10 V. Acquisition time is not just the time required for the output to settle, but also includes the time required for all internal nodes to settle so that the output assumes the proper value when switched to the hold mode.
• Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent difference.
• Hold Settling Time: The time required for the output to settle within 1 mV of final value after the hold logic command.
• Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. This error term occurs even for long sample times.
• Aperture Time: The delay required between hold command and an input analog transition, so that the transition does not affect the held output.

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

12.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

LF198-N,LF298,LF398-N LF198A-N,LF398A-N www.ti.com SNOSBI3C –JULY 2000–REVISED OCTOBER 2018 Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N Submit Documentation FeedbackCopyright © 2000–2018, Texas Instruments Incorporated

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LF198AH/NOPB Active Production TO-99 (LMC) | 8 500 | OTHER Yes Call TI Level-1-NA-UNLIM -55 to 125 ( LF198AH, LF198AH LF198H Active Production TO-99 (LMC) | 8 500 | OTHER No Call TI Level-1-NA-UNLIM -55 to 125 ( LF198H, LF198H) LF198H/NOPB Active Production TO-99 (LMC) | 8 500 | TRAY NON-STD Yes Call TI Level-1-NA-UNLIM -55 to 125 ( LF198H, LF198H) LF298M/NOPB Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -25 to 85 LF298M LF298M/NOPB.B Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -25 to 85 LF298M LF298MX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -25 to 85 LF298M LF298MX/NOPB.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -25 to 85 LF298M LF398AN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 398AN LF398AN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 398AN LF398H Active Production TO-99 (LMC) | 8 500 | TRAY NON-STD No Call TI Level-1-NA-UNLIM 0 to 70 LF398H LF398H/NOPB Active Production TO-99 (LMC) | 8 500 | OTHER Yes Call TI Level-1-NA-UNLIM 0 to 70 ( LF398H, LF398H) LF398M/NOPB Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 LF398M LF398M/NOPB.B Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 LF398M LF398MX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 LF398M LF398MX/NOPB.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 LF398M LF398N/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 398N LF398N/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 398N LF398N/NOPBG4 Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 398N LF398N/NOPBG4.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF 398N (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. Addendum-Page 1

www.ti.com 7-Oct-2025 (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LF298MX/NOPB SOIC D 14 2500 356.0 356.0 35.0 LF398MX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LF298M/NOPB D SOIC 14 55 495 8 4064 3.05 LF298M/NOPB.B D SOIC 14 55 495 8 4064 3.05 LF398AN/NOPB P PDIP 8 40 502 14 11938 4.32 LF398AN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LF398M/NOPB D SOIC 14 55 495 8 4064 3.05 LF398M/NOPB.B D SOIC 14 55 495 8 4064 3.05 LF398N/NOPB P PDIP 8 40 502 14 11938 4.32 LF398N/NOPB.B P PDIP 8 40 502 14 11938 4.32 LF398N/NOPBG4 P PDIP 8 40 502 14 11938 4.32 LF398N/NOPBG4.B P PDIP 8 40 502 14 11938 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE C .305-.335 [7.75-8.51] .165-.185 [4.19-4.70] .010-.040 [0.25-1.02] SEATING PLANE .040 MAX [1.02] .335-.370 [8.51-9.40] .110-.160 [2.79-4.06] .028-.034 [0.71-0.86] .500 MIN [12.7] .225 [5.72] 8X .016-.021 [0.41-0.53] .200 [5.08] .100 [2.54] UNCONTROLLED LEAD DIA .055[1.397] MAX .029-.045 [0.74-1.14]

45 TYP

TO-CAN - 5.72 mm max heightLMC0008A TRANSISTOR OUTLINE 4220610/B 09/2024 NOTES: 1. All linear dimensions are in inches [millimeters]. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pin numbers shown for reference only. Numbers may not be marked on package. 4. Reference JEDEC registration MO-002/TO-99. MAX .010 [0.25] C A A

www.ti.com EXAMPLE BOARD LAYOUT (45 ) TYP .003 MAX [0.07] ALL AROUND 7X .003 MAX [0.07] ALL AROUND ( .200 ) [5.08] ( .055) [1.4] 7X ( .055) [1.4] METAL 8X ( .031) VIA [0.8] (R.002 ) TYP [0.05] TO-CAN - 5.72 mm max heightLMC0008A TRANSISTOR OUTLINE 4220610/B 09/2024 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 12X 7X SOLDER MASK OPENING SOLDER MASK OPENING METAL

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