LF298H

LF198 NSC | Alldatasheet

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Technical content

Features

n Operates from±5V to±18V supplies n Less than 10 µs acquisition time n TTL, PMOS, CMOS compatible logic input n 0.5 mV typical hold step at Ch = 0.01 µF n Low input offset n 0.002% gain accuracy n Low output noise in hold mode n Input characteristics do not change during hold mode n High supply rejection ratio in sample or hold n Wide bandwidth n Space qualified, JM38510 Logic inputs on the LF198 are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4V. The LF198 will operate from ±5V to±18V supplies. An “A” version is available with tightened electrical specifications. Typical Connection and Performance Curve Functional Diagram DS005692-32 Acquisition Time DS005692-16 DS005692-1 July 2000 LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits © 2000 National Semiconductor Corporation DS005692 www.national.com

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ±18V Power Dissipation (Package Limitation) (Note 2) 500 mW Operating Ambient Temperature Range LF198/LF198A −55˚C to +125˚C LF298 −25˚C to +85˚C LF398/LF398A 0˚C to +70˚C Storage Temperature Range −65˚C to +150˚C Input Voltage Equal to Supply Voltage Logic To Logic Reference Differential Voltage (Note 3) +7V, −30V Output Short Circuit Duration Indefinite Hold Capacitor Short Circuit Duration 10 sec Lead Temperature (Note 4) H package (Soldering, 10 sec.) 260˚C N package (Soldering, 10 sec.) 260˚C M package: Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C Thermal Resistance (θ JA) (typicals) H package 215˚C/W (Board mount in still air) 85˚C/W (Board mount in 400LF/min air flow) N package 115˚C/W M package 106˚C/W θ JC (H package, typical) 20˚C/W

Electrical Characteristics

The following specifcations apply for −VS + 3.5V≤ VIN ≤ +VS − 3.5V, +VS = +15V, −VS = −15V, TA =T j = 25˚C, Ch = 0.01 µF, R L =1 0kΩ , LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified. Parameter Conditions LF198/LF298 LF398 Units Min Typ Max Min Typ Max Input Offset Voltage, (Note 5) Tj = 25˚C 1 3 2 7 mV Full Temperature Range 5 10 mV Input Bias Current, (Note 5) T j = 25˚C 5 25 10 50 nA Full Temperature Range 75 100 nA Input Impedance T j = 25˚C 10 10 1010 Ω Gain Error T j = 25˚C, RL = 10k 0.002 0.005 0.004 0.01 % Full Temperature Range 0.02 0.02 % Feedthrough Attenuation Ratio T j = 25˚C, Ch = 0.01 µF 86 96 80 90 dB at 1 kHz Output Impedance T j = 25˚C, “HOLD” mode 0.5 2 0.5 4 Ω Full Temperature Range 4 6 Ω Supply Current, (Note 5) T j≥25˚C 4.5 5.5 4.5 6.5 mA Logic and Logic Reference Input Tj = 25˚C 2 10 2 10 µA Current Leakage Current into Hold T j = 25˚C, (Note 7) 30 100 30 200 pA Capacitor (Note 5) Hold Mode Acquisition Time to 0.1% ΔV OUT = 10V, Ch = 1000 pF 4 4 µs C h = 0.01 µF 20 20 µs Hold Capacitor Charging Current VIN−VOUT =2 V 5 5 m A Supply Voltage Rejection Ratio VOUT = 0 80 110 80 110 dB Input Offset Voltage, (Note 5) Tj = 25˚C 1 1 2 2 mV Full Temperature Range 2 3 mV Input Bias Current, (Note 5) T j = 25˚C 5 25 10 25 nA Full Temperature Range 75 50 nA LF198/LF298/LF398, LF198A/LF398A www.national.com 2

The following specifcations apply for −VS + 3.5V≤ VIN ≤ +VS − 3.5V, +VS = +15V, −VS = −15V, TA =T j = 25˚C, Ch = 0.01 µF, R L =1 0kΩ , LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified. Parameter Conditions LF198A LF398A Units Min Typ Max Min Typ Max Input Impedance T j = 25˚C 10 10 1010 Ω Gain Error T j = 25˚C, RL = 10k 0.002 0.005 0.004 0.005 % Full Temperature Range 0.01 0.01 % Feedthrough Attenuation Ratio T j = 25˚C, Ch = 0.01 µF 86 96 86 90 dB at 1 kHz Output Impedance T j = 25˚C, “HOLD” mode 0.5 1 0.5 1 Ω Full Temperature Range 4 6 Ω “HOLD” Step, (Note 6) T j = 25˚C, Ch = 0.01µF, VOUT = 0 0.5 1 1.0 1 mV Supply Current, (Note 5) T j≥25˚C 4.5 5.5 4.5 6.5 mA Logic and Logic Reference Input Tj = 25˚C 2 10 2 10 µA Current Leakage Current into Hold T j = 25˚C, (Note 7) 30 100 30 100 pA Capacitor (Note 5) Hold Mode Acquisition Time to 0.1% ΔV OUT = 10V, Ch = 1000 pF 4 6 4 6 µs C h = 0.01 µF 20 25 20 25 µs Hold Capacitor Charging Current VIN−VOUT =2 V 5 5 m A Supply Voltage Rejection Ratio VOUT = 0 90 110 90 110 dB Note 1:“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 2:The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD =( TJMAX −T A)/θJA, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum junction temperature, TJMAX , for the LF198/LF198A is 150˚C; for the LF298, 115˚C; and for the LF398/LF398A, 100˚C. Note 3:Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the nega- tive supply. Note 4:See AN-450 “Surface Mounting Methods and their effects on Product Reliability” for other methods of soldering surface mount devices. Note 5:These parameters guaranteed over a supply voltage range of±5t o±18V, and an input range of −VS + 3.5V≤ VIN ≤ +V S − 3.5V. Note 6:Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. Note 7:Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range. Note 8:A military RETS electrical test specification is available on request. The LF198 may also be procured to Standard Military Drawing#5962-8760801GA or to MIL-STD-38510 part ID JM38510/12501SGA. Typical Performance Characteristics Note 9:See Definition of Terms Aperture Time (Note 9) DS005692-17 Dielectric Absorption Error in Hold Capacitor DS005692-18 Dynamic Sampling Error DS005692-19 LF198/LF298/LF398, LF198A/LF398A www.national.com3

Typical Performance Characteristics(Continued) Note 10:See Definition Output Droop Rate DS005692-20 Hold Step DS005692-21 “Hold” Settling Time (Note 10) DS005692-22 Leakage Current into Hold Capacitor DS005692-23 Phase and Gain (Input to Output, Small Signal) DS005692-24 Gain Error DS005692-25 Power Supply Rejection DS005692-26 Output Short Circuit Current DS005692-27 Output Noise DS005692-28 LF198/LF298/LF398, LF198A/LF398A www.national.com 4

Typical Performance Characteristics(Continued) Logic Input Configurations Input Bias Current DS005692-29 Feedthrough Rejection Ratio (Hold Mode) DS005692-30 Hold Step vs Input Voltage DS005692-31 Output Transient at Start of Sample Mode DS005692-12 Output Transient at Start of Hold Mode DS005692-13 TTL & CMOS 3V ≤ VLOGIC (Hi State)≤ 7V DS005692-33 Threshold = 1.4V DS005692-34 Threshold = 1.4V *Select for 2.8V at pin 8 LF198/LF298/LF398, LF198A/LF398A www.national.com5

Logic Input Configurations(Continued) Application Hints Hold Capacitor Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size and cost may also become important for larger values. Use of the curves included with this data sheet should be helpful in se- lecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast signals, the capacitor drive currents may cause a significant temperature rise in the LF198. A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A mylar cap, for instance, may “sag back” up to 0.2% after a quick change in voltage. A long sample time is required before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low hysteresis are polysty- rene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not nearly as good. The advantage of polypropylene over polystyrene is that it extends the maxi- mum ambient temperature from 85˚C to 100˚C. Most ce- ramic capacitors are unusable with > 1% hysteresis. Ce- ramic “NPO” or “COG” capacitors are now available for 125˚C operation and also have low dielectric absorption. For more exact data, see the curve Dielectric Absorption Error. The hysteresis numbers on the curve are final values, taken after full relaxation. The hysteresis error can be significantly reduced if the output of the LF198 is digitized quickly after the hold mode is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10 — 50 ms. If A-to-D conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten. DC and AC Zeroing DC zeroing is accomplished by connecting the offset adjust pin to the wiper ofa1k Ω potentiometer which has one end tied to V + and the other end tied through a resistor to ground. The resistor should be selected to give≈0.6 mA through the 1k potentiometer. AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output. A 10 pF capacitor from the wiper to the hold capacitor will give ±4m V hold step adjustment with a 0.01 µF hold capacitor and 5V logic supply. For larger logic swings, a smaller capacitor < 10 pF) may be used. Logic Rise Time For proper operation, logic signals into the LF198 must have a minimum dV/dt of 1.0 V/µs. Slower signals will cause ex- cessive hold step. If a R/C network is used in front of the CMOS 7V ≤ V LOGIC (Hi State)≤ 15V DS005692-35 Threshold = 0.6 (V+) + 1.4V DS005692-36 Threshold = 0.6 (V+) − 1.4V Op Amp Drive DS005692-37 Threshold≈ +4V DS005692-38 Threshold = −4V LF198/LF298/LF398, LF198A/LF398A www.national.com 6

Application Hints(Continued) logic input for signal delay, calculate the slope of the wave- form at the threshold point to ensure that it is at least 1.0 V/µs. Sampling Dynamic Signals Sample error to moving input signals probably causes more confusion among sample-and-hold users than any other pa- rameter. The primary reason for this is that many users make the assumption that the sample and hold amplifier is truly locked on to the input signal while in the sample mode. In ac- tuality, there are finite phase delays through the circuit creat- ing an input-output differential for fast moving signals. In ad- dition, although the output may have settled, the hold capacitor has an additional lag due to the 300Ω series resis- tor on the chip. This means that at the moment the “hold” command arrives, the hold capacitor voltage may be some- what different than the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic which switches the circuit from sample to hold. For ex- ample, consider an analog input of 20 Vp-p at 10 kHz. Maxi- mum dV/dt is 0.6 V/µs. With no analog phase delay and 100 ns logic delay, one could expect up to (0.1 µs) (0.6V/µs) = 60 mVerror if the “hold” signal arrived near maximum dV/dt of the input. A positive-going input would give a +60 mV er- ror. Now assume a 1 MHz (3 dB) bandwidth for the overall analog loop. This generates a phase delay of 160 ns. If the hold capacitor sees this exact delay, then error due to analog delay will be (0.16 µs) (0.6 V/µs) = −96 mV. Total output error is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To add to the confusion, analog delay is proportioned to hold capacitor value while digital delay remains constant. A family of curves (dynamic sampling error) is included to help esti- mate errors. A curve labeled Aperture Timehas been included for sam- pling conditions where the input is steady during the sam- pling period, but may experience a sudden change nearly coincident with the “hold” command. This curve is based on a 1 mV error fed into the output. A second curve, Hold Settling Timeindicates the time re- quired for the output to settle to 1 mV after the “hold” com- mand. Digital Feedthrough Fast rise time logic signals can cause hold errors by feeding externally into the analog input at the same time the amplifier is put into the hold mode. To minimize this problem, board layout should keep logic lines as far as possible from the analog input and the C h pin. Grounded guarding traces may also be used around the input line, especially if it is driven from a high impedance source. Reducing high amplitude logic signals to 2.5V will also help. Guarding Technique DS005692-5 Use 10-pin layout. Guard around Chis tied to output. LF198/LF298/LF398, LF198A/LF398A www.national.com7

X1000 Sample & Hold DS005692-39 *For lower gains, the LM108 must be frequency compensated Sample and Difference Circuit (Output Follows Input inHold Mode) DS005692-40 VOUT =V B + ΔVIN(HOLD MODE) Ramp Generator with Variable Reset Level DS005692-42 Integrator with Programmable Reset Level DS005692-43 LF198/LF298/LF398, LF198A/LF398A www.national.com 8

Typical Applications(Continued) Output Holds at Average of Sampled Input DS005692-46 Increased Slew Current DS005692-47 Reset Stabilized Amplifier (Gain of 1000) DS005692-49 Fast Acquisition, Low Droop Sample & Hold DS005692-50 LF198/LF298/LF398, LF198A/LF398A www.national.com9

Typical Applications(Continued) Synchronous Correlator for Recovering Signals Below Noise Level DS005692-52 2–Channel Switch DS005692-53 AB ZIN 1010Ω 47 kΩ BW .1 MHz .400 kHz Crosstalk −90 dB −90 dB @ 1 kHz Offset ≤ 6m V ≤ 75 mV DC & AC Zeroing DS005692-59 Staircase Generator DS005692-55 *Select for step height 50k → ≅ 1V Step LF198/LF298/LF398, LF198A/LF398A www.national.com 10

Typical Applications(Continued) Definition of Terms Hold Step:The voltage step at the output of the sample and hold when switching from sample mode to hold mode with a steady (dc) analog input voltage. Logic swing is 5V. Acquisition Time:The time required to acquire a new ana- log input voltage with an output step of 10V. Note that acqui- sition time is not just the time required for the output to settle, but also includes the time required for all internal nodes to settle so that the output assumes the proper value when switched to the hold mode. Gain Error:The ratio of output voltage swing to input volt- age swing in the sample mode expressed as a per cent dif- ference. Hold Settling Time:The time required for the output to settle within 1 mV of final value after the “hold” logic com- mand. Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. Note that this error term occurs even for long sample times. Aperture Time:The delay required between “Hold” com- mand and an input analog transition, so that the transition does not affect the held output. Connection Diagrams Differential Hold DS005692-57 Capacitor Hysteresis Compensation DS005692-56 **Adjust for amplitude Dual-In-Line Package DS005692-11 Order Number LF398N or LF398AN See NS Package Number N08E Small-Outline Package DS005692-15 Order Number LF298M or LF398M See NS Package Number M14A Metal Can Package DS005692-14 Order Number LF198H, LF198H/883, LF298H, LF398H, LF198AH or LF398AH See NS Package Number H08C (Note 8) LF198/LF298/LF398, LF198A/LF398A www.national.com11

Physical Dimensionsinches (millimeters) unless otherwise noted Metal Can Package (H) Order Number LF198H, LF298H, LF398H, LF198AH or LF398AH Molded Small-Outline Package (M) Order Number LF298M or LF398M LF198/LF298/LF398, LF198A/LF398A www.national.com 12

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Molded Dual-In-Line Package (N) Order Number LF398N or LF398AN LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.