TMS320LF2407A_17 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 134
Technical content
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068High-Performance Static CMOS Technology − 25-ns Instruction Cycle Time (40 MHz) − 40-MIPS Performance − Low-Power 3.3-V Design /C0068Based on TMS320C2xx DSP CPU Core − Code-Compatible With F243/F241/C242 − Instruction Set and Module Compatible With F240 /C0068Flash (LF) and ROM (LC) Device Options − LF240xA: LF2407A, LF2406A, LF2403A, LF2402A − LC240xA: LC2406A, LC2404A, LC2403A, LC2402A /C0068On-Chip Memory − Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors) or ROM − Programmable “Code-Security” Feature for the On-Chip Flash/ROM − Up to 2.5K Words x 16 Bits of Data/Program RAM − 544 Words of Dual-Access RAM − Up to 2K Words of Single-Access RAM /C0068Boot ROM (LF240xA Devices) − SCI/SPI Bootloader /C0068Up to Two Event-Manager (EV) Modules (EVA and EVB), Each Includes: − Two 16-Bit General-Purpose Timers − Eight 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable: − Three-Phase Inverter Control − Center- or Edge-Alignment of PWM Channels − Emergency PWM Channel Shutdown With External PDPINTx Pin − Programmable Deadband (Deadtime) Prevents Shoot-Through Faults − Three Capture Units for Time-Stamping of External Events − Input Qualifier for Select Pins − On-Chip Position Encoder Interface Circuitry − Synchronized A-to-D Conversion − Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control − Applicable for Multiple Motor and/or Converter Control /C0068External Memory Interface (LF2407A) − 192K Words x 16 Bits of Total Memory: 64K Program, 64K Data, 64K I/O /C0068Watchdog (WD) Timer Module /C006810-Bit Analog-to-Digital Converter (ADC) − 8 or 16 Multiplexed Input Channels − 500-ns MIN Conversion Time − Selectable Twin 8-State Sequencers Triggered by Two Event Managers /C0068Controller Area Network (CAN) 2.0B Module (LF2407A, 2406A, 2403A) /C0068Serial Communications Interface (SCI) /C006816-Bit Serial Peripheral Interface (SPI) (LF2407A, 2406A, LC2404A, 2403A) /C0068Phase-Locked-Loop (PLL)-Based Clock Generation /C0068Up to 40 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins /C0068Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts) /C0068Power Management: − Three Power-Down Modes − Ability to Power Down Each Peripheral Independently /C0068Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1 † (JTAG) /C0068Development Tools Include: − Texas Instruments (TI) ANSI C Compiler, Assembler/Linker, and Code Composer Studio Debugger − Evaluation Modules − Scan-Based Self-Emulation (XDS510) − Broad Third-Party Digital Motor Control Support /C0068Package Options − 144-Pin LQFP PGE (LF2407A) − 100-Pin LQFP PZ (2406A, LC2404A) − 64-Pin TQFP PAG (LF2403A, LC2403A, LC2402A) − 64-Pin QFP PG (2402A) /C0068Extended Temperature Options (A and S) − A: − 40°C to 85°C − S: − 40°C to 125°C Copyright 2005, Texas Instruments Incorporated Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Code Composer Studio and XDS510 are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. † IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Functional Block Diagram of the 2407A Functional Block Diagram of the 2407A DSP CPU 35. . Enhanced Analog-to-Digital Converter Serial Communications Interface (SCI) Module 53. . . . LF240xA and LC240xA Electrical Migrating From LF240xA (Flash) Devices to Migrating From 240x Devices to 240xA Devices 111. . . Migrating From LF240x Devices to Table of Contents
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
REVISION HISTORY
11 Added the VCCA pin to final note on Table 2
27 Modified LC2403A memory map (Figure 7) in location 8200
50 Added a sentence to the paragraph following Figure 12
59 Added 1/4 W to second column header in Table 10, Loop Filter Component Values With Damping Factor = 2.0
71 Added a note to recommended operating conditions table
72 Added a note to electrical characteristics table
77 Added Figure 23
101 Changed parameter td(WRN) in switching characteristics over recommended operating conditions for an external memory interface write at 40 MHz [H = 0.5tc(CO)] table 108 Changed MAX value for ICCA in operating characteristics over recommended operating condition ranges table
110 Added note to Table 18
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
description
The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The 240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary section for device-specific features. The 240xA generation offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash devices of up to 32K words offer a cost-effective reprogrammable solution for volume production. The 240xA devices offer a password-based “code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in on-chip Flash/ROM. Note that Flash-based devices contain a 256-word boot ROM to facilitate in-circuit programming. The 240xA family also includes ROM devices that are fully pin-to-pin compatible with their Flash counterparts. All 240xA devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Devices with dual event managers enable multiple motor and/or converter control with a single 240xA DSP controller. Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes inadvertent pin-triggering by glitches. The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 375 ns and offers up to 16 channels of analog input. The autosequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead. A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring additional communication interfaces, the 2407A, 2406A, 2404A, and 2403A offer a 16-bit synchronous serial peripheral interface (SPI). The 2407A, 2406A, and 2403A offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs). To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger supports this family. Numerous third-party developers not only offer device-level development tools, but also system-level design and development support. TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.
Table 1. Hardware Features of 240xA Devices Denotes features that are different/new compared to 240x devices.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional block diagram of the 2407A DSP controller XTAL1/CLKIN XTAL2 PLLVCCA PLLF2 PLLF VSSA VREFHI ADCIN08−ADCIN15 VCCA ADCIN00−ADCIN07 SCIRXD/IOPA1 SPISIMO/IOPC2 XINT2/ADCSOC/IOPD0 SCITXD/IOPA0 VREFLO Port A(0−7) IOPA[0:7] SPICLK/IOPC4 SPISTE/IOPC5 SPISOMI/IOPC3 Port E(0−7) IOPE[0:7] Port F(0−6) IOPF[0:6] Port C(0−7) IOPC[0:7] Port D(0) IOPD[0] Port B(0−7) IOPB[0:7] TDO TDI CANRX/IOPC7 TRST CANTX/IOPC6 EMU1 PDPINTB TCK EMU0 TMS CAP5/QEP4/IOPF0 CAP4/QEP3/IOPE7 PWM7/IOPE1 PWM8/IOPE2 CAP6/IOPF1 PWM10/IOPE4 PWM9/IOPE3 PWM11/IOPE5 PWM12/IOPE6 T4PWM/T4CMP/IOPF3 T3PWM/T3CMP/IOPF2 TDIRB/IOPF4 TCLKINB/IOPF5 DARAM (B0)
256 Words
DARAM (B1) DARAM (B2)
32 Words
(With Twin Autosequencer) ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ RS CLKOUT/IOPE0 XINT1/IOPA2 BIO/IOPC1 MP/MC TMS2 A0−A15 D0−D15 TP1 TP2 BOOT_EN/XF READY STRB R/W RD PS, DS, IS VIS_OE ENA_144 WE CAP3/IOPA5 PWM1/IOPA6 CAP1/QEP1/IOPA3 CAP2/QEP2/IOPA4 PDPINTA PWM5/IOPB2 PWM6/IOPB3 PWM3/IOPB0 PWM4/IOPB1 PWM2/IOPA7 T2PWM/T2CMP/IOPB5 T1PWM/T1CMP/IOPB4 TCLKINA/IOPB7 TDIRA/IOPB6 VDD (3.3 V) VSS VCCP(5V) ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ SARAM (2K Words) Flash/ROM (32K Words: 4K/12K/12K/4K) External Memory Interface Event Manager A /C00683 × Capture Input /C00686 × Compare/PWM Output /C00682 × GP Timers/PWM SCI SPI WD Digital I/O (Shared With Other Pins) CAN JTAG Port Event Manager B /C00683 × Capture Input /C00686 × Compare/PWM Output /C00682 × GP Timers/PWM ÈÈÈ ÈÈÈ ÈÈÈ Indicates optional modules. The memory size and peripheral selection of these modules change for different 240xA devices. See Table 1 for device-specific details. W/R / IOPC0
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pinouts 144 143 142 141 140 139 138 137 136 135 134 RS133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 108 107 106 105 104 103 102 101 100 111 110 109 TMS320LF2407A PGE PDPINTA PLLF TDIRA/IOPB6 XINT2/ADCSOC/IOPD0 CLKOUT/IOPE0 PDPINTB XTAL1/CLKIN XTAL2 PLLVCCA PLLF2 BOOT_EN/XF CCPV TP1 TP2 IOPF6 EMU0 EMU1/OFF TCK TDI TDO TMS TMS2 TRST DS IS PS R/W W/R/IOPC0 RD WE STRB READY MP/MC ENA_144 VIS_OE A10 A11 A12 A13 A14 A15 D10 D11 D12 D13 D14 D15 PLLVCCA VDD DDV VDD DDV VDDO DDOV DDOV VDDO VDDO DDOV VSS SSV VSS SSV VSSO SSOV SSOV VSSO VSSO SSOV SSOV CAP1/QEP1/IOPA3 CAP2/QEP2/IOPA4 CAP3/IOPA5 PWM1/ PWM2/ PWM3/ PWM4/ PWM5/ PWM6/ T1PWM/T1CMP/IOPB4 T2PWM/T2CMP/IOPB5 TCLKINA/ CAP4/QEP3/IOPE7 CAP5/QEP4/IOPF0 CAP6/ PWM7/ PWM8/ PWM9/ PWM10/ PWM11/ PWM12/ T3PWM/T3CMP/IOPF2 T4PWM/T4CMP/IOPF3 TDIRB/IOPF4 TCLKINB/ ADCIN00 ADCIN01 ADCIN02 ADCIN03 ADCIN04 ADCIN05 ADCIN06 ADCIN07 ADCIN08 ADCIN09 ADCIN10 ADCIN11 ADCIN12 ADCIN13 ADCIN14 ADCIN15 REFHIV REFLOV CCAV SSAV CANRX/ CANTX/ SCITXD/IOPA0 SCIRXD/IOPA1 SPICLK/IOPC4 SPISIMO/IOPC2 SPISOMI/IOPC3 SPISTE/IOPC5 XINT1/IOPA2 † Bold, italicized pin names indicate pin function after reset. ‡ BOOT_EN is available only on Flash devices. IOPB7 IOPE6 IOPB3 IOPB2 IOPE5 IOPB1 IOPB0 IOPA7 IOPE4 IOPA6 IOPE3 IOPE2 IOPE1 IOPF1 IOPC7 IOPC6 IOPF5 IOPC1BIO/ PGE PACKAGE† (TOP VIEW)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pinouts (continued) SCIRXD/ TMS TDO VDDO VSSO TDI PDPINTB TCK RS IOPF6 VDD VSS TCLKINB/IOPF5 XTAL2 XTAL1/CLKIN BOOT_EN/XF§ BIO/IOPC1 VSSA VCCA VREFHI VREFLO ADCIN08 ADCIN00 ADCIN09 ADCIN01 ADCIN10 TCLKINA/IOPB7 PWM12/IOPE6 PWM6/IOPB3 V SSO VDDO PWM5/IOPB2 PWM11/IOPE5 PWM4/IOPB1 VSS VDD PWM3/IOPB0 PWM2/IOPA7 PWM10/IOPE4 PWM1/IOPA6 VCCP¶ PWM9/IOPE3 TP1 PWM8/IOPE2 TP2 PWM7/IOPE1 V SSO VDDO CAP6/IOPF1 CANRX/IOPC7‡ CANTX/IOPC6‡50 26100 25242322212019181716151413121110987654321 51525354555657585960616263646566676869707172737475 ADCIN11 ADCIN02 ADCIN12 ADCIN03 ADCIN13 ADCIN04 ADCIN05 ADCIN14 ADCIN06 ADCIN07 ADCIN15 EMU1/ EMU0 CAP4/QEP3/ V CAP1/QEP1/ CAP5/QEP4/ CAP2/QEP2/ V CAP3/ /IOPE0 DD DDO TRST TDIRB/ V T4PWM/T4CMP/ PDPINTA PLLF2 PLLF T1PWM/T1CMP/ T2PWM/T2CMP/ XINT2/ADCSOC/ SCITXD/ SPISOMI/ SPISTE/ SPICLK/ DDO PZ PACKAGE† (TOP VIEW) TDIRA/ TMS320LC2404A PZ TMS320LC2406A PZ TMS320LF2406A PZT3PWM/T3CMP/ XINT1/ PLLVCCA TMS2 VDD VDDO VSS VSS VSSOVSSO VSSO VSSO † Bold, italicized pin names indicate pin function after reset. ‡ CANTX and CANRX are not available on LC2404A devices. § BOOT_EN is available only on Flash devices. ¶ On the ROM devices (LC240xA), VCCP is a No Connect (NC). IOPF4 IOPF3 IOPF2 IOPB6 IOPB4 IOPB5 IOPC0 IOPD0 IOPA2 IOPA0 IOPA1 SPISIMO/IOPC2 IOPC3 IOPC5 IOPC4 IOPE7 CLKOUT IOPA3 IOPF0 IOPA4 IOPA5 TDIRB/IOPF4 OFF
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pinouts (continued) PAG PACKAGE†‡ (TOP VIEW) 64 17 TMS320LF2403A PAG TMS320LC2403A PAG TMS320LC2402A PAG CLKOUT/IOPE0 CAP3/IOPA5 23456789 1 0 1 1 1 2 1 3 1 4 1 5 47 46 45 44 4342 41 40 39 38 37 36 35 34 1863 1962 2061 2160 2259 2358 2457 2556 2655 2754 2853 2952 3051 3150 CAP2/QEP2/IOPA4 CAP1/QEP1/IOPA3 VSS VDD EMU0 EMU1/ OFF VSSO VDDO ADCIN07 ADCIN06 ADCIN05 ADCIN04 ADCIN03 ADCIN02 VREFHI VCCA VSSA BOOT_EN/XF§ XTAL1/CLKIN XTAL2 VSS VDD RS TCK TDI TDO TMS V REFLO ADCIN00 ADCIN01CANTX/IOPC6 CANRX/IOPC7 TP2 TP1 VCCP¶ PWM1/IOPA6 PWM2/IOPA7 PWM3/IOPB0 VDD VSS PWM4/IOPB1 PWM5/IOPB2 VDDO VSSO PWM6/IOPB3 TCLKINA/IOPB7 TRST VSSO VDDO PDPINTA PLLF2 PLLF PLLVCCA T1PWM/T1CMP/IOPB4 T2PWM/T2CMP/IOPB5 XINT2/ADCSOC/IOPD0 SCITXD/IOPA0 SCIRXD/IOPA1 TMS2 † Bold, italicized pin names indicate pin function after reset. ‡ For LC2402A, the following pins are different from what is shown: Pin 45: IOPC2 Pin 46: IOPC3 Pin 47: IOPC4 Pin 63: IOPC7 Pin 64: IOPC6 § BOOT_EN is available only on flash devices. ¶ On the ROM devices (LC240xA), VCCP is a No Connect (NC). SPICLK/ SPISOMI/ SPISIMO/ IOPC4 IOPC3 IOPC2
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pinouts (continued) VREFHI VCCA VSSA BOOT_EN/XF‡ XTAL1/CLKIN XTAL2 VSS VDD RS TCK TDI TDO TMSVDDO IOPC6 IOPC7 TP2 TP1 VCCP§ PWM1/IOPA6 PWM2/IOPA7 PWM3/IOPB0 VDD VSS PWM4/IOPB1 PWM5/IOPB2 V ADCIN00 PDPINTA PLLF2 PLLF T1PWM/T1CMP/ T2PWM/T2CMP/ SCITXD/ EMU0 TMS2 TCLKINA/ PWM6/ CAP1/QEP1/ CAP2/QEP2/ CAP3/ CLKOUT ADCIN01 ADCIN02 ADCIN03 ADCIN04 ADCIN05 ADCIN06 ADCIN07 REFLO SCIRXD/ XINT2/ADCSOC/ PLLVCCA EMU1/ TRST TMS320LC2402A PG TMS320LF2402A PG VSSO VDDO VDDO VSSO VDD VSS IOPB4 IOPB5 IOPD0 IOPA0 IOPA1 IOPC2 IOPC3 IOPC4 IOPB7 IOPB3 /IOPE0 IOPA5 IOPA4 IOPA3 OFF 191 2 3 4 5 6 7 8 91 01 11 2 1 3 1 41 5 1 61 7 1 8 3351 34 3550 49 48 47 46 45 44 43 42 41 40 3938 37 36 PG PACKAGE (TOP VIEW) † Bold, italicized pin names indicate pin function after reset. ‡ BOOT_EN is available only on Flash devices. § On the ROM devices (LC240xA), VCCP is a No Connect (NC). VSSO
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions The TMS320LF2407A device is the superset of all the 240xA devices. All signals are available on the 2407A device. Table 2 lists the signals available in the 240xA generation of devices. Table 2. LF240xA and LC240xA Pin List and Package Options†‡ EVENT MANAGER A (EVA) CAP1/QEP1/IOPA3 83 57 57 4 Capture input #1/quadrature encoder pulse input #1 (EVA) or GPIO ( ↑) CAP2/QEP2/IOPA4 79 55 55 3 Capture input #2/quadrature encoder pulse input #2 (EVA) or GPIO ( ↑) CAP3/IOPA5 75 52 52 2 Capture input #3 (EVA) or GPIO ( ↑) PWM1/IOPA6 56 39 39 59 Compare/PWM output pin #1 (EVA) or GPIO ( ↑) PWM2/IOPA7 54 37 37 58 Compare/PWM output pin #2 (EVA) or GPIO ( ↑) PWM3/IOPB0 52 36 36 57 Compare/PWM output pin #3 (EVA) or GPIO ( ↑) PWM4/IOPB1 47 33 33 54 Compare/PWM output pin #4 (EVA) or GPIO ( ↑) PWM5/IOPB2 44 31 31 53 Compare/PWM output pin #5 (EVA) or GPIO ( ↑) PWM6/IOPB3 40 28 28 50 Compare/PWM output pin #6 (EVA) or GPIO ( ↑) T1PWM/T1CMP/IOPB4 16 12 12 40 Timer 1 compare output (EVA) or GPIO ( ↑) T2PWM/T2CMP/IOPB5 18 13 13 41 Timer 2 compare output (EVA) or GPIO ( ↑) TDIRA/IOPB6 14 11 11 Counting direction for general-purpose (GP) timer (EVA) or GPIO. If TDIRA = 1, upward counting is selected. If TDIRA = 0, downward counting is selected. ( ↑) TCLKINA/IOPB7 37 26 26 49 External clock input for GP timer (EVA) or GPIO. Note that the timer can also use the internal device clock. ( ↑) EVENT MANAGER B (EVB) CAP4/QEP3/IOPE7 88 60 60 Capture input #4/quadrature encoder pulse input #3 (EVB) or GPIO ( ↑) CAP5/QEP4/IOPF0 81 56 56 Capture input #5/quadrature encoder pulse input #4 (EVB) or GPIO ( ↑) CAP6/IOPF1 69 48 48 Capture input #6 (EVB) or GPIO ( ↑) PWM7/IOPE1 65 45 45 Compare/PWM output pin #7 (EVB) or GPIO ( ↑) PWM8/IOPE2 62 43 43 Compare/PWM output pin #8 (EVB) or GPIO ( ↑) PWM9/IOPE3 59 41 41 Compare/PWM output pin #9 (EVB) or GPIO ( ↑) PWM10/IOPE4 55 38 38 Compare/PWM output pin #10 (EVB) or GPIO ( ↑) PWM11/IOPE5 46 32 32 Compare/PWM output pin #11 (EVB) or GPIO ( ↑) PWM12/IOPE6 38 27 27 Compare/PWM output pin #12 (EVB) or GPIO ( ↑) † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin functions (continued) Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued) EVENT MANAGER B (EVB) (CONTINUED) T3PWM/T3CMP/IOPF2 8 7 7 Timer 3 compare output (EVB) or GPIO ( ↑) T4PWM/T4CMP/IOPF3 6 5 5 Timer 4 compare output (EVB) or GPIO ( ↑) TDIRB/IOPF4 2 2 2 Counting direction for general-purpose (GP) timer (EVB) or GPIO. If TDIRB = 1, upward counting is selected. If TDIRB = 0, downward counting is selected. ( ↑) TCLKINB/IOPF5 126 89 89 External clock input for GP timer (EVB) or GPIO. Note that the timer can also use the internal device clock. ( ↑) ANALOG-TO-DIGITAL CONVERTER (ADC) ADCIN00 112 79 79 18 Analog input #0 to the ADC ADCIN01 110 77 77 17 Analog input #1 to the ADC ADCIN02 107 74 74 16 Analog input #2 to the ADC ADCIN03 105 72 72 15 Analog input #3 to the ADC ADCIN04 103 70 70 14 Analog input #4 to the ADC ADCIN05 102 69 69 13 Analog input #5 to the ADC ADCIN06 100 67 67 12 Analog input #6 to the ADC ADCIN07 99 66 66 11 Analog input #7 to the ADC ADCIN08 113 80 80 Analog input #8 to the ADC ADCIN09 111 78 78 Analog input #9 to the ADC ADCIN10 109 76 76 Analog input #10 to the ADC ADCIN11 108 75 75 Analog input #11 to the ADC ADCIN12 106 73 73 Analog input #12 to the ADC ADCIN13 104 71 71 Analog input #13 to the ADC ADCIN14 101 68 68 Analog input #14 to the ADC ADCIN15 98 65 65 Analog input #15 to the ADC VREFHI 115 82 82 20 ADC analog high-voltage reference input VREFLO 114 81 81 19 ADC analog low-voltage reference input VCCA 116 83 83 21 Analog supply voltage for ADC (3.3 V)§ VSSA 117 84 84 22 Analog ground reference for ADC † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions (continued) CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI) CANRX/IOPC7 CANRX 70 49 − 63 CAN receive data or GPIO (LF2403A) ( ↑) CANRX/IOPC7 IOPC7 70 49 49 63 GPIO only (2402A) ( ↑) CANTX/IOPC6 CANTX 72 50 − 64 CAN transmit data or GPIO (LF2403A) ( ↑) CANTX/IOPC6 IOPC6 72 50 50 64 GPIO only (2402A) ( ↑) SCITXD/IOPA0 25 17 17 43 SCI asynchronous serial port transmit data or GPIO ( ↑) SCIRXD/IOPA1 26 18 18 44 SCI asynchronous serial port receive data or or GPIO ( ↑) SPICLK/IOPC4 SPICLK 35 24 24 47 SPI clock or GPIO (LF2403A) ( ↑) SPICLK/IOPC4 IOPC4 35 24 24 47 GPIO only (2402A) ( ↑) SPISIMO/IOPC2 SPISIMO 30 21 21 45 SPI slave in, master out or GPIO (LF2403A) ( ↑) SPISIMO/IOPC2 IOPC2 30 21 21 45 GPIO only (2402A) ( ↑) SPISOMI/IOPC3 SPISOMI 32 22 22 46 SPI slave out, master in or GPIO (LF2403A) ( ↑) SPISOMI/IOPC3 IOPC3 32 22 22 46 GPIO only (2402A) ( ↑) SPISTE/IOPC5 SPISTE 33 23 23 − SPI slave transmit enable (optional) or GPIO ( ↑)SPISTE/IOPC5 IOPC5 33 23 23 − SPI slave transmit-enable (optional) or GPIO ( ↑) EXTERNAL INTERRUPTS, CLOCK RS 133 93 93 28 Device Reset (in) and Watchdog Reset (out). Device reset. RS causes the device to terminate execution and to set PC = 0. When RS is brought to a high level, execution begins at location 0x0000 of program memory. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the RS pin will be driven low for the watchdog reset duration of 128 CLKIN cycles. The output buffer of this pin is an open-drain with an internal pullup (20 µA, typical). It is recommended that this pin be driven by an open-drain device. ( ↑) PDPINTA 7 6 6 36 Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins (EVA) in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINTA is a falling-edge-sensitive interrupt. ( ↑) † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin functions (continued) EXTERNAL INTERRUPTS, CLOCK (CONTINUED) XINT1/IOPA2 23 16 16 External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is programmable. ( ↑) XINT2/ADCSOC/IOPD0 21 15 15 42 External user interrupt 2 and ADC start of conversion or GPIO. External “start-of-conversion” input for ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is programmable. ( ↑) CLKOUT/IOPE0 73 51 51 1 Clock output or GPIO. This pin outputs either the CPU clock (CLKOUT) or the watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14) of the system control and status register (SCSR). This pin can be used as a GPIO if not used as a clock output pin. ( ↑) PDPINTB 137 95 95 Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins (EVB) in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINTB is a falling-edge-sensitive interrupt. ( ↑) OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS XTAL1/CLKIN 123 87 87 24 PLL oscillator input pin. Crystal input to PLL/clock source input to PLL. XTAL1/CLKIN is tied to one side of a reference crystal. XTAL2 124 88 88 25 Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a reference crystal. This pin goes in the high-impedance state when EMU1/OFF is active low. PLLVCCA 12 10 10 39 PLL supply (3.3 V) IOPF6 131 92 92 General-purpose I/O ( ↑) BOOT_EN / BOOT_EN 121 86 − 23 Boot ROM enable, GPO, XF. This pin will be sampled as input (BOOT_EN ) to update SCSR2.3 (BOOT_EN bit) during reset and then driven as an output signal for XF. AfterBOOT_EN / XF XF 121 86 86 23 during reset and then driven as an output signal for XF. After reset, XF is driven high. ROM devices do not have boot ROM, hence, no BOOT_EN modes. The BOOT_EN pin must be driven with a passive circuit only. ( ↑) PLLF 11 9 9 38 PLL loop filter input 1 † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions (continued) OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED) PLLF2 10 8 8 37 PLL loop filter input 2 VCCP (5V) 58 40 40 60 Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash programming. The Flash cannot be programmed if this pin is connected to GND. When not programming the Flash (i.e., during normal device operation), this pin can either be left connected to the 5-V supply or it can be tied to GND. This pin must not be left floating at any time. Do not use any current-limiting resistor in series with the 5-V supply on this pin. This pin is a “no connect” (NC) on ROM parts (i.e., this pin is not connected to any circuitry internal to the device). Connecting this pin to 5 V or leaving it open makes no difference on ROM parts. TP1 60 42 42 61 Test pin 1. Do not connect. TP2 63 44 44 62 Test pin 2. Do not connect. BIO/IOPC1 119 85 85 Branch control input. BIO is polled by the BCND pma,BIO instruction. If BIO is low, a branch is executed. If BIO is not used, it should be pulled high. This pin is configured as a branch control input by all device resets. It can be used as a GPIO, if not used as a branch control input. ( ↑) EMULATION AND TEST EMU0 90 61 61 7 Emulator I/O #0 with internal pullup. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. ( ↑) EMU1/OFF 91 62 62 8 Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. When TRST is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = 0 EMU0 = 1 EMU1/OFF = 0 ( ↑) TCK 135 94 94 29 JTAG test clock with internal pullup ( ↑) † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin functions (continued) EMULATION AND TEST (CONTINUED) TDI 139 96 96 30 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. ( ↑) TDO 142 99 99 31 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. ( ↓) TMS 144 100 100 32 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. ( ↑) TMS2 36 25 25 48 JTAG test-mode select 2 (TMS2) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. Used for test and emulation only. This pin can be left unconnected in user applications. If the PLL bypass mode is desired, TMS2, TMS, and TRST should be held low during reset. ( ↑) TRST 1 1 1 33 JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. ( ↓) NOTE: Do not use pullup resistors on TRST ; it has an internal pulldown device. TRST is an active high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application−specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I ↓) † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions (continued) ADDRESS, DATA, AND MEMORY CONTROL SIGNALS DS 87 Data space strobe. IS , DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. They are placed in the high-impedance state.¶ IS 82 I/O space strobe. IS, DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. They are placed in the high-impedance state.¶ PS 84 Program space strobe. IS, DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. They are placed in the high-impedance state.¶ R/W 92 Read/write qualifier signal. R/W indicates transfer direction during communication to an external device. It is normally in read mode (high), unless low level is asserted for performing a write operation. R/W is placed in the high-impedance state.¶ W/R / IOPC0 W/R 19 Write/Read qualifier or GPIO. This is an inverted R/W signal useful for zero-wait-state memory interface. It is normally low, unless a memory writeW/R / IOPC0 IOPC0 19 14 14 interface. It is normally low, unless a memory write operation is performed. See Table 12, Port C section, for reset note regarding LF2406A and LF2402A. ( ↑) RD 93 Read-enable strobe. Read-select indicates an active, external read cycle. RD is active on all external program, data, and I/O reads. RD is placed in the high-impedance state.¶ WE 89 Write-enable strobe. The falling edge of WE indicates that the device is driving the external data bus (D15 −D0). WE is active on all external program, data, and I/O writes. WE is placed in the high-impedance state.¶ STRB 96 External memory access strobe. STRB is always high unless asserted low to indicate an external bus cycle. STRB is active for all off-chip accesses. STRB is placed in the high-impedance state.¶ † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin functions (continued) ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED) READY 120 READY is pulled low to add wait states for external accesses. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready, it pulls the READY pin low. The processor waits one cycle and checks READY again. Note that the processor performs READY-detection if at least one software wait state is programmed. To meet the external READY timing parameters, the wait-state generator control register (WSGR) should be programmed for at least one wait state. ( ↑) MP/MC 118 Microprocessor/Microcomputer mode select. If this pin is low during reset, the device is put in microcomputer mode and program execution begins at 0000h of internal program memory (Flash EEPROM). A high value during reset puts the device in microprocessor mode and program execution begins at 0000h of external program memory. This line sets the MP/MC bit (bit 2 in the SCSR2 register). ( ↓) ENA_144 122 Active high to enable external interface signals. If pulled low, the 2407A behaves like the 2406A/2403A/2402A—i.e., it has no external memory and generates an illegal address if DS is asserted. This pin has an internal pulldown. ( ↓) VIS_OE 97 Visibility output enable (active when data bus is output). This pin is active (low) whenever the external data bus is driving as an output during visibility mode. Can be used by external decode logic to prevent data bus contention while running in visibility mode. A0 80 Bit 0 of the 16-bit address bus A1 78 Bit 1 of the 16-bit address bus A2 74 Bit 2 of the 16-bit address bus A3 71 Bit 3 of the 16-bit address bus A4 68 Bit 4 of the 16-bit address bus A5 64 Bit 5 of the 16-bit address bus A6 61 Bit 6 of the 16-bit address bus A7 57 Bit 7 of the 16-bit address bus A8 53 Bit 8 of the 16-bit address bus A9 51 Bit 9 of the 16-bit address bus A10 48 Bit 10 of the 16-bit address bus A11 45 Bit 11 of the 16-bit address bus † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions (continued) ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED) A12 43 Bit 12 of the 16-bit address bus A13 39 Bit 13 of the 16-bit address bus A14 34 Bit 14 of the 16-bit address bus A15 31 Bit 15 of the 16-bit address bus D0 127 Bit 0 of 16-bit data bus ( ↑) D1 130 Bit 1 of 16-bit data bus ( ↑) D2 132 Bit 2 of 16-bit data bus ( ↑) D3 134 Bit 3 of 16-bit data bus ( ↑) D4 136 Bit 4 of 16-bit data bus ( ↑) D5 138 Bit 5 of 16-bit data bus ( ↑) D6 143 Bit 6 of 16-bit data bus ( ↑) D7 5 Bit 7 of 16-bit data bus ( ↑) D8 9 Bit 8 of 16-bit data bus ( ↑) D9 13 Bit 9 of 16-bit data bus ( ↑) D10 15 Bit 10 of 16-bit data bus ( ↑) D11 17 Bit 11 of 16-bit data bus ( ↑) D12 20 Bit 12 of 16-bit data bus ( ↑) D13 22 Bit 13 of 16-bit data bus ( ↑) D14 24 Bit 14 of 16-bit data bus ( ↑) D15 27 Bit 15 of 16-bit data bus ( ↑) POWER SUPPLY 29 20 20 6 V # 50 35 35 27 Core supply 3 3 V Digital logic supply voltageVDD# 86 59 59 56 Core supply +3.3 V. Digital logic supply voltage. 129 91 91 4 4 4 10 42 30 30 35 V # 67 47 47 52 I/O buffer supply +3.3 V. Digital logic and buffer supplyVDDO# 77 54 54 I/O buffer supply +3.3 V. Digital logic and buffer supply voltage. 95 64 64 141 98 98 † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin functions (continued) POWER SUPPLY (CONTINUED) 28 19 19 5 V # 49 34 34 26 Core ground Digital logic ground referenceVSS# 85 58 58 55 Core ground. Digital logic ground reference. 128 90 90 3 3 3 9 41 29 29 34 66 46 46 51 VSSO# 76 53 53 I/O buffer ground. Digital logic and buffer ground reference.VSSO 94 63 63 I/O buffer ground. Digital logic and buffer ground reference. 125 97 97 140 † Bold, italicized pin names indicate pin function after reset. ‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset. § It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. ¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high # No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000 −00FF in the program space will be occupied by boot ROM. † Addresses 0040h−0043h in on-chip program memory are reserved for code security passwords. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 1. TMS320LF2407A Memory Map
22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000 −00FF in the program space will be occupied by boot ROM. † Addresses 0040h−0043h in program memory are reserved for code security passwords. example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 2. TMS320LF2406A Memory Map
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000 −00FF in the program space will be occupied by boot ROM. † Addresses 0040h−0043h in program memory are reserved for code security passwords. example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 3. TMS320LF2403A Memory Map
24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000 −00FF in the program space will be occupied by boot ROM. † Addresses 0040h−0043h in program memory are reserved for code security passwords. example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 4. TMS320LF2402A Memory Map
† Addresses 0040h−0043h in program memory are reserved for code security passwords. example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 5. TMS320LC2406A Memory Map
26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
0100 Reserved
† Addresses 0040h−0043h in program memory are reserved for code security passwords. example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 6. TMS320LC2404A Memory Map
† Addresses 0040h−0043h in program memory are reserved for code security passwords. example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 7. TMS320LC2403A Memory Map
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
† Addresses 0040h−0043h in program memory are reserved for code security passwords. example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved. a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved. has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved. Figure 8. TMS320LC2402A Memory Map
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 peripheral memory map of the 2407A/2406A ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ Reserved Reserved ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ 70C0−70FF General-Purpose Timer Registers Flag Registers Event Manager − EVB Deadband Registers Compare, PWM, and Interrupt Mask, Vector, and Capture and QEP Registers 7500−7508 7511−7519 7520−7529 752C−7531 7532−753F 7432−743F 742C−7431 7420−7429 7411−7419 7400−7408 Illegal Flag Registers Interrupt Mask, Vector and Capture and QEP Registers Deadband Registers Compare, PWM, and Timer Registers General-Purpose Event Manager − EVA 710F−71FF 7100−710E 70A0−70BF 7090−709F 7080−708F 7070−707F 7060−706F 7050−705F 7040−704F 7030−703F 7020−702F 7010−701F 7000−700F CAN Control Registers ADC Control Registers Digital I/O Control Registers External-Interrupt Registers SCI SPI Watchdog Timer Registers Control Registers System Configuration and Hex Hex 005F 0007 0006 0005 0004 0003 0000 and Reserved Emulation Registers Interrupt Flag Register Interrupt-Mask Register FFFF 77F0 77EF 7540 753F 7500 74FF 7440 743F 7400 73FF 7000 6FFF 1000 07FF 0400 03FF 0300 02FF 0200 01FF 0080 007F 0060 005F 0000 External† Peripheral Frame 3 (PF3) Peripheral Frame 2 (PF2) Peripheral Frame 1 (PF1) On-Chip DARAM B1 On-Chip DARAM B0 Reserved On-Chip DARAM B2 and Reserved Memory-Mapped Registers “Illegal” indicates that access to these addresses causes a nonmaskable interrupt (NMI). ÈÈÈÈ ÈÈÈÈ ÈÈÈÈ Reserved “Reserved” indicates addresses that are reserved for test. † Available in LF2407A only ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal 0100 00FF Reserved ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ Illegal0500 04FF SARAM (2K)0800 0FFF ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ CAN Mailbox Illegal 7230−73FF 7200−722F Illegal Reserved Code Security Passwords Illegal 77F3 77F4 7FFF 8000 Reserved77FF 7800
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
device reset and interrupts The TMS320x240xA software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The LF240xA recognizes three types of interrupt sources. /C0068Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any other executing functions. All maskable interrupts are disabled until the reset service routine enables them. The LF240xA devices have two sources of reset: an external reset pin and a watchdog timer time-out (reset). /C0068Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two types: − External interrupts are generated by one of four external pins corresponding to the interrupts XINT1, XINT2, PDPINTA, and PDPINTB. These four can be masked both by dedicated enable bits and by the CPU interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. − Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A, event manager B, SPI, SCI, CAN, and ADC. They can be masked both by enable bits for each event in each peripheral and by the CPU IMR, which can mask each maskable interrupt line at the DSP core. /C0068Software-generated interrupts for the LF240xA devices include: − The INTR instruction. This instruction allows initialization of any LF240xA interrupt with software. Its operand indicates the interrupt vector location to which the CPU branches. This instruction globally disables maskable interrupts (sets the INTM bit to 1). − The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction globally disables maskable interrupts. 240xA devices do not have the NMI hardware signal, only software activation is provided. − The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts. − An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction. Six core interrupts (INT1−INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to the F24x devices. The PIE manages all the peripheral interrupts from the 240xA peripherals and are grouped to share the six core level interrupts. Figure 9 shows the PIE block diagram for hardware-generated interrupts. The PIE block diagram (Figure 9) and the interrupt table (Table 3) explain the grouping and interrupt vector maps. LF240xA devices have interrupts identical to those of the F24x devices and should be completely code-compatible. 240xA devices also have peripheral interrupts identical to those of the F24x − plus additional interrupts for new peripherals such as event manager B. Though the new interrupts share the 24x interrupt grouping, they all have a unique vector to differentiate among the interrupts. See Table 3 for details.
Indicates change with respect to the TMS320F243/F241/C242 data sheets. Interrupts from external interrupt pins. The remaining interrupts are internal to the peripherals. Figure 9. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
interrupt request structure Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors 0000h N/A N RS pin, Watchdog Reset from pin, watchdog timeout Reserved 2 − 0026h N/A N CPU Emulator trap NMI 3 NMI 0024h N/A N Nonmaskable Interrupt Nonmaskable interrupt, software interrupt only PDPINTA 4 0.0 0020h Y EVA Power device protection PDPINTB 5 2.0 0019h Y EVB Power device protection interrupt pins ADCINT 6 0.1 0004h Y ADC ADC interrupt in high-priority mode XINT1 7 0.2 0001h Y External Interrupt Logic External interrupt pins in high XINT2 8 INT1 0.3 0011h Y External Interrupt Logic External interrupt pins in high priority SPIINT 9 INT1 0002h 0.4 0005h Y SPI SPI interrupt pins in high priority RXINT 10 0002h 0.5 0006h Y SCI SCI receiver interrupt in high-priority mode TXINT 11 0.6 0007h Y SCI SCI transmitter interrupt in high-priority mode CANMBINT 12 0.7 0040 Y CAN CAN mailbox in high-priority mode CANERINT 13 0.8 0041 Y CAN CAN error interrupt in high-priority mode CMP1INT 14 0.9 0021h Y EVA Compare 1 interrupt CMP2INT 15 0.10 0022h Y EVA Compare 2 interrupt CMP3INT 16 0.11 0023h Y EVA Compare 3 interrupt T1PINT 17 INT2 0.12 0027h Y EVA Timer 1 period interrupt T1CINT 18 INT2 0004h 0.13 0028h Y EVA Timer 1 compare interrupt T1UFINT 19 0004h 0.14 0029h Y EVA Timer 1 underflow interrupt T1OFINT 20 0.15 002Ah Y EVA Timer 1 overflow interrupt CMP4INT 21 2.1 0024h Y EVB Compare 4 interrupt CMP5INT 22 2.2 0025h Y EVB Compare 5 interrupt CMP6INT 23 2.3 0026h Y EVB Compare 6 interrupt T3PINT 24 2.4 002Fh Y EVB Timer 3 period interrupt T3CINT 25 2.5 0030h Y EVB Timer 3 compare interrupt T3UFINT 26 2.6 0031h Y EVB Timer 3 underflow interrupt T3OFINT 27 2.7 0032h Y EVB Timer 3 overflow interrupt † See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information. NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details. New peripheral interrupts and vectors with respect to the F243/F241 devices.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 33POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 interrupt request structure (continued) Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors (Continued) T2PINT 28 1.0 002Bh Y EVA Timer 2 period interrupt T2CINT 29 1.1 002Ch Y EVA Timer 2 compare interrupt T2UFINT 30 1.2 002Dh Y EVA Timer 2 underflow interrupt T2OFINT 31 INT3 1.3 002Eh Y EVA Timer 2 overflow interrupt T4PINT 32 INT3 0006h 2.8 0039h Y EVB Timer 4 period interrupt T4CINT 33 2.9 003Ah Y EVB Timer 4 compare interrupt T4UFINT 34 2.10 003Bh Y EVB Timer 4 underflow interrupt T4OFINT 35 2.11 003Ch Y EVB Timer 4 overflow interrupt CAP1INT 36 1.4 0033h Y EVA Capture 1 interrupt CAP2INT 37 1.5 0034h Y EVA Capture 2 interrupt CAP3INT 38 INT4 1.6 0035h Y EVA Capture 3 interrupt CAP4INT 39 INT4 0008h 2.12 0036h Y EVB Capture 4 interrupt CAP5INT 40 2.13 0037h Y EVB Capture 5 interrupt CAP6INT 41 2.14 0038h Y EVB Capture 6 interrupt SPIINT 42 1.7 0005h Y SPI SPI interrupt (low priority) RXINT 43 1.8 0006h Y SCI SCI receiver interrupt (low-priority mode) TXINT 44 INT5 000Ah 1.9 0007h Y SCI SCI transmitter interrupt (low-priority mode) CANMBINT 45 000Ah 1.10 0040h Y CAN CAN mailbox interrupt (low-priority mode) CANERINT 46 1.11 0041h Y CAN CAN error interrupt (low-priority mode) ADCINT 47 1.12 0004h Y ADC ADC interrupt (low priority) XINT1 48 INT6 000Ch 1.13 0001h Y External Interrupt Logic External interrupt pins XINT2 49 000Ch 1.14 0011h Y External Interrupt Logic External interrupt pins (low-priority mode) Reserved 000Eh N/A Y CPU Analysis interrupt TRAP N/A 0022h N/A N/A CPU TRAP instruction Phantom Interrupt Vector N/A N/A 0000h N/A CPU Phantom interrupt vector INT8−INT16 N/A 0010h−0020h N/A N/A CPU Software interrupt vectors† INT20−INT31 N/A 00028h−0003Fh N/A N/A CPU Software interrupt vectors† † See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information. NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details. New peripheral interrupts and vectors with respect to the F243/F241 devices.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers between program memory and data memory. This architecture permits coefficients that are stored in program memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a four-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. See the functional block diagram of the 240xA DSP CPU for more information. TMS320x240xA instruction set The x240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control. For maximum throughput, the next instruction is prefetched while the current one is being executed. Because the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory. addressing modes The TMS320x240xA instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and register. In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each page containing 128 words. Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (AR0−AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively. scan-based emulation TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware- development support. Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx by way of the IEEE 1149.1-compatible (JTAG) interface. The x240xA DSPs do not include boundary scan. The scan chain of these devices is useful for emulation function only.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram of the 2407A DSP CPU Data Bus OSCALE (0−7) D15−D0 A15−A0 1616 ACCL(16)ACCH(16)C CALU(32) 3232 MUX ISCALE (0−16) MUX PREG(32) Multiplier TREG0(16) MUX MUX B1 (256 × 16) B2 (32 × 16) DARAM B0 (256 × 16) DARAM LSB from IR MUX DP(9) MUX 1616 ARAU(16) ARB(3) ARP(3) Program Bus AR7(16) AR6(16) AR5(16) AR3(16) AR2(16) AR1(16) AR0(16) Stack 8 × 16 PC MUX WE RD XTAL2 CLKOUT XTAL1 XINT[1−2] MP/MC RS XF READY STRB R/W PS DS IS Control Data Bus Program Bus Data Bus AR4(16) MUX MUX Data/Prog PSCALE (−6,/hairline 0,/hairline 1,/hairline 4) Data FLASH EEPROM/ ROM MUX MUX NPAR PAR MSTACK Program Control (PCTRL) Memory Map Register IMR (16) IFR (16) GREG (16) Program Bus NOTES: A. See Table 4 for symbol descriptions. B. For clarity, the data and program buses are shown as single buses although they include address and data bits. C. See the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU instruction set information.
36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 4. Legend for the 240xA DSP CPU Internal Hardware as an index value for AR updates of more than one and as a compare value to AR. provides status results to PCTRL. and 1 contain 256 words, while block 2 contains 32 words. form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. the 240xA devices, this register is reserved. IMR individually masks or enables the six core-level interrupts. INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available. output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. signed or unsigned 2s-complement arithmetic multiply. address-generation logic is used to generate sequential addresses in data space. Address Register NPAR holds the program address to be driven out on the PAB in the next cycle. operations scheduled for the current bus cycle. PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
Table 4. Legend for the 240xA DSP CPU Internal Hardware (Continued) routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep. for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction. and restored for subroutines. Figure 10. Organization of Status Registers ST0 and ST1 Table 5. Status Register Field Definitions instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP. LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed. Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. on the status of C. C is set to 1 on a reset.
38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 5. Status Register Field Definitions (Continued) address of 16 bits. DP can be modified by the LST and LDP instructions. Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled. a maskable interrupt trap is taken. overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV. this bit, respectively. LST can also be used to modify the OVM. Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter. and can be loaded by the LST #1 instruction. SXM is set to 1 by reset. instructions can execute based on the condition of TC. by the CLRC XF instruction. XF is set to 1 by reset. functions. The functional block diagram shows the components of the CPU. CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6. Table 6. PSCALE Product-Shift Modes
00 No shift Product feed to CALU or data bus with no shift
01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
128 consecutive multiply/accumulates without the possibility of overflow. from the coefficient table sequentially and step through the data in any of the indirect addressing modes. throw away the oldest sample.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
multiplier (continued) The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high half, then, is loaded using the LPH instruction. central arithmetic logic unit The TMS320x240xA central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier. The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU is always provided from the accumulator, and the other input can be provided from the product register (PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator. The TMS320x240xA devices support floating-point operations for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized — that is, floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of TREG. The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result in overflow.) The CALU can execute a variety of branch instructions that depend on the status of the CALU and the accumulator. These instructions can be executed conditionally based on any meaningful combination of these status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 41POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 central arithmetic logic unit (continued) The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation. The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it. Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the carry bit. The carry bit is set to one on a hardware reset. accumulator The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 16−31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0−15). When the postscaling shifter is used on the low word, the LSBs are zero-filled. The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The 240xA provides a register file containing eight auxiliary registers (AR0−AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers also can be stored in data memory or used as inputs to the CALU. The auxiliary register file (AR0−AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either by ±1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
The TMS320x240xA devices are configured with the following memory modules: /C0068Dual-access random-access memory (DARAM) /C0068Single-access random-access memory (SARAM) /C0068Flash /C0068ROM /C0068Boot ROM dual-access RAM (DARAM) There are 544 words × 16 bits of DARAM on the 240xA devices. The 240xA DARAM allows writes to and reads from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data memory) instructions allow dynamic configuration of the memory maps through software. When using on-chip RAM, the 240xA runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of the 240xA architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY line or on-chip software wait-state generator can be used to interface the 2407A to slower, less expensive external memory. single-access RAM (SARAM) There are 2K words × 16 bits of SARAM on some of the 240xA devices. † The PON and DON bits select SARAM (2K) mapping in program space, data space, or both. See Table 19 for details on the SCSR2 register and the PON and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data spaces. The SARAM (starting at 8000h in program memory) is accessible in external memory space (for 2407A only), if the on-chip SARAM is not enabled. flash EEPROM Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile. However, it has the advantage of “in-target” reprogrammability. The LF2407A incorporates one 32K /C0002 16-bit Flash EEPROM module in program space. The Flash module has multiple sectors that can be individually protected while erasing or programming. The sector size is non-uniform and partitioned as 4K/12K/12K/4K sectors. Unlike most discrete Flash memory, the LF240xA Flash does not require a dedicated state machine, because the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming, the IEEE Standard 1149.1 ‡ (JTAG) scan port provides easy access to the on-chip RAM for downloading the algorithms and Flash code. This Flash requires 5 V for programming (at VCCP pin only) the array. The Flash runs at zero wait state while the device is powered at 3.3 V. ROM The LC240xA devices contain mask-programmable ROM located in program memory space. Customers can arrange to have this ROM programmed with contents unique to any particular application. See Table 1 for the ROM memory capacity of each LC240xA device. † See Table 1 for device-specific features. ‡ IEEE Standard 1149.1−1990, IEEE Standard Test Access Port.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 boot ROM (LF240xA only) Boot ROM is a 256-word ROM memory-mapped in program space 0000−00FF. This ROM will be enabled if the BOOT_EN pin is low during reset. The BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if the BOOT_EN pin is low at reset. Boot ROM can also be enabled by writing 0 to the SCSR2.3 bit and disabled by writing 1 to this bit. The boot ROM has a generic bootloader to transfer code through SCI or SPI ports. The incoming code should disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not be enabled. The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows: /C0068If the SCITXD pin is pulled low, the PLL multiplier is set to 2. /C0068If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default) /C0068If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4. Care should be taken such that a combination of CLKIN and the PLL multiplication factor should not result in a CPU clock speed of greater than 40 MHz, the maximum rated speed. Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI. See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more details about the bootloader operation. flash/ROM security 240xA devices incorporate a security feature that prevents external access to program memory. This feature is useful in preventing unauthorized duplication of proprietary code. If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken: 1. A “dummy” read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word “dummy” indicates that the destination address of this read is insignificant. NOTE: Step 2 is not required if 40h−43h contain 0000 0000 0000 0000h or FFFF FFFF FFFF FFFFh. 2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h, 77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h, 41h, 42h, and 43h (of program memory space), respectively. The device becomes “unsecured” one cycle after the last instruction that unsecures the part. Code Security Module Disclaimer The Code Security Module (“CSM”) included on this device was designed to password protect the data stored in the associated memory (either ROM or Flash) and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI’s published specifications for the warranty period applicable for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
module/signal names would differ. Table 7. Module and Signal Names for EVA and EVB
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
† 2402A devices do not support external direction control. TDIR is not available. Figure 11. Event Manager A Block Diagram
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 general-purpose (GP) timers There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes: /C0068A 16-bit timer, up-/down-counter, TxCNT, for reads or writes /C0068A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes /C0068A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes /C0068A 16-bit timer-control register,TxCON, for reads or writes /C0068Selectable internal or external input clocks /C0068A programmable prescaler for internal or external clock inputs /C0068Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interrupts /C0068A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is selected) The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed. full-compare units There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. programmable deadband generator The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values (from 0 to 16 µs) can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register. PWM waveform generation Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands , and two independent PWMs by the GP-timer compares.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Characteristics of the PWMs are as follows: /C006816-bit registers /C0068Programmable deadband for the PWM output pairs, from 0 to 12 µs /C0068Minimum deadband width of 25 ns /C0068Change of the PWM carrier frequency for PWM frequency wobbling as needed /C0068Change of the PWM pulse widths within and after each PWM period as needed /C0068External-maskable power and drive-protection interrupts /C0068Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms /C0068Minimized CPU overhead using auto-reload of the compare and period registers /C0068The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register. − PDPINTA pin status is reflected in bit 8 of COMCONA register. − PDPINTB pin status is reflected in bit 8 of COMCONB register. capture unit The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits. Capture units include the following features: /C0068One 16-bit capture control register, CAPCONx (R/W) /C0068One 16-bit capture FIFO status register, CAPFIFOx /C0068Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base /C0068Three 16-bit 2-level-deep FIFO stacks, one for each capture unit /C0068Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.] /C0068User-specified transition (rising edge, falling edge, or both edges) detection /C0068Three maskable interrupt flags, one for each capture unit quadrature-encoder pulse (QEP) circuit Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 49POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 input qualifier circuitry An input-qualifier circuitry qualifies the input signal to the CAP1 −6, QEP1 −4, XINT1/2, ADCSOC and PDPINTA/B pins in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. On the LC2402A, input qualification is for the CAP1, CAP2, CAP3, PDPINTA , and XINT2/ADCSOC pins. enhanced analog-to-digital converter (ADC) module A simplified functional block diagram of the ADC module is shown in Figure 12. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include: /C006810-bit ADC core with built-in S/H /C006816-channel, MUXed inputs /C0068Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can be programmed to select any 1 of 16 input channels /C0068Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers) /C0068Sixteen result registers (individually addressable) to store conversion values − The digital value of the input analog voltage is derived by: Digital Value /C00431024 /C0032Input Analog Voltage /C0042VREFLO VREFHI /C0042VREFLO Digital Value = 0 Digital Value = 1023 when input ≤ VREFLO when VREFLO < input < VREFHI when input ≥ VREFHI Note: All fractional values are truncated. /C0068Multiple triggers as sources for the start-of-conversion (SOC) sequence − S/W − software immediate start − EVA − Event manager A (multiple event sources within EVA) − EVB − Event manager B (multiple event sources within EVB) − Ext − External pin (ADCSOC) /C0068Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS /C0068Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize conversions /C0068EVA and EVB triggers can operate independently in dual-sequencer mode /C0068Sample-and-hold (S/H) acquisition time window has separate prescale control NOTE: The calibration and self-test features are not present in 240xA devices.
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
in the ADC module. Figure 12 shows the block diagram of the 240xA ADC module. algorithms. This gives increased resolution over traditional single-sampled conversion results. Figure 12. Block Diagram of the 240xA ADC Module
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
The mailboxes are situated in one 48-word x 16-bit RAM. It can be written to or read by the CPU or the CAN. inserts one wait state for the CPU. Table 8. 3.3-V CAN Transceivers for the TMS320Lx240xA DSPs
40 C to 85 C
† This is the nomenclature printed on the device, since the footprint is too small to accommodate the entire part number. the interrupt bits that are set and clear them after service.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 serial communications interface (SCI) module The 240xA devices include a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. Features of the SCI module include: /C0068Two external pins: − SCITXD: SCI transmit-output pin − SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. /C0068Baud rate programmable to 64K different rates − Up to 2500 Kbps at 40-MHz CPUCLK /C0068Data-word format − One start bit − Data-word length programmable from one to eight bits − Optional even/odd/no parity bit − One or two stop bits /C0068Four error-detection flags: parity, overrun, framing, and break detection /C0068Two wake-up multiprocessor modes: idle-line and address bit /C0068Half- or full-duplex operation /C0068Double-buffered receive and transmit functions /C0068Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. − Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) − Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) /C0068Separate enable bits for transmitter and receiver interrupts (except BRKDT) /C0068NRZ (non-return-to-zero) format /C0068Ten SCI module control registers located in the control register frame beginning at address 7050h NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is acces sed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect. Figure 14 shows the SCI module block diagram.
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 14. Serial Communications Interface (SCI) Module Block Diagram
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 55POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 serial peripheral interface (SPI) module Some 240xA devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include: /C0068Four external pins: − SPISOMI: SPI slave-output/master-input pin − SPISIMO: SPI slave-input/master-output pin − SPISTE: SPI slave transmit-enable pin − SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO, if the SPI module is not used. /C0068Two operational modes: master and slave /C0068Baud rate: 125 different programmable rates/10 Mbps at 40-MHz CPUCLK /C0068Data word length: one to sixteen data bits /C0068Four clocking schemes (controlled by clock polarity and clock phase bits) include: − Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. − Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. − Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. − Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. /C0068Simultaneous receive and transmit operation (transmit function can be disabled in software) /C0068Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. /C0068Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE: All registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. When a register is acce ssed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect.
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 15 is a block diagram of the SPI in slave mode. NOTE A: The diagram is shown in the slave mode. Figure 15. Four-Pin Serial Peripheral Interface Module Block Diagram
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 57POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SPI slave mode operation in LF2403A The LF2403A device does not have the SPISTE/IOPC5 pin. (This function is available as an internal signal only.) The following must be done to put the LF2403A SPI in slave mode: 1. Configure SPISTE /IOPC5 signal for GPIO mode by clearing the MCRB.5 bit. 2. Configure SPISTE /IOPC5 signal as an output (by writing a 1 to bit 13 of PCDATDIR) and drive it low (by writing a 0 to bit 5 of PCDATDIR). Note that SPISTE/IOPC5 should not be driven low until after the SPI is configured and taken out of reset. NOTE: The slave SPISTE/IOPC5 signal must not be driven low until after the master and slave SPI modules are configured and taken out of reset. The initialization sequence is as follows: a. The master SPI is configured first and taken out of reset. This ensures that the master SPICLK is initialized to its appropriate level (high or low, depending on the polarity bit) first, before the slave SPI starts accepting clock pulses. b. The slave SPI is configured and taken out of reset. c. The GPIO/SPI pins of the slave is then configured for SPI operation and the SPISTE /IOPC5 signal is driven low. This is done after ensuring the correct level of the master SPICLK signal. One method of doing this would be to read the level of the SPICLK pin through the PCDATDIR register and then deciding on the appropriate course of action. d. SPI transmission may commence now. Transmission of data should not be attempted until both master and slave are configured and the slave SPISTE /IOPC5 signal is driven low. PLL-based clock module The 240xA has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different CPU clock rates. See Figure 16 for the PLL Clock Module Block Diagram, Table 9 for clock rates, and Table 10 for the loop filter component values. The PLL-based clock module provides two modes of operation: /C0068Crystal-operation This mode allows the use of an external crystal/resonator to provide the time base to the device. /C0068External clock source operation This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the XTAL1/CLKIN pin.
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 16. PLL Clock Module Block Diagram Table 9. PLL Clock Selection Through Bits (11−9) in SCSR1 Register Default multiplication factor after reset is (1,1,1), i.e., 0.5 × Fin. resistance of 30 Ω −150 Ω and draws no more than 1 mW; it should be specified at a load capacitance of 20 pF. TMS320LC2402A DSP Controllers Silicon Errata (literature number SPRZ185) for details on this requirement. pin unconnected as shown in part b of Figure 17.
the proper tank component values that will ensure start-up and stability over the entire operating range. Figure 17. Recommended Crystal/Clock Connection a specified oscillator frequency (XTAL1), see Table 10. Table 10. Loop Filter Component Values With Damping Factor = 2.0 it is reset, or, if it receives an interrupt request.
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
- CPU clock domain − consists of the clock for most of the CPU logic
- System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU. oscillator and WDCLK are also shut down when in IDLE2 mode. System and Peripherals (literature number SPRU357). Table 11. Low-Power Modes Summary Reference Guide: System and Peripherals (literature number SPRU357). 240xA devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, SPI, CAN, EVB, and EVA. Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device. Depending on the application, these peripherals can be turned on/off to achieve low power. See the SCSR1 register for details on the peripheral clock enable bits.
function of a pin or the general-purpose I/O function. /C0068Data and Control Registers — used to control the data and data direction of bidirectional I/O pins. /C0068MUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin. whether the pin is an input (0) or an output (1). is an input, data is read from this bit; if the direction selected is an output, data is written to this bit. The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
01 MUX Control Bit
Figure 18. Shared Pin Configuration A summary of shared pin configurations and associated bits is shown in Table 12.
62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 12. Shared Pin Configurations† † Bold, italicized pin names indicate pin functions at reset. § If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from. ¶ If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output. is reserved in these devices and must be written with a zero. || Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device.
Table 12. Shared Pin Configurations† (Continued) † Bold, italicized pin names indicate pin functions at reset. § If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from. ¶ If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output. is reserved in these devices and must be written with a zero. || Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device. are memory-mapped to the data space. Table 13. Addresses of Digital I/O Control Registers
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
external memory interface (LF2407A) The TMS320LF2407A can address up to 64K × 16 words of memory (or registers) in each of the program, data, and I/O spaces. On-chip memory, when enabled, occupies some of this off-chip range. The CPU of the TMS320LF2407A schedules a program fetch, data read, and data write on the same machine cycle. This is because from on-chip memory, the CPU can execute all three of these operations in the same cycle. However, the external interface multiplexes the internal buses to one address bus and one data bus. The external interface sequences these operations to complete first the data write, then the data read, and finally the program read. The LF2407A supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address and data buses, along with the PS , DS, and IS space-select signals, allow addressing of 64K 16-bit words in program, data, and I/O space. Since on-chip peripheral registers occupy positions of data-memory space (7000−7FFF), the externally addressable data-memory space is 32K 16-bit words (8000−FFFF). Note that the global memory space of the C2xx core is not used for 240xA DSP devices. Therefore, the global memory allocation register (GREG) is reserved for all these devices. Input/output (I/O) design is simplified by having I/O space treated the same way as memory. I/O devices are accessed in the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices. The LF2407A external parallel interface provides various control signals to facilitate interfacing to the device. The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal provides a timing reference for all external cycles. For convenience, the device also provides the RD and the WE output signals, which indicate a read cycle and a write cycle, respectively, along with timing information for those cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to the LF2407A. The 2407A provides RD and W/R signals to help the zero-wait-state external memory interface. At higher CLKOUT speeds, RD may not meet the slow memory device’s timing. In such instances, the W/R signal could be used as an alternative signal with some tradeoffs. See the timing parameters for details. The TMS320LF2407A supports zero-wait-state reads on the external interface. However, to avoid bus conflicts, writes take two cycles. This allows the TMS320LF2407A to buffer the transition of the data bus from input to output (or from output to input) by a half cycle. In most systems, the TMS320LF2407A ratio of reads to writes is significantly large to minimize the overhead of the extra cycle on writes. wait-state generation (LF2407A only) Wait-state generation is incorporated in the LF2407A without any external hardware for interfacing the LF2407A with slower off-chip memory and I/O devices. Adding wait states lengthens the time the CPU waits for external memory or an external I/O port to respond when the CPU reads from or writes to that external memory or I/O port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states operate on CLKOUT cycle boundaries. To avoid bus conflicts, writes from the LF2407A always take at least two CLKOUT cycles. The LF2407A offers two options for generating wait states: /C0068READY Signal. With the READY signal, you can externally generate any number of wait states. The READY pin has no effect on accesses to internal memory. /C0068On-Chip Wait-State Generator. With this generator, you can generate zero to seven wait states.
TMS320LF2407A,/thinTMS320LF2406A,/thinTMS320LF2403A,/thinTMS320LF2402A TMS320LC2406A,/figureTMS320LC2404A,/figureTMS320LC2403A,/figureTMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 65POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 generating wait states with the READY signal When the READY signal is low, the LF2407A waits one CLKOUT cycle and then checks READY again. The LF2407A does not continue executing until the READY signal is driven high; therefore, if the READY signal is not used, it should be pulled high. The READY pin can be used to generate any number of wait states. However, when the LF2407A operates at full speed, it may not respond fast enough to provide a READY-based wait state for the first cycle. For extended wait states using external READY logic, the on-chip wait-state generator should be programmed to generate at least one wait state. generating wait states with the LF2407A on-chip software wait-state generator The software wait-state generator can be programmed to generate zero to seven wait states for a given off-chip memory space (program, data, or I/O), regardless of the state of the READY signal. These zero to seven wait states are controlled by the wait-state generator register (WSGR) (I/O FFFFh). For more detailed information on the WSGR and associated bit functions, see the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357). watchdog (WD) timer module The x240xA devices include a watchdog (WD) timer module. The WD function of this module monitors software and hardware operation by generating a system reset if it is not periodically serviced by software by having the correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following: /C0068WD Timer − Seven different WD overflow rates − A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and generates a system reset if an incorrect value is written to the register − WD check bits that initiate a system reset if an incorrect value is written to the WD control register (WDCR) /C0068Automatic activation of the WD timer, once system reset is released − Three WD control registers located in control register frame beginning at address 7020h. NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte is read as zeros. Writing to the upper byte has no effect. Figure 19 shows the WD block diagram. Table 14 shows the different WD overflow (time-out) selections. The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of to the WDDIS pin of the TMS320F243/241 devices.
66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
† Writing to bits WDCR.5−3 with anything but the correct pattern (101) generates a system reset. Figure 19. Block Diagram of the WD Module
Table 14. WD Overflow (Time-out) Selections implementations, and fully integrate and debug software and hardware modules. on pricing and availability, contact the nearest TI field sales office or authorized distributor. Table 15. Development Support Tools PC is a trademark of International Business Machines Corp.. Code Composer Studio, XDS510, and XDS510PP are trademarks of Texas Instruments.
68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 16. TMS320x24x-Specific Development Tools engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). of the device have been demonstrated fully. TI’s standard warranty applies. TMS320 is a trademark of Texas Instruments. eZdsp is a trademark of Spectrum Digital, Inc.
expected end-use failure rate still is undefined. Only qualified production devices are to be used. options that are available on 240xA devices. Figure 20. TMS320x240xA Device Nomenclature
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s guides for all devices and development support tools; and hardware and software applications. Useful reference documentation includes: /C0068User Guides − TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) − Manual Update Sheet for TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (SPRU357) [literature number SPRZ015] − TMS320C240 DSP Controllers CPU, System, and Instruction Set Reference Guide (literature number SPRU160) /C0068Data Sheets − TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers (literature number SPRS145) − TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP Controllers (literature number SPRS094) − TMS320LF2401A DSP Controller (literature number SPRS161) /C0068Application Reports − 3.3-V DSP for Digital Motor Control (literature number SPRA550) To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com. To send comments regarding this TMS320x240xA data sheet (literature number SPRS145), use the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 71POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 LF240xA AND LC240xA ELECTRICAL SPECIFICATIONS DATA absolute maximum ratings over operating free-air temperature ranges (unless otherwise noted)† † Clamp current stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to V SS. 2. Long −term high−temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see the IC Package Thermal Metrics Application Report (literature number SPRA953) and the Reliability Data for TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963). recommended operating conditions‡§ MIN NOM MAX UNIT VDD/VDDO Supply voltage VDDO = VDD ± 0.3 V 3 3.3 3.6 V VSS Supply ground 0 0 0 V PLLVCCA PLL supply voltage 3 3.3 3.6 V VCCA¶ ADC supply voltage 3 3.3 3.6 V VCCP Flash programming supply voltage# 4.75 5 5.25 V fCLKOUT Device clock frequency (system clock) 2 40 MHz V || High level input voltage All inputs 2 V 03 VVIH|| High-level input voltage All inputs 2 VDD + 0.3 V V Low level input voltage All inputs 08 VVIL Low-level input voltage All inputs 0.8 V Output pins Group 1/C0107 − 2 mA IOH High-level output source current, VOH = 2.4 V Output pins Group 2/C0107 − 4 mAIOH High level output source current, VOH 2.4 V Output pins Group 3/C0107 − 8 mA Output pins Group 1/C0107 2 mA IOL Low-level output sink current, VOL = VOL MAX Output pins Group 2/C0107 4 mAIOL Low level output sink current, VOL V OL MAX Output pins Group 3/C0107 8 mA T Free air temperature A version − 40 85 °CTA Free-air temperature S version − 40 125 °C TJ Junction temperature − 40 25 150 °C Nf Flash endurance for the array (Write/erase cycles) − 40°C to 85°C 10K cycles ‡ See the mechanical data package page for thermal resistance values, ΘJA (junction-to-ambient), ΘJC (junction-to-case), and Ψjt (junction-to-top of case) § The drive strengths of the EVA PWM pins and the EVB PWM pins are not identical. ¶ VCCA should not differ from VDD by more than 0.3 V. # For applications that involve millions of power cycles, it is recommended that VCCP be powered after VDD. || The input buffers used in 240x/240xA are not 5-V compatible. /C0107Primary signals and their groupings: Group 1: PWM1 −PWM6, T1PWM, T2PWM, CAP1−CAP6, TCLKINA, IOPF6, IOPC1, TCK, TDI, TMS, XF, A0−A15, RS Group 2: PS /DS/IS, RD, W/R, STRB, R/W, VIS_OE, D0−D15, T3PWM, T4PWM, PWM7−PWM12, CANTX, CANRX, SPICLK, SPISOMI, SPISIMO, SPISTE, EMU0, EMU1, TDO, TMS2 Group 3: TDIRA, TDIRB, SCIRXD, SCITXD, XINT1, XINT2, CLKOUT, TCLKINB
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating free-air temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V High level output voltage VDD = 3.0 V, IOH = IOHMAX 2.4 VDDO VVOH High-level output voltage All outputs at 50 µA VDDO − 0.2 V VOL† Low-level output voltage IOL = IOLMAX 0.4 V I Input current (low level) With pullup V 33 V V 0 V −10 −16 −30 AIIL Input current (low level) With pulldown VDD = 3.3 V, VIN = 0 V ±2 µA I Input current (high level) With pullup V 33 V V V AIIH Input current (high level) With pulldown VDD = 3.3 V, VIN = VDD 10 16 30 µA IOZ Leakage current, high-impedance state (off-state) VO = VDD or 0 V ±2 µA Ci Input capacitance 2 pF Co Output capacitance 3 pF † For group 3 pins, VOL could be up to 0.6 V, when output source current is 8 mA. current consumption by power-supply pins over recommended operating free-air temperature ranges at 40-MHz CLOCKOUT PARAMETER TEST CONDITIONS DEVICE MIN TYP MAX UNIT A test code running in B0 RAM does the LF2407A 95 120 mA A test code running in B0 RAM does the following: LF2406A 95 120 mAfollowing: 1. Enables clock to all peripherals.
2 Toggles all PWM outputs at 20 kHz
I † Operational Current 2. Toggles all PWM outputs at 20 kHz. 3. Performs a continuous conversion of all LF2402A 85 110 mA IDD† Operational Current 3. Performs a continuous conversion of all ADC channels.
4 An infinite loop which transmits a character
- An infinite loop which transmits a character out of SCI and executes MACD instructions. LC2404A 85 110 mAout of SCI and executes MACD instructions. NOTE: All I/O pins are floating LC2403A 75 95 mA NOTE: All I/O pins are floating. LC2402A 75 95 mA LF2407A 10 22 mA LF2406A 10 22 mA LF2403A 10 22 mA ICCA ADC module current LF2402A 10 22 mA ICCA ADC module current LC2406A 10 22 mA LC2404A 10 22 mA LC2403A 10 22 mA LC2402A 10 22 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 73POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2407A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 70 80 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA IDD† Operational Current LPM2 Clock to all peripherals is disabled. Flash is powered down 200 400 µA ICCA ADC module current LPM2 Flash is powered down. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator. current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2406A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 70 80 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA IDD† Operational Current LPM2 Clock to all peripherals is disabled. Flash is powered down 200 400 µA ICCA ADC module current LPM2 Flash is powered down. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator. current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2403A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 70 80 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA IDD† Operational Current LPM2 Clock to all peripherals is disabled. Flash is powered down 200 400 µA ICCA ADC module current LPM2 Flash is powered down. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2402A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 60 70 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA IDD† Operational Current LPM2 Clock to all peripherals is disabled. Flash is powered down 200 400 µA ICCA ADC module current LPM2 Flash is powered down. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator. current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2406A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 50 70 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA I † Operational Current −40°C to 85°C 20 200 µA IDD† Operational Current LPM2 −40°C to 125°C 20 400 µA ICCA ADC module current LPM2 Clock to all peripherals is disabled. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator. current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2404A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 50 70 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA I † Operational Current −40°C to 85°C 20 200 µA IDD† Operational Current LPM2 −40°C to 125°C 20 400 µA ICCA ADC module current LPM2 Clock to all peripherals is disabled. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 75POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2403A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 50 70 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA I † Operational Current −40°C to 85°C 20 200 µA IDD† Operational Current LPM2 −40°C to 125°C 20 400 µA ICCA ADC module current LPM2 Clock to all peripherals is disabled. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator. current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2402A) PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT IDD† Operational Current LPM0 Clock to all peripherals is enabled. 40 60 mA ICCA ADC module current LPM0 Clock to all peripherals is enabled. No I/O pins are switching. 10 22 mA IDD† Operational Current LPM1 Clock to all peripherals is disabled. 35 45 mA ICCA ADC module current LPM1 Clock to all peripherals is disabled. No I/O pins are switching. 0 0 mA I † Operational Current −40°C to 85°C 20 200 µA IDD† Operational Current LPM2 −40°C to 125°C 20 400 µA ICCA ADC module current LPM2 Clock to all peripherals is disabled. Input clock is disabled.‡ 0 0 mA † IDD is the current flowing into the VDD, VDDO, and PLLVCCA pins. ‡ If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 21. LF2407A Typical Current Consumption (With Peripheral Clocks Enabled) Figure 22. LC2406A Typical Current Consumption (With Peripheral Clocks Enabled) Instruction Set Reference Guide (literature number SPRU160).
Figure 23. Emulator Connection Without Signal Buffering for the DSP Peripherals (literature number SPRU357) for further information on how to turn off the clock to the peripherals. Table 17. Typical Current Consumption by Various Peripherals (at 40 MHz) † This number represents the current drawn by the digital portion of the ADC module. by the analog portion of the ADC (ICCA) as well.
78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 24. Test Load Circuit level of 2.4 V and to a maximum logic-low level of 0.4 V. Figure 25 shows output levels.
0.4 V (VOL)
2.4 V (VOH)
Figure 25. Output Levels Figure 26 shows the input levels.
0.8 V (VIL)
2.0 V (VIH)
Figure 26. Input Levels
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 79POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Input transition times are specified as follows: /C0068For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower. /C0068For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher. PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A A[15:0] MS Memory strobe pins IS , DS, or PS Cl XTAL1/CLKIN R READY CO CLKOUT RD Read cycle or RD D D[15:0] RS RESET pin RS INT XINT1, XINT2 W Write cycle or WE Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don’t care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) general notes on timing All output signals from the 240xA devices (including CLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this data sheet.
80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
† Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum. † Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum. Figure 27. CLKIN-to-CLKOUT Timing with PLL and External Clock in ×4 Mode
† During power-on reset, the device can continue to hold the RS pin low for another 128 CLKIN cycles. B. XTAL1 refers to the internal oscillator clock if on-chip oscillator is used. C. t OSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design. or pulldowns will always sink/source a small amount of current once powered. Figure 28. Power-on Reset (See Note A) XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital. XDS510 and XDS510PP, are trademarks of Texas Instruments.
82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
† XTAL1 refers to internal oscillator clock if on-chip oscillator is used. Figure 29. Warm Reset
† The parameter tw(RSL1) refers to the time RS is an output. † XTAL1 refers to internal oscillator clock if on-chip oscillator is used. Figure 30. Watchdog Initiated Reset
84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
† WAKE INT can be any valid interrupt or RESET. Figure 31. IDLE1 Entry and Exit Timing − LPM0 † WAKE INT can be any valid interrupt or RESET. Figure 32. IDLE2 Entry and Exit Timing − LPM1 Figure 33. HALT Mode − LPM2
‡ This is different from 240x devices. † tOSC is the oscillator start-up time. ‡ CLKOUT frequency after LPM2 wakeup will be the same as that upon entering LPM2 (x4 shown as an example). § PDPINTx interrupt vector, if PDPINTx interrupt is enabled. ¶ If PDPINTx interrupt is disabled. Figure 34. LPM2 Wakeup Using PDPINTx
86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 35. XF and BIO Timing
88 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
CAP refers to all QEP and capture input pins. † This is different from 240x devices. Figure 38. Capture Input and QEP Timing
INT refers to XINT1 and XINT2. PDP refers to PDPINTx. † This is different from 240x devices. high depends on the state of the FCOMPOE bit. Figure 39. External Interrupts Timing
90 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 40. General-Purpose Output Timing Figure 41. General-Purpose Input Timing
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 •91 SPI MASTER MODE TIMING PARAMETERS SPI master mode timing information is listed in the following tables. SPI master mode external timing parameters (clock phase = 0)†‡ (see Figure 42) NO. SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 UNITNO. MIN MAX MIN MAX UNIT 1 tc(SPC)M Cycle time, SPICLK 4tc(CO) 128tc(CO) 5tc(CO) 127tc(CO) ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) ns2§ tw(SPCL)M Pulse duration, SPICLK low ns tw(SPCL)M Pulse duration, SPICLK low ns3§ tw(SPCH)M Pulse duration, SPICLK high ns td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO valid (clock polarity = 0) − 10 10 − 10 10 ns4§ td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO valid (clock polarity = 1) − 10 10 − 10 10 ns tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity =0) 0.5tc(SPC)M −10 0.5tc(SPC)M +0.5tc(CO) −10 ns5§ tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity =1) 0.5tc(SPC)M −10 0.5tc(SPC)M +0.5tc(CO) −10 ns tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) 0 0 ns8§ tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) 0 0 ns tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.25tc(SPC)M −10 0.5tc(SPC)M −0.5tc(CO) −10 ns9§ tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.25tc(SPC)M −10 0.5tc(SPC)M −0.5tc( C O )−10 ns † The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. ‡ tc = system clock cycle time = 1/CLKOUT = tc(CO) § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
92 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
communication stream is complete. Figure 42. SPI Master Mode External Timing (Clock Phase = 0)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 •93 SPI master mode external timing parameters (clock phase = 1)†‡ (see Figure 43) NO. SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 UNITNO. MIN MAX MIN MAX UNIT 1 tc(SPC)M Cycle time, SPICLK 4tc(CO) 128tc(CO) 5tc(CO) 127tc(CO) ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) ns2§ tw(SPCL)M Pulse duration, SPICLK low ns tw(SPCL)M Pulse duration, SPICLK low ns3§ tw(SPCH)M Pulse duration, SPICLK high ns tsu(SIMO-SPCH)M Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0) 0.5tc(SPC)M −10 0.5tc(SPC)M −10 ns6§ tsu(SIMO-SPCL)M Setup time, SPISIMO data valid before SPICLK low (clock polarity = 1) 0.5tc(SPC)M −10 0.5tc(SPC)M −10 ns tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity =0) 0.5tc(SPC)M −10 0.5tc(SPC)M −10 ns7§ tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity =1) 0.5tc(SPC)M −10 0.5tc(SPC)M −10 ns 10§ tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0 0 ns10§ tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0 0 ns 11§ tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 0.25tc(SPC)M −10 0.5tc(SPC)M −10 ns11§ tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.25tc(SPC)M −10 0.5tc(SPC)M −10 ns † The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. ‡ tc = system clock cycle time = 1/CLKOUT = tc(CO) § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
communication stream is complete. Figure 43. SPI Master Mode External Timing (Clock Phase = 1)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 95POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SPI slave mode timing parameters Slave mode timing information is listed in the following tables. SPI slave mode external timing parameters (clock phase = 0) †‡ (see Figure 44) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(CO)‡ ns 13§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S 13§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 14§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S 14§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 15§ td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 0.375tc(SPC)S−10 ns15§ td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 0.375tc(SPC)S−10 ns 16§ tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity =0) 0.75tc(SPC)S 16§ tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity =1) 0.75tc(SPC)S ns 19§ tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0 19§ tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0 ns 20§ tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S ns20§ tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S ns † The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. ‡ tc = system clock cycle time = 1/CLKOUT = tc(CO) § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
the SPI communication stream is complete. Figure 44. SPI Slave Mode External Timing (Clock Phase = 0)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 97POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SPI slave mode timing parameters (continued) SPI slave mode external timing parameters (clock phase = 1) †‡ (see Figure 45) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 8tc(CO) ns 13§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S ns13§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 14§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S ns14§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 17§ tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns17§ tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S ns 18§ tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0.75tc(SPC)S ns18§ tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0.75tc(SPC)S ns 21§ tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0 ns21§ tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0 ns 22§ tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S ns22§ tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S ns † The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set. ‡ tc = system clock cycle time = 1/CLKOUT = tc(CO) § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
the SPI communication stream is complete. Figure 45. SPI Slave Mode External Timing (Clock Phase = 1)
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 99POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 external memory interface read timing switching characteristics over recommended operating conditions for an external memory interface read at 40 MHz [H = 0.5t c(CO)] (see Figure 46) PARAMETER MIN MAX UNIT td(COL-CNTL) Delay time, CLKOUT low to control valid 4 ns td(COL-CNTH) Delay time, CLKOUT low to control inactive 5 ns td(COL-A)RD Delay time, CLKOUT low to address valid 8 ns td(COH-RDL) Delay time, CLKOUT high to RD strobe active 5 ns td(COL-RDH) Delay time, CLKOUT low to RD strobe inactive high −8 1 ns td(COL-SL) Delay time, CLKOUT low to STRB strobe active low 5 ns td(COL-SH) Delay time, CLKOUT low to STRB strobe inactive high 6 ns td(WRN) Delay time, W/R going low to R/W rising 5 ns th(A)COL Hold time, address valid after CLKOUT low 2 ns tsu(A)RD Setup time, address valid before RD strobe active low H − 7 ns th(A)RD Hold time, address valid after RD strobe inactive high 0 ns timing requirements [H = 0.5tc(CO)] (see Figure 46) MIN MAX UNIT ta(A) Access time, read data from address valid 2H −10 ns ta(RD) Access time, read data from RD low H − 7 ns tsu(D)RD Setup time, read data before RD strobe inactive high 8 ns th(D)RD Hold time, read data after RD strobe inactive high 0 ns th(AIV-D) Hold time, read data after address invalid 0 ns
100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 46. Memory Interface Read/Read Timings
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 101POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 external memory interface write timing switching characteristics over recommended operating conditions for an external memory interface write at 40 MHz [H = 0.5t c(CO)] (see Figure 47) PARAMETER MIN MAX UNIT td(COH-CNTL) Delay time, CLKOUT high to control valid 4 ns td(COH-CNTH) Delay time, CLKOUT high to control inactive 5 ns td(COH-A)W Delay time, CLKOUT high to address valid 10 ns td(COH-RWL) Delay time, CLKOUT high to R/W low 6 ns td(COH-RWH) Delay time, CLKOUT high to R/W high 6 ns td(COL-WL) Delay time, CLKOUT low to WE strobe active low 6 ns td(COL-WH) Delay time, CLKOUT low to WE strobe inactive high 6 ns ten(D)COL Enable time, data bus driven from CLKOUT low −3 ns td(COL-SL) Delay time, CLKOUT low to STRB active low 6 ns td(COL-SH) Delay time, CLKOUT low to STRB inactive high 6 ns td(WRN) Delay time, R/W rising to W/R going low 5 ns th(A)COLW Hold time, address valid after CLKOUT low −5 ns tsu(A)W Setup time, address valid before WE strobe active low H−9 ns tsu(D)W Setup time, write data before WE strobe inactive high 2H−17 ns th(D)W Hold time, write data after WE strobe inactive high 2 ns tdis(W-D) Disable time, data bus high impedance from WE high 5 ns
102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
driven. CLKOUT is to be used along with VIS_OE for trace capabilities. Figure 47. Memory Interface Write/Write Timings
† The WSGR register must be programmed before the READY pin can be used. See the READY pin description for more details. Figure 48. Ready-on-Read Timings
104 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 49. Ready-on-Read Timings With One Software Wait (SW) State and
Figure 50. Ready-on-Write Timings
106 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 51. Ready-on-Write Timings With One Software Wait (SW) State and
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 107POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 10-bit analog-to-digital converter (ADC) The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA. The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic circuitry that can be present on V SS and VCC from coupling into the ADC analog stage. All ADC specifications are given with respect to VSSA unless otherwise noted. recommended operating conditions MIN NOM MAX UNIT VCCA Analog supply voltage 3.0 3.3 3.6 V VSSA Analog ground 0 V VREFHI Analog supply reference source† ‡ VCCA V VREFLO Analog ground reference source† VSSA V VAI Analog input voltage, ADCIN00−ADCIN07 VREFLO VREFHI V † VREFHI and VREFLO must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time. ‡ VREFHI can be from 2.0 V to VCCA; however, the accuracy of the ADC depends on the ground bounce and noise on the target board. ADC operating frequency MIN MAX UNIT ADC operating frequency 4 30 MHz
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
108 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
10-bit analog-to-digital converter (ADC) (continued) operating characteristics over recommended operating condition ranges † PARAMETER DESCRIPTION MIN TYP MAX UNIT VCCA = 3.3 V 10 22 mA ICCA Analog supply current VCCA = VREFHI = 3.3 V PLL or OSC power down 1 µA IADREFHI VREFHI input current 0.75 1.5 mA IADCIN Analog input leakage 1 µA C Analog input capacitance Typical capacitive load on Non-sampling 10 pFCai Analog input capacitance Typical capacitive load on analog input pin Sampling 30 pF td(PU) Delay time, power-up to ADC valid Time to stabilize analog stage after power-up 10 µs ZAI Analog input source impedance Analog input source impedance needed for conversions to remain within specifications at min tw(SH) 53 10 Ω Zero-offset error /C00342 LSB † Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. EDNL and EINL PARAMETER DESCRIPTION CLKOUT MIN MAX UNIT EDNL‡ Differential nonlinearity error Difference between the actual step width and the ideal value 30 MHz /C00342 LSB EINL‡ Integral nonlinearity error Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error
30 MHz /C00342 LSB
‡ Test conditions: VREFHI = VCCA , VREFLO = VSSA
Guide: System and Peripherals (literature number SPRU357) for more details. ‡ The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC). Figure 52. Analog-to-Digital Internal Module Timing
110 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
† TI releases upgrades to the Flash algorithms for these devices; hence, these typical values are subject to change. could also impact the timing parameters. Table 18 outlines the differences between the LF240xA (Flash) devices and the LC240xA (ROM) devices. Table 18. Differences Between LF240xA (Flash) Devices and LC240xA (ROM) Devices § The SPISTE pin is not available on the LF2403A. See the SPI Slave Mode Operation in LF2403A section. ¶ Application code should NOT access Illegal/Reserved addresses.
- Access to external Program, Data, and I/O space is considered illegal and would assert an NMI.
- The external Program and I/O spaces are implemented as “reserved” addresses and any access will not assert an NMI. However,
the external data memory space is illegal.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 111POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 migrating from 240x devices to 240xA devices This section highlights the new features/migration issues of the 240xA devices (as compared to the 240x family) and describes the impact these features/issues have on user applications. maximum clock speed 240xA devices can operate at a maximum speed of 40 MHz compared to the 30-MHz operation of 240x devices. This change in clock speed warrants a change in the register contents of all the peripherals. For example, to maintain the same baud rate, the divisor values that are loaded to the SPI, SCI, and CAN registers must be recalculated. code security module 240xA devices incorporate a “code security module” which protects the contents of program memory from unauthorized duplication. Passwords stored in password locations (PWL) 0040h to 0043h are used for this purpose. Even if the code is not secured with passwords (i.e., PWL contains FFFFFFFFFFFFFFFFh), the PWL must still be read to gain access to the program memory contents. Note that locations 0040h to 0043h were available for user code in the 240x devices, which lack the “code security module”. In 240xA devices, these locations are reserved for the passwords and are not available for the user code. Even if code security feature is not used, these locations must be written with all ones. This fact must be borne in mind while submitting ROM codes to TI. input-qualifier circuitry An input-qualifier circuitry qualifies the input signal to the CAP1–6 (QEP1 −4), XINT1/2, ADCSOC, and PDPINTA/B pins in the x240xA devices. The state of the internal input signal will change only after these pins are high/low for 6 (12) clock edges. The user must hold the pin high/low for 6 (12) cycles to ensure that the device see the level change. The increase in the pulse width of the signals used to excite these pins must be taken into account while migrating from the 240x to the 240xA family. Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. This bit is a “reserved” bit in 240x devices. status of the PDPINTx pin The current status of the PDPINTx pins is now reflected in bit 8 of the COMCONx registers. This bit is a “reserved” bit in 240x devices. operation of the IOPC0 pin At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A), W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register) is reserved in these devices and must be written with a zero. external pulldown resistor for TRST pin An external pulldown resistor may be needed for the TRST pin in boards that operate in noisy environments. Refer to the TRST pin description for more details.
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
112 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
migrating from LF240x devices to LC240xA devices When migrating from an “unsecured” Flash device (LF240x) to a “secured” ROM device (LC240xA), two migration paths have to be taken into consideration: /C0068Migrating from a 240x device to a 240xA device (see the Migrating From 240x Devices to 240xA Devices section) /C0068Migrating from a Flash (LF) device to a ROM (LC) device (see the Migrating From LF240xA (Flash) Devices to LC240xA (ROM) Devices section)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description Indicates change with respect to the F243/F241, C242 device register maps.
114 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued) Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
116 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
118 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
120 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
122 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
124 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps.
Indicates change with respect to the F243/F241 C242 device register mapsIndicates change with respect to the F243/F241, C242 device register maps. † Register shown with bits set in register mode.
126 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 20. Typical Thermal Resistance Characteristics Table 21. Typical Thermal Resistance Characteristics Table 22. Typical Thermal Resistance Characteristics Table 23. Typical Thermal Resistance Characteristics
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 127POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA (CONTINUED) The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s).
www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DHDLF2406APZA NRND LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA TMS LF2406APZA-GREE NRND LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA TMS TMS320LF2402APGA NRND QFP PG 64 66 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 85 320LF2402APGA TMS TMS320LF2402APGAR NRND QFP PG 64 400 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 85 320LF2402APGA TMS TMS320LF2402APGS NRND QFP PG 64 66 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 125 320LF2402APGS TMS TMS320LF2403APAG4 NRND TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LF2403APAGA TMS320 TMS320LF2403APAGA NRND TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LF2403APAGA TMS320 TMS320LF2403APAGS NRND TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 LF2403APAGS TMS320 TMS320LF2406APZA NRND LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA TMS TMS320LF2406APZAG4 NRND LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA TMS TMS320LF2406APZAR NRND LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 320LF2406APZA TMS TMS320LF2406APZS NRND LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 320LF2406APZS TMS TMS320LF2407APGEA NRND LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 320LF2407APGEA TMS TMS320LF2407APGEG4 NRND LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 320LF2407APGEA TMS TMS320LF2407APGES NRND LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 320LF2407APGES TMS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
www.ti.com 15-Apr-2017 Addendum-Page 2 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/C 10/96 0,27 0,17 0,13 NOM 0,25 0,75 0,45 0,05 MIN Seating Plane Gage Plane 108 109 144 SQ SQ22,20 21,80 19,80 17,50 TYP 20,20 1,35 1,45 1,60 MAX M0,08 0°–7° 0,08 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
MQFP008 – JULY 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PG (R-PQFP-G64) PLASTIC QUAD FLATPACK 4040101/B 03/95 0,15 NOM 18,0014,20 13,80 17,20 12,00 TYP 0,25 1,10 0,70 0,10 MIN Gage Plane 18,00 TYP 23,20 24,00 19,80 20,20 3,10 MAX 2,70 TYP 0,25 0,45 0°–10° Seating Plane 0,10 1,00 M0,20 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149/B 11/96 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 12,00 TYP 0,17 100 SQ SQ15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0°–7° Seating Plane 0,08 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 4040282/C 11/96 Gage Plane 0,17 0,27 7,50 TYP SQ 9,80 1,05 0,95 11,80 12,20 1,20 MAX 10,20 SQ 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS”AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non- compliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated