LDO40L STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: STMICROELECTRONICS
  • PDF pages: 25

Technical content

Datasheet sections

  • 1 Block diagram
  • 2 Pin configuration
  • 3 Typical application diagram
  • 4 Absolute maximum ratings
  • 5 Electrical characteristics
  • 6 Application information
  • 6.1 Operating input voltage
  • 6.2 Output voltage adjustment
  • 6.3 Output voltage sense pin
  • 6.4 Protection features
  • 6.5 Enable pin
  • 6.6 Input and output capacitors
  • 7 Typical characteristics
  • 8 Package information
  • 8.1 DFN6 (3x3) package information
  • 8.2 DFN6 (3x3) tape and reel mechanical data
  • 9 Ordering information

Features

  • AEC-Q100 qualified
  • Low quiescent current: typ. 45 µA at no load
  • Wide input voltage operating range up to 38 V
  • Low startup voltage: 3.5 V
  • Output current up to 400 mA
  • Output voltage accuracy: – ± 3% (including line, load and temperature variation)
  • Ultra low-dropout: – 36 mV @ 100 mA load current – 140 mV @ 400 mA load current
  • High PSRR: 70 dB @ 1 kHz
  • Very low noise: 20 µV RMS/VOUT
  • Protection features: current limitation, thermal shutdown
  • -40 °C to +125 °C operating temperature range
  • Package: DFN6 (3x3) (wettable flanks)

Applications

  • Automotive applications
  • Body control modules
  • Instruments and clusters
  • Automotive LED lighting

Description

The LDO40L is a 400 mA LDO regulator, designed for being used in severe automotive environments. Low quiescent current makes it suitable for applications permanently connected to battery. This feature is especially critical when electronic modules remain in active mode when ignition is off. The LDO40L embeds protection functions, such as: current limit and thermal shutdown. The extended input voltage range, low drop voltage and low quiescent current features make it suitable also for low power industrial and consumer applications. Maturity status link LDO40L 400 mA, 38 V low-dropout regulator, with 45 μA quiescent current LDO40L Datasheet DS12711 - Rev 3 - February 2020 For further information contact your local STMicroelectronics sales office.

1 Block diagram

Figure 1. Block diagram, fixed version Figure 2. Block diagram, adjustable version

2 Pin configuration

Figure 3. Pin configuration (marking view) Table 1. Pin description

3 Typical application diagram

Figure 4. Typical application diagram (fixed versions) Figure 5. Typical application diagram (adjustable versions)

4 Absolute maximum ratings

Table 2. Absolute maximum ratings operation under these conditions is not implied. All values are referred to GND. Table 3. Thermal data Note: R thJA for DFN6 based on a 4-layer JEDEC PCB (2S2P) test board with 2 thermal vias.

5 Electrical characteristics

Unless otherwise specified: TJ = -40 to 125 °C; VIN = 13.2 V, VOUT = 5 V, VEN = 5 V, IOUT = 1 mA; CIN = COUT = 1 µF; Typical values referred to TA = 25 °C. Table 4. Electrical characteristics

Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit IQ Quiescent current IOUT = 400 mA µA80 140 Shutdown current VEN = 0 V, VIN = 13.2 V 0.2 2.2 µA IADJ Adjustable input current 1 µA ISC Short-circuit current VIN = 6 V, VOUT = 0 V 1.2 1.6 A VEN Enable input logic low, VEN-L 0.65 V Enable input logic high, VEN-H 2.7 IEN Enable pin input current VIN = 6 V, VEN = 5 V 0.5 1.5 µA TSHDN Thermal shutdown 175 Hysteresis 25 1. V IN-MIN = VOUT + VDROP or 5 V, whichever is greater. 2. V IN = VOUT + 1 V or 5 V, whichever is greater. 3. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. LDO40L

6 Application information

6.1 Operating input voltage

The LDO40L is a low-dropout linear voltage regulator equipped with a low-RDS-(on) P-channel MOSFET used as a pass-element. The device internal circuits are able to start with an input voltage as low as 3.5 V, whatever is the nominal output voltage (see Figure 22. Output voltage vs. input voltage (no load). Defined the desired output voltage VOUT-NOM, the minimum input voltage VIN-MIN needed to fully bias the pass-element, is VIN-MIN = VOUT-NOM + VDROP. This allows to exit the dropout condition and achieve output voltage regulation. The full regulation performance guaranteed by Section 5 Electrical characteristics in terms of output accuracy and tolerance versus line and load changes is achieved for the highest input voltage among VIN-MIN = VOUT-NOM + 1 V and VIN-MIN = 5 V . At input voltages lower than VIN-MIN = (VOUT-NOM + VDROP) the regulator enters dropout condition, regulation is not guaranteed and the output voltage tracks the input except for a voltage depending on the load current (IOUT) and the pass-element resistance (see Figure 22. Output voltage vs. input voltage (no load). This tracking behavior can be useful during cold crank conditions.

6.2 Output voltage adjustment

The LDO40LY is available in fixed and adjustable output voltage versions. The latter option is usually chosen when the output voltage has to be set to non-standard values. In the adjustable version, the output voltage can be set from 2.5 V up to 11 V, by connecting a resistor divider between the ADJ pin and the output. The architecture of the LDO40LY features a precise bandgap reference, which generates a fixed voltage VREF = 1.2 V between VOUT and ADJ terminals (refer to Figure 2. Block diagram, adjustable version and Figure 5. Typical application diagram (adjustable versions) ). When the R1-R2 resistor divider is connected, a fixed current is generated through the divider. Since the contribution of current sourced by the ADJ pin is negligible (few tens of nA), the resulting output voltage is obtained by using the following equation: V O U T = V RE F 1 + R 2 / R 1 , w i t ℎ V RE F = 1.2 V t yp . (1) In order to guarantee a correct regulation, the resistor divider must be calculated for an output voltage of min. 2.5 V.

6.3 Output voltage sense pin

In the DFN6 package on pin 5, an additional VSENSE connection is available. This pin must not be left floating, since it is necessary for a correct sensing of the output voltage. It can be either connected to the load in a remote- sensing configuration, or directly shorted to the VOUT pin (pin 4, refer to Figure 4. Typical application diagram (fixed versions) and Figure 5. Typical application diagram (adjustable versions)).

6.4 Protection features

The device is self-protected from short-circuits and overtemperature events. In case of strong overload or short-circuit on the output, the output current is limited to a value of typically 1.5 A and kept constant even when the load impedance is zero. If the overload persists, the temperature on the internal die rises, until the thermal protection is triggered, which happens when the junction temperature reaches 175 °C. The device is subsequently shut down. As soon as the junction temperature falls again below 150 °C the device re-starts. Even if the above described protections are able to keep the device safe in the worst cases, a correct thermal design of the application is recommended, according to the operating ambient temperature and the maximum power dissipation allowed by the chosen package. In order to calculate the maximum power that the device can dissipate, keeping the junction temperature below TJ-OP = 125 °C, the following formula is used: P D M A X = 125 − T A M B / R T H J − A (2) The power dissipation on the device is calculated as PD = (VIN - VOUT) x IOUT. LDO40L

Application information

6.5 Enable pin

The enable function allows the LDO output to be enabled/disabled. The regulator is turned on in case the pin EN is connected to a voltage higher than VEN-H, the LDO can be turned off if the voltage on EN pin is lower than VEN-L. No internal pull-up / pull-down is present on the EN pin, therefore it must not be left floating in the application.

6.6 Input and output capacitors

The LDO40LY requires external capacitors to ensure the regulator control loop stability. A capacitor with a minimum value of 1 μF is required on at the input port of the LDO40LY. This capacitor must be located as close as possible to the input pin of the device and returned to a clean analog ground. Good quality ceramic capacitors are suggested. The device control loop is designed to be stable with good quality ceramic capacitors (such as: X5R/X7R types) with a minimum capacitance of 1 μF and equivalent series resistance in the [5 mΩ – 12 Ω] range. There is no upper limit to the output capacitance. Figure 27. Stability plan shows the stability plan tested on real capacitors, up to 10 µF. A value of 4.7 μF is suitable for the majority of applications, improving dynamic response and minimizing the risk of ringing and oscillations. It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the full operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR variations must be taken into account in the design phase to ensure the device works in the expected stability region. There is no maximum limit to the output capacitance, provided that the above conditions are respected. LDO40L Enable pin DS12711 - Rev 3 page 9/25

7 Typical characteristics

Figure 6. Output voltage vs. temperature (VIN = 6 V, Figure 7. Output voltage vs. temperature (VIN = 13.2 V, Figure 8. Output voltage vs. temperature (VIN = 18 V, Figure 9. Output voltage vs. temperature (VIN = 4.3 V,

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

8.1 DFN6 (3x3) package information

Figure 40. DFN6 (3x3) package outline Table 5. DFN6 (3x3) mechanical data

Package information

DS12711 - Rev 3 page 16/25

Figure 41. DFN6 (3x3) recommended footprint (dimensions are in mm)

8.2 DFN6 (3x3) packing information

Figure 42. DFN6 (3x3) tape outline

Figure 43. DFN6 (3x3) reel outline Table 6. DFN6 (3x3) tape and reel mechanical data

9 Ordering information

Table 7. Order code

Ordering information

DS12711 - Rev 3 page 20/25

Revision history

Table 8. Document revision history 12-Sep-2018 1 Initial release. Updated: Figure 3. Pin configuration (marking view) and Table 1. Pin description. Added: footnote in Table 7. Order code. 10-Feb-2020 3 Updated Table 7. Order code.