LDC2114YFDT

Texas Instruments

Inductive Touch Solution for Low-Power HMI and Button Applications

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ADVANCE□INFORMATION Inductive Sensing Core IN0 Logic GND SCL SDA I2C LPWRB IN3 COM LDC2114 Digital Algorithm INTB VDD Resonant Circuit Driver OUT0 IN1 IN2 OUT1 OUT2 OUT3 Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LDC2112,LDC2114 SNOSD15 – DECEMBER 2016 LDC2112,LDC2114InductiveTouchSolutionforLow-PowerHMIandButtonApplications

1 Features

1• Low Power Consumption: – One Button: 6 µA at 0.625 SPS – Two Buttons: 85 µA at 20 SPS

Configurable Button Scan Rates – 0.625 SPS to 80 SPS
Force Level Measurement of Touch Buttons
Independent Channel Operation – Two Channels for LDC2112 – Four Channels for LDC2114
Integrated Algorithms to Enable: – Adjustable Force Threshold per Button – Environmental Shift Compensation – Simultaneous Button Press Detection
Supports Independent Operation without MCU
Robust EMI Performance – CISPR 22 Class B and CISPR 24 Compliant
Supply Voltage: 1.8 V ± 5%
Temperature Range: –40 °C to +85 °C
Interface: – I2C – Dedicated Logic Output per Button

2 Applications

Touch buttons and force level measurements on different materials, including metal, plastic, and glass for:

Consumer electronics: – Smartphones – Smart watches and other wearable devices – Smart speakers – Tablets/PCs – Virtual reality headsets – Sound bars
Industrial applications: – Televisions – Handheld devices – Home appliances – HMI panels and keypads

3 Description

Inductive sensing technology enables touch button design on a wide variety of materials such as metal, glass, plastic, and wood, by measuring small deflections of conductive targets. The sensor for an inductive touch system is a coil that can be implemented on a small, compact PCB located behind the panel and protected from the environment. The LDC2112/LDC2114 can reliably detect material deflections of less than 200 nm. The LDC2112/LDC2114 is a multi-channel low-noise inductance to digital converter with integrated algorithms to implement inductive touch applications. The device employs an innovative LC resonator that offers high rejection of noise and interference. The LDC2112/LDC2114 includes an ultra-low power mode intended for power on/off buttons in battery powered applications. The LDC2112/LDC2114 is available in a 16-pin WCSP or TSSOP package. The 0.4 mm pitch WCSP package has a very small 1.6 × 1.6 mm nominal body size. The 1.2 mm pitch TSSOP package has a 5.0 × 4.4 mm nominal body size. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LDC2112/LDC2114 WCSP (16) 1.6 mm × 1.6 mm LDC2112/LDC2114 TSSOP (16) 5.0 mm × 4.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

12 Mechanical, Packaging, and Orderable

4 Revision History

December 2016 * Initial release.

ADVANCE□INFORMATION A B C D 1 2 3 4 LPW RB SDA OUT1 OUT0SCLCOMGND GND NCADDRINTBNC VDD NC IN1 IN0 LPWRB SDA OUT1 OUT0 SCLCOM GND GND NC ADDR INTB NC VDD NC IN1 IN0 8 9 161 LDC2112 LDC2112,LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Product Folder Links: LDC2112 LDC2114 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

Top View (Bumps Down) LDC2112 16-Pin TSSOP Top View (1) I = Input, O = Output, P=Power, G=Ground, A=Analog (2) Both pins should be connected to the system ground on the PCB. Pin Functions - LDC2112 PIN I/O(1) DESCRIPTION NAME NO. VDD C1 P Power supply GND G Ground(2) INTB B2 O Interrupt output Polarity can be configured in Register 0x11. Default is active low. LPWRB C2 I Normal / Low Power Mode select Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode. COM D2 A Common return current path for all LC resonator sensors A capacitor should be connected from this pin to GND. Refer to Setting COM Pin Capacitor. IN0 A3 A Channel 0 LC sensor input IN1 A2 A Channel 1 LC sensor input OUT0 D4 O Channel 0 logic output Polarity can be configured in Register 0x1C. OUT1 C4 O Channel 1 logic output Polarity can be configured in Register 0x1C. ADDR B3 I I2C address When ADDR = Low, I2C address = 0x2A. When ADDR = High, I2C address = 0x2B. SCL D3 I I2C clock SDA C3 I/O I2C data NC — No connect Leave them floating.B1

ADVANCE□INFORMATION A B C D 1 2 3 4 LPW RB SDA OUT1 OUT0SCLCOMGND GND OUT2OUT3INTBIN3 VDD IN2 IN1 IN0 LPWRB SDA OUT1 OUT0 SCLCOM GND GND OUT2 OUT3 INTB IN3 VDD IN2 IN1 IN0 8 9 161 LDC2114 LDC2112,LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated LDC2114 16-Pin WCSP Top View (Bumps Down) LDC2114 16-Pin TSSOP Top View (1) I = Input, O = Output, P=Power, G=Ground, A=Analog (2) Both pins should be connected to the system ground on the PCB. Pin Functions - LDC2114 PIN I/O(1) DESCRIPTION NAME NO. VDD C1 P Power supply GND G Ground(2) INTB B2 O Interrupt output Polarity can be configured in Register 0x11. Default is active low. LPWRB C2 I Normal / Low Power Mode select Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode. COM D2 A Common return current path for all LC resonator sensors A capacitor should be connected from this pin to GND. Refer to Setting COM Pin Capacitor. IN0 A3 A Channel 0 LC sensor input IN1 A2 A Channel 1 LC sensor input IN2 A1 A Channel 2 LC sensor input IN3 B1 A Channel 3 LC sensor input OUT0 D4 O Channel 0 logic output Polarity can be configured in Register 0x1C. OUT1 C4 O Channel 1 logic output Polarity can be configured in Register 0x1C. OUT2 B4 O Channel 2 logic output Polarity can be configured in Register 0x1C. OUT3 B3 O Channel 3 logic output Polarity can be configured in Register 0x1C. SCL D3 I I2C clock SDA C3 I/O I2C data I2C address = 0x2A.

ADVANCE□INFORMATION LDC2112,LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Product Folder Links: LDC2112 LDC2114 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Maximum voltage across any two pins is VDD + 0.3 V

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range unless otherwise noted.(1) MIN MAX UNIT VDD Supply voltage 2 V Vi Voltage on any pin –0.3 2(2) V TJ Junction temperature –40 85 ℃ Tstg Storage temperature –65 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 VCharged device model (CDM), per JEDEC specification JESD22- C101(2) ±250

6.3 Recommended Operating Conditions

Over operating free-air temperature range unless otherwise noted. MIN NOM MAX UNIT VDD Supply voltage 1.71 1.89 V TJ Junction temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) LDC2112/LDC2114 UNITYFD (WCSP) (TSSOP)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 81.8 105.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.4 40.3 °C/W RθJB Junction-to-board thermal resistance 18.2 50.2 °C/W ΨJT Junction-to-top characterization parameter 0.3 3.6 °C/W ΨJB Junction-to-board characterization parameter 18 49.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W

ADVANCE□INFORMATION LDC2112,LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) I2C read/write communication and pull-up resistors current through SCL, SDA not included. (2) For typical percentage offset distribution of the scan rates, refer to Figure 8.

6.5 Electrical Characteristics

Over operating free-air temperature range unless otherwise noted. VDD = 1.8 V, TJ = 25 °C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER VDD Supply voltage 1.71 1.8 1.89 V IDDNP Normal power mode supply current(1) 4 buttons, 40 SPS per button, 1 ms sampling window, LPRWB = 1, QSENSOR = 11, LSENSOR = 0.85 µH, CSENSOR = 58 pF, RP = 0.7 kΩ 0.47 mA IDDLP Low power mode supply current(1) 1 button, 1.25 SPS, 1 button, 1.25 SPS, 1 ms sampling window, LPRWB = 0, QSENSOR = 11, LSENSOR = 0.85 µH, CSENSOR = 58 pF, RP = 0.7 kΩ 9 µA IDDSB Standby supply current No button active (EN = 0x00) 5 10 µA SENSOR ISENSORMAX Sensor maximum current drive Registers SENSORn_CONFIG: RPn = 0 (n = 0, 1, 2, or 3) 2.5 mA RP, min Minimum sensor RP 350 Ω RP, max Maximum sensor RP 10 kΩ fSENSOR Sensor resonant frequency 1 30 MHz QSENSOR, MIN Minimum sensor quality factor 5 QSENSOR, MAX Maximum sensor quality factor 30 VSENSOR Sensor oscillation amplitude (peak-to- peak) Measured on the INn (n = 0, 1, 2, or 3) pins with reference to COM. 0.9 V CIN Sensor pin input capacitance 17 pF CONVERTER SRNP, min Minimum normal power mode scan rate(2) LPWRB = 1 7 10 13 SPS SRNP, max Maximum normal power mode scan rate(2) LPWRB = 1 56 80 104 SPS SRLP, min Minimum low power mode scan rate(2) LPWRB = 0 0.438 0.625 0.813 SPS SRLP, max Maximum low power mode scan rate(2) LPWRB = 0 3.5 5 6.5 SPS Resolution Output code width 12 Bits

6.6 Digital Interface

(1) This parameter is specified by design and/or characterization and is not tested in production.

6.7 I2C Interface

Figure 1. I2C Timing Diagram

10 SPS

20 SPS

40 SPS

80 SPS

0.625 SPS

1.25 SPS

2.5 SPS

5 SPS

6.8 Typical Characteristics

Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25 °C. Figure 2. Supply Current vs Sensor RP for Normal Power Figure 3. Supply Current vs Sensor RP for Low Power Mode. Figure 4. Supply Current vs Temperature, Sensor RP = 650 Figure 5. Supply Current vs VDD, Sensor RP = 650 Ω Figure 6. Standby Current vs Temperature Figure 7. Standby Current vs VDD

Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25 °C. Figure 8. Scan Rate Percentage Offset Distribution at 30 °C

7 Detailed Description

7.1 Overview

LDC2112/LDC2114 incorporates customizable post-processing algorithms for enhanced robustness. LDC2112/LDC2114 is operational from –40 °C to +85 °C with a 1.8 V ± 5% power supply voltage. operation are supply bypassing capacitors and a COM pin capacitor to ground.

7.2 Functional Block Diagram

Figure 9. Block Diagram of LDC2112

Figure 10. Block Diagram of LDC2114

7.3 Feature Description

7.3.1 Multi-Button and Single-Button Operation

channel index n. In those instances, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114. rate. Each button can be enabled independently to be active in Low Power Mode and Normal Power Mode.

7.3.2 Button Output Interfaces

reported by the interrupt pin, INTB. Its polarity is configurable through Register INTPOL (Address 0x11). value is correlated to the amount of force applied to the button.

7.3.3 Programmable Button Sensitivity

gain factor over a range of 232 times. Each gain step increases the gain by a factor of between 1.06 and 1.12. The gain required for an application is primarily determined by the mechanical rigidity of each individual button. The individual gain steps are listed in the Gain Table.

7.3.4 Baseline Tracking

7.3.5 Integrated Button Algorithms

information, refer to Mitigating False Button Detections.

7.3.6 I2C Interface

LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses.

Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 1 to start the register write session
Poll for RDY_TO_WRITE (Register STATUS, Address 0x00) bit = 1
I2C write to configure registers
Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 0 to terminate the register write session After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. The waveform of the above process is shown in Figure 11.

Figure 11. Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for

7.3.6.1 Selectable I2C Address (LDC2112 Only)

7.3.6.2 I2C Interface Specifications

increment as long as the master acknowledges.

7.3.6.3 I2C Bus Control

release it sometime within those nine clocks. If not, then power cycle to clear the bus. of a device fault, the device state will be reset internally, and all the registers will be reset with default settings. register settings if needed.

7.4 Device Functional Modes

10, 20, 40, or 80 SPS, and a Low Power Mode for reduced current consumption at 0.625, 1.25, 2.5, or 5 SPS.

7.4.1 Normal Power Mode

Mode Scan Rate, refer to Electrical Characteristics.

7.4.2 Low Power Mode

Low Power Mode Scan Rate, refer to Electrical Characteristics.

7.4.3 Configuration Mode

I2C Interface for more information.

7.5 Register Maps

Table 1. Register List 0x00 STATUS 0x00 Device status. 0x01 OUT 0x00 Channel output logic states.

Table 1. Register List (continued) 0x0A RESET 0x00 Reset device and register configurations. 0x0B RESERVED 0x00 Reserved. Set to 0x00. 0x0C EN 0x1F Enable channels and low power modes. 0x0D NP_SCAN_RATE 0x01 Normal Power Mode scan rate. 0x0E GAIN0 0x28 Gain for Channel 0 sensitivity adjustment. 0x0F LP_SCAN_RATE 0x02 Low Power Mode scan rate. 0x10 GAIN1 0x28 Gain for Channel 1 sensitivity adjustment. 0x11 INTPOL 0x01 Interrupt polarity. 0x12 GAIN2 0x28 Gain for Channel 2 sensitivity adjustment. 0x13 LP_BASE_INC 0x06 Low power base increment. 0x14 GAIN3 0x28 Gain for Channel 3 sensitivity adjustment. 0x15 NP_BASE_INC 0x04 Normal power base increment. 0x17 LC_DIVIDER 0x03 LC oscillation frequency divider. 0x18 HYST 0x08 Hysteresis for threshold. 0x1A COMMON_DEFORM 0x00 Anti-common and anti-deformation. 0x1B RESERVED 0x00 Reserved. Set to 0x00. 0x1C OPOL_DPOL 0x0F Output polarity. 0x1D RESERVED 0x00 Reserved. Set to 0x00. 0x1E CNTSC 0x55 Counter scale. 0x1F RESERVED 0x00 Reserved. Set to 0x00. 0x21 RESERVED 0x00 Reserved. Set to 0x00. 0x23 RESERVED 0x00 Reserved. Set to 0x00. 0x25 FTF0 0x00 Sensor 0 fast tracking factor. 0x27 RESERVED 0x00 Reserved. Set to 0x00. 0x28 FTF1_2 0x00 Sensors 1 and 2 fast tracking factors. 0x29 RESERVED 0x00 Reserved. Set to 0x00. 0x2A RESERVED 0x00 Reserved. Set to 0x00. 0x2B FTF3 0x00 Sensor 3 fast tracking factor.

7.5.1 Individual Register Listings

read and write capability, a ‘R’indicates read-only, and a ‘W’indicates write-only. supports burst mode with auto-incrementing register addresses. Table 2. Register STATUS – Address 0x00

7 OUT_STATUS R 0 Output Status

field is cleared by reading this register.

6 CHIP_READY R 1 Chip Ready Status

b0: chip not ready after internal reset. b1: chip ready after internal reset.

5 RDY_TO_WRITE R 0 Ready to Write

4 MAXOUT R 0 Max-Out Error

3 FSM_WD R 0 Finite-State Machine Watchdog Error

halted. Cleared by a read of the status register. b0: no error in finite state machine. b1: error in finite state machine.

2 LC_WD R 0 LC Sensor Watchdog Error

a read of the status register. b0: no error in LC oscillator initialization. b1: error in LC oscillator initialization.

1 TIMEOUT R 0 Button Timeout

Reports when any button is asserted for more than 50 seconds. Cleared by a read of the status register. 0 RESERVED R 0 Reserved. Set to b0. Table 3. Register OUT – Address 0x01 7:4 RESERVED R 0000 Reserved. Set to b0000.

3 OUT3 R 0 Output Logic State for Channel 3 (LDC2114 Only)

b0: No button press detected on Channel 3. b1: Button press detected on Channel 3.

2 OUT2 R 0 Output Logic State for Channel 2 (LDC2114 Only)

b0: No button press detected on Channel 2. b1: Button press detected on Channel 2.

Table 3. Register OUT – Address 0x01 (continued)

1 OUT1 R 0 Output Logic State for Channel 1

b0: No button press detected on Channel 1. b1: Button press detected on Channel 1.

0 OUT0 R 0 Output Logic State for Channel 0

b0: No button press detected on Channel 0. b1: Button press detected on Channel 0. Table 4. Register DATA0_LSB – Address 0x02 7:0 DATA0[7:0] R 0000 0000 The lower 8 bits of Channel 0 data (Two’s complement). Table 5. Register DATA0_MSB – Address 0x03 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA0[11:8] R 0000 The upper 4 bits of Channel 0 data (Two’s complement). Table 6. Register DATA1_LSB – Address 0x04 7:0 DATA1[7:0] R 0000 0000 The lower 8 bits of Channel 1 data (Two’s complement). Table 7. Register DATA1_MSB – Address 0x05 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA1[11:8] R 0000 The upper 4 bits of Channel 1 data (Two’s complement). Table 8. Register DATA2_LSB – Address 0x06 7:0 DATA2[7:0] R 0000 0000 The lower 8 bits of Channel 2 data (Two’s complement). Table 9. Register DATA2_MSB – Address 0x07 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA2[11:8] R 0000 The upper 4 bits of Channel 2 data (Two’s complement). Table 10. Register DATA3_LSB – Address 0x08 7:0 DATA3[7:0] R 0000 0000 The lower 8 bits of Channel 3 data (Two’s complement). Table 11. Register DATA3_MSB – Address 0x09 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA3[11:8] R 0000 The upper 4 bits of Channel 3 data (Two’s complement). Table 12. Register RESET – Address 0x0A 7:5 RESERVED R 000 Reserved. Set to b000.

4 FULL_RESET R/W 0 Device Reset

resume until STATUS:CHIP_READY = 1. 3:1 RESERVED R 000 Reserved. Set to b000.

Table 12. Register RESET – Address 0x0A (continued)

0 CONFIG_MODE R/W 0 Configuration Mode

configuration changes should be made with this bit set to 1. Table 13. Register EN – Address 0x0C

7 LPEN3 R/W 0 Channel 3 Low-Power-Enable (LDC2114 Only)

b0: Disable Channel 3 in Low Power Mode.

6 LPEN2 R/W 0 Channel 2 Low-Power-Enable (LDC2114 Only)

b0: Disable Channel 2 in Low Power Mode.

5 LPEN1 R/W 0 Channel 1 Low-Power-Enable

b0: Disable Channel 1 in Low Power Mode.

4 LPEN0 R/W 1 Channel 0 Low-Power-Enable

b0: Disable Channel 0 in Low Power Mode.

3 EN3 R/W 1 Channel 3 Enable

2 EN2 R/W 1 Channel 2 Enable

1 EN1 R/W 1 Channel 1 Enable

0 EN0 R/W 1 Channel 0 Enable

Table 14. Register NP_SCAN_RATE – Address 0x0D 7:2 RESERVED R b00 0000 Reserved. Set to b00 0000. Refer to Configuring Button Scan Rate for more information. Table 15. Register GAIN0 – Address 0x0E 7:6 RESERVED R 00 Reserved. Set to b00. Refer to the Gain Table for detailed configuration.

Table 16. Register LP_SCAN_RATE – Address 0x0F 7:2 RESERVED R b00 0000 Reserved. Set to b00 0000. Refer to Configuring Button Scan Rate for more information. Table 17. Register GAIN1 – Address 0x10 7:6 RESERVED R 00 Reserved. Set to b00. Refer to the Gain Table for detailed configuration. Table 18. Register INTPOL – Address 0x11 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000.

2 INTPOL R/W 0 Interrupt Polarity

b0: Set INTB pin polarity to active low. b1: Set INTB pin polarity to active high. 1:0 RESERVED R 01 Reserved. Set to b01. Table 19. Register GAIN2 – Address 0x12 7:6 RESERVED R 00 Reserved. Set to b00. Refer to the Gain Table for detailed configuration. Table 20. Register LP_BASE_INC – Address 0x13 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. Table 21. Register GAIN3 – Address 0x14 7:6 RESERVED R 00 Reserved. Set to b00. Refer to the Gain Table for detailed configuration. Table 22. Register NP_BASE_INC – Address 0x15 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. Table 23. Register MAXWIN – Address 0x16 7:4 RESERVED R b0000 Reserved. Set to b0000.

3 MAXWIN3 R/W 0 Max-Win Algorithm Setting for Channel 3 (LDC2114 Only)

b0: Channel 3 is excluded from the max-win group. b1: Channel 3 is included in the max-win group.

Table 23. Register MAXWIN – Address 0x16 (continued)

2 MAXWIN2 R/W 0 Max-Win Algorithm Setting for Channel 2 (LDC2114 Only)

b0: Channel 2 is excluded from the max-win group. b1: Channel 2 is included in the max-win group.

1 MAXWIN1 R/W 0 Max-Win Algorithm Setting for Channel 1

b0: Channel 1 is excluded from the max-win group. b1: Channel 1 is included in the max-win group.

0 MAXWIN0 R/W 0 Max-Win Algorithm Setting for Channel 0

b0: Channel 0 is excluded from the max-win group. b1: Channel 0 is included in the max-win group. Table 24. Register LC_DIVIDER – Address 0x17 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. conjunction with SENCYCn. Valid values: [b000:b111]. Table 25. Register HYST – Address 0x18 7:4 RESERVED R b0000 Reserved. Set to b0000. Table 26. Register TWIST – Address 0x19 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. When set to 0, the anti-twist algorithm is not enabled. DATA is negative by a threshold. Anti-twist Threshold = ANTITWIST × 4. Table 27. Register COMMON_DEFORM – Address 0x1A

7 ANTICOM3 R/W 0 Anti-Common Algorithm Setting for Channel 3 (LDC2114

b0: Exclude Channel 3 from the anti-common group. b1: Include Channel 3 in the anti-common group.

6 ANTICOM2 R/W 0 Anti-Common Algorithm Setting for Channel 2 (LDC2114

b0: Exclude Channel 2 from the anti-common group. b1: Include Channel 2 in the anti-common group.

Table 27. Register COMMON_DEFORM – Address 0x1A (continued)

5 ANTICOM1 R/W 0 Anti-Common Algorithm Setting for Channel 1

b0: Exclude Channel 1 from the anti-common group. b1: Include Channel 1 in the anti-common group.

4 ANTICOM0 R/W 0 Anti-Common Algorithm Setting for Channel 0

b0: Exclude Channel 0 from the anti-common group. b1: Include Channel 0 in the anti-common group.

3 ANTIDFORM3 R/W 0 Anti-Deform Algorithm Setting for Channel 3 (LDC2114

b0: Exclude Channel 3 from the anti-deform group. b1: Include Channel 3 in the anti-deform group.

2 ANTIDFORM2 R/W 0 Anti-Deform Algorithm Setting for Channel 2 (LDC2114

b0: Exclude Channel 2 from the anti-deform group. b1: Include Channel 2 in the anti-deform group.

1 ANTIDFORM1 R/W 0 Anti-Deform Algorithm Setting for Channel 1

b0: Exclude Channel 1 from the anti-deform group. b1: Include Channel 1 in the anti-deform group.

0 ANTIDFORM0 R/W 0 Anti-Deform Algorithm Setting for Channel 0

b0: Exclude Channel 0 from the anti-deform group. b1: Include Channel 0 in the anti-deform group. Table 28. Register OPOL_DPOL – Address 0x1C

7 OPOL3 R/W 0 Output Polarity for OUT3 Pin (LDC2114 Only)

6 OPOL2 R/W 0 Output Polarity for OUT2 Pin (LDC2114 Only)

5 OPOL1 R/W 0 Output Polarity for OUT1 Pin

4 OPOL0 R/W 0 Output Polarity for OUT0 Pin

3 DPOL3 R/W 1 Data Polarity for Channel 3 (LDC2114 Only)

b0: DATA3 decreases as fSENSOR3 increases.

2 DPOL2 R/W 1 Data Polarity for Channel 2 (LDC2114 Only)

b0: DATA2 decreases as fSENSOR2 increases.

1 DPOL1 R/W 1 Data Polarity for Channel 1

b0: DATA1 decreases as fSENSOR1 increases.

0 DPOL0 R/W 1 Data Polarity for Channel 0

b0: DATA0 decreases as fSENSOR0 increases.

Table 29. Register CNTSC – Address 0x1E(1) Table 30. Register SENSOR0_CONFIG – Address 0x20

7 RP0 R/W 0 Channel 0 Sensor RP Range Select

7 RP1 R/W 0 Channel 1 Sensor RP Range Select

Set based on the actual sensor RP physical parameter. the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information.

Table 31. Register SENSOR1_CONFIG – Address 0x22 (continued) Refer to Designing Sensor Parameters for more information. Table 32. Register SENSOR2_CONFIG – Address 0x24

7 RP2 R/W 0 Channel 2 Sensor RP Range Select (LDC2114 Only)

Set based on the actual sensor RP physical parameter. the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. Refer to Designing Sensor Parameters for more information. Table 33. Register FTF0 – Address 0x25 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. Defines baseline tracking speed for negative values of DATA0. Refer to Tracking Baseline for more information. 0 RESERVED R 0 Reserved. Set to b0. Table 34. Register SENSOR3_CONFIG – Address 0x26

7 RP3 R/W 0 Channel 3 Sensor RP Range Select (LDC2114 Only)

Table 34. Register SENSOR3_CONFIG – Address 0x26 (continued) Table 35. Register FTF1_2 – Address 0x28 Defines baseline tracking speed for negative values of DATA2. Refer to Tracking Baseline for more information. Defines baseline tracking speed for negative values of DATA1. Refer to Tracking Baseline for more information. 3:0 RESERVED R b0000 Reserved. Set to b0000. Table 36. Register FTF3 – Address 0x2B 7:2 RESERVED R b00 0000 Reserved. Set to b00 0000. Defines baseline tracking speed for negative values of DATA3. Refer to Tracking Baseline for more information. Table 37. Register MANUFACTURER_ID_LSB – Address 0xFC Table 38. Register MANUFACTURER_ID_MSB – Address 0xFD Table 39. Register DEVICE_ID_LSB – Address 0xFE Table 40. Register DEVICE_ID_MSB – Address 0xFF

7.5.1.1 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3

Table 41. GAINn Bit Values in Decimal and Corresponding Normalized Gain Factors

Table 41. GAINn Bit Values in Decimal and Corresponding Normalized Gain Factors (continued)

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Understanding Theory of Operation

composition of the conductor. Figure 16. Metal Deflection The eddy current generates its own magnetic field, which opposes the original field generated by the inductor. This effect reduces the effective inductance of the system, resulting in an increase in sensor frequency. distance should typically be less than 10% of the shorter side of the coil.

1 L Q R C

Figure 17. Sensor Inductance and Frequency vs Target Distance values of the changes in sensor frequencies.

8.1.2 Designing Sensor Parameters

parameters must be within the ranges as specified in the Sensor section of the Electrical Characteristics table. Figure 18. LC Resonator The LC sensor frequency, as defined by the equation below, must be between 1 MHz and 30 MHz. The sensor quality factor, as defined by the equation below, must be between 5 and 30.

Figure 19. Equivalent Parallel Circuit the oscillation amplitude. RP must be between 350 Ω and 10 kΩ.

1 MHz ≤ fSENSOR ≤ 30 MHz
5 ≤ Q ≤ 30
350 Ω ≤ RP ≤ 10 kΩ

8.1.3 Setting COM Pin Capacitor

can be obtained with the Spiral_Inductor_Designer tab of the LDC Tools Spreadsheet.

8.1.4 Defining Power-On Timing

The low power architecture of the LDC2112/LDC2114 makes it possible for the device to be active all the time. power-on timing of the LDC2112/LDC2114 is illustrated in Figure 20 below. Figure 20. Power-On Timing

8.1.5 Configuring Button Scan Rate

can be independently enabled through a bit in Register EN (Address 0x0C). Table 42. Button Scan Rates

10 Not Applicable b11 High (1)

20 Not Applicable b10 High (1)

40 Not Applicable b01 High (1)

80 Not Applicable b00 High (1)

8.1.6 Programming Button Sampling Window

channels will sample sequentially, as illustrated in Figure 21. Figure 21. Configurable Scan Rate and Button Sampling Window 1 MHz to 30 MHz. The exact definition of the button sampling window is given by the equation below.

0.0861 SENCYC 1CNTSC LCDIV ceiling log , 0,1 , 2, or 3

where is the sensor frequency in MHz.

128 SENCYC 1 2

is the sensor frequency in MHz. this can be achieved by setting SENCYCn = 17 and LCDIV = 2. Alternatively, from the button sampling window and sensor frequency, the LCDIV can be read off from Figure 22. = 2. Then SENCYCn can be calculated accordingly. Figure 22. LCDIV as a Function of Sensor Frequency and Button Sampling Window

8.1.7 Scaling Frequency Counter Output

8.1.8 Setting Button Triggering Threshold

press. When the DATAn decreases to 128 – 32 = 96, the LDC considers the button to be released. Figure 23. Button Triggering Threshold with Hysteresis

8.1.9 Tracking Baseline

Figure 24. Baseline Tracking in the Presence of a Button Press Table 43. Fast Tracking Factor Settings

8.1.10 Mitigating False Button Detections

non-idealities. These are listed below.

8.1.10.1 Eliminating Common-Mode Change (Anti-Common)

feature by programming Register COMMON_DEFORM (Address 0x1A).

Figure 25. Illustration of the Anti-Common Feature

8.1.10.2 Resolving Simultaneous Button Presses (Max-Win)

group by configuring Register MAXWIN (Address 0x16). Figure 26. Illustration of the Max-Win Feature

8.1.10.3 Overcoming Case Twisting (Anti-Twist)

configurable threshold. The anti-twist algorithm can be enabled by configuring Register TWIST (Address 0x19).

OUT n DQG,17%DUHSURJUDPPHGWR³$FWLYH/RZ´. Scan Rate: 40 SPS. Twisting effect of Buttons 0 and 1. Intentional Press of Button 1. Figure 27. Illustration of the Anti-Twist Feature

8.1.10.4 Mitigating Metal Deformation (Anti-Deform)

COMMON_DEFORM (Address 0x1A).

8.1.11 Reporting Interrupts for Button Presses and Error Conditions

default polarity is active low and can be configured through Register INTPOL (Address 0x11). Figure 28. Timing Diagram of a Single Button Press

OUT n DQG,17%DUHSURJUDPPHGWR³$FWLYH/RZ´. Scan Rate: 40 SPS. Figure 31. Timing Diagram of an Error Condition in the Presence of a Button Press

8.1.12 Estimating Supply Current

while channels switching on and off. The static current is about 1.45 mA. The dynamic current is a function of the supply voltage and sensor frequency. fSENSOR is the sensor frequency in MHz. The sensor current is inversely proportional to the sensor RP. A is an empirical parameter dependent on the sensor RP in kΩ and supply voltage VDD in V. tSCAN is the button scan window in ms.

8.2 Typical Application

8.2.1 Touch Button Design

The low power architecture of LDC2112/LDC2114 makes them ideal for driving button sensors in consumer electronics, such as mobile phones. Most mobile phones today have three buttons along the edges, namely the power button, volume up, and volume down. The LDC2112 can support two buttons, and LDC2114 can support four. On a typical smartphone, the two volume buttons are next to each other, so they may be susceptible to false detections such as simultaneous button presses. To prevent such mis-triggers, they can be grouped together to take advantage of the various features that mitigate false detections as explained in Mitigating False Button Detections. For example, if MAXWIN is applied to the two volume buttons, only the one with the greater force will be triggered. The phone case does not require any mechanical cutouts at the button locations. This can support reduced manufacturing cost for the case and enhance the case’s resistance to moisture intrusion, dust and dirt. This is a great advantage compared to mechanical buttons in the market today.

8.2.1.1 Design Requirements

The sensor parameters, including frequency, RP, and Q factor have to be within the design space of the LDC2112/LDC2114 as specified in Electrical Characteristics.

8.2.1.2 Detailed Design Procedure

The LDC2112/LDC2114 is a multi-channel device. The italic n in the parameters below refers to the nth channel, that is, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114. 1. Select system-based options:

Select Normal or Low Power Mode of operation by connecting the LPWRB pin to VDD or GND, respectively. Configure the enable bits for all channels in Register EN (Address 0x0C).
Select polarities of OUTn and INTB pins by configuring Register OPOL_DPOL (Address 0x1C) and Register INTPOL (Address 0x11).
Configure sensor frequency setting in Registers SENSORn_CONFIG (Addresses 0x20, 0x22, 0x24, 0x26). 2. Choose sampling rate (80, 40, 20, 10, 5, 2.5, 1.25, or 0.625 SPS) based on system power consumption requirement, and configure Register NP_SCAN_RATE (Address 0x0D) or Register LP_SCAN_RATE (Address 0x0F). 3. Choose button sampling window based on power consumption and noise requirements (recommended: 1 ms to 8 ms). While a longer button sampling window provides better noise performance, 1 ms is typically sufficient for most applications. Set SENCYCn and LCDIV in Registers SENSORn_CONFIG (Addresses 0x20, 0x22, 0x24, 0x26) and Register LC_DIVIDER (Address 0x17) in the following steps:
Calculate LCDIV = ceiling (log2 (fSENSORn × tSAMPLE) – 12), where fSENSORn is sensor frequency in MHz, tSAMPLE is button sampling window in µs
If LCDIV < 0, set it to 0
Adjust SENCYCn to get desired tSAMPLE according to tSAMPLE = 128 × (SENCYCn + 1) × 2LCDIV / fSENSORn 4. Calibrate gain in the appropriate Registers GAINn (Addresses 0x0E, 0x10, 0x12, 0x14). The gain setting can be used to tune the sensitivity of the touch button. GAINn is a 6-bit field with 64 different gain levels corresponding to a relative gain of 1 to 232. A good mechanical and sensor design typically requires a gain level of around 32 to 50, corresponding to relative gains of 16 to 76 (normalized to gain level of 0). Use the following sequence to determine the appropriate gain for each button:
Apply minimum desired force to the button.
Read initial DATAn value after the button press. Note that the baseline tracking will affect this value.
Calculate gain factor needed to increase DATAn to the programmed threshold (default is 160).
Look up the Gain Table to find the required gain setting. 5. Enable special features to mitigate button interference if there is any. Registers MAXWIN, TWIST, COMMON_DEFORM (Addresses 0x16, 0x19, 0x1A).

8.2.1.3 Application Curves

Figure 32. Conversion DATA vs Time for Channels 0 and 1

9 Power Supply Recommendations

The LDC2114 power supply should be bypassed with a 1-μF and a 0.1-μF pair of capacitors in parallel to ground. The smaller value 0.1-µF capacitor should be placed closer to the VDD pin than the 1-μF capacitor. The capacitors should be a low ESL, low ESR type. To enable close positioning of the capacitors, use of 0201 footprint devices for the bypass capacitors is recommended. Refer to Recommended Operating Conditions for more details.

10 Layout

10.1 Layout Guidelines

The COM pin must be bypassed to ground with an appropriate value capacitor. CCOM must be placed as close as possible to the COM pin. The COM signal must be tied to a small copper fill placed underneath the INn signals. To enable closer positioning of the capacitors, use of 0201 footprint devices for the bypass capacitors is recommended. Each active channel needs to have an LC resonator connected to the corresponding INn pins. The sensor capacitor must be placed within 10 mm of the corresponding INn pin, and the inductor (NOT shown in Figure 33) must be placed at the appropriate location next to (but not touching) the metal target. The INn traces must be at least 6 mil (0.15 mm) wide to minimize parasitic inductances. For the chip-scale package, the inner 4 device pads (INTB, OUT3, LPWRB, and SDA) must be routed out on an inner layer through vias, with the traces offset to reduce coupling with other signals. For many layouts, these 4 vias may need to use blind vias or microvias to bring the signals out. The PCB layer stackup must use a thinner (4 mil or 0.1 mm thickness) dielectric between the top copper and next copper layer so that microvias can be used.

10.2 Layout Example

Figure 33. Layout of LDC2114 (WCSP-16) With Decoupling Capacitors and Sensor Capacitors

10.3 WCSP Light Sensitivity

wavelengths in the red and infrared part of the spectrum have the most detrimental effect.

11 Device and Documentation Support

11.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 44. Related Links

11.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Export Control Notice

Commerce and other competent Government authorities to the extent required by those laws.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C

0.4 MAX

0.175 0.125 1.2 TYP 1.2 TYP 16X 0.285 0.185 0.4 TYP 0.4 TYP B E A D 4222547/A 12/2015 DSBGA - 0.4 mm max heightYFD0016 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SYMM SYMM 3 4 0.05 C BALL A1 CORNER SEATING PLANE BALL TYP D C B A 1 2

0.015 C A B

www.ti.com EXAMPLE BOARD LAYOUT (0.4) TYP ( ) METAL 0.225 0.05 MAX SOLDER MASK OPENING METAL UNDER SOLDER MASK ( ) SOLDER MASK OPENING 0.225

0.05 MIN

DSBGA - 0.4 mm max heightYFD0016 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM LAND PATTERN EXAMPLE SCALE:40X 1 2 A B C 3 4 D NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED ADVANCE□INFORMATION LDC2112,LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (0.4) TYP (0.4) TYP 16X ( 0.25) (R ) TYP0.05 METAL TYP 4222547/A 12/2015 DSBGA - 0.4 mm max heightYFD0016 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. D SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 1 2 A B C 3 4 ADVANCE□INFORMATION LDC2112,LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Product Folder Links: LDC2112 LDC2114 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated

www.ti.com 21-Dec-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LDC2112PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 85 LDC2112PWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI -40 to 85 LDC2112YFDR PREVIEW DSBGA YFD 16 3000 TBD Call TI Call TI -40 to 85 LDC2112YFDT PREVIEW DSBGA YFD 16 250 TBD Call TI Call TI -40 to 85 LDC2114PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 85 LDC2114PWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI -40 to 85 LDC2114YFDR PREVIEW DSBGA YFD 16 3000 TBD Call TI Call TI -40 to 85 LDC2114YFDT PREVIEW DSBGA YFD 16 250 TBD Call TI Call TI -40 to 85 PLDC2114YFDT ACTIVE DSBGA YFD 16 250 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

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Product Information

LDC2114YFDT specifications and overview.

Summary

Inductive Touch Solution for Low-Power HMI and Button Applications

Description

Inductive Touch Solution for Low-Power HMI and Button Applications

Source title LDC2114YFDT Datasheet(PDF) - Texas Instruments

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