LDC1312DNTT

Texas Instruments

Multi-Channel 12-Bit Inductance to Digital Converter (LDC) for Inductive Sensing

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Sensing Range (Target Distance / /c87SENSOR ) Measurement Precision (µm) 0 10% 20% 30% 40% 50% 60% 70% 0.25 0.5 0.75 1.25 1.5 1.75 2.25 2.5 D001 IN0A IN0B IN1A IN1B LDC1312 VDD Core GND SCL SDA I2C CLKIN ADDR INTB SD Sensor 0 GND MCU VDD I2C Peripheral 3.3 V 3.3 V GPIO GPIO 3.3 V

40 MHz

Sample & Buy T echnical Documents Tools & Software Support & Community LDC1312,LDC1314 SNOSCZ0 – DECEMBER 2014 LDC1312,LDC1314Multi-Channel12-BitInductancetoDigitalConverter(LDC)for InductiveSensing

1 Features 3 Description

The LDC1312 and LDC1314 are 2- and 4-channel, 1• Easy-to-use – minimal configuration required 12-bit inductance to digital converters (LDCs) for• Measure up to 4 sensors with one IC inductive sensing solutions. With multiple channels

Multiple channels support environmental and and support for remote sensing, the LDC1312 and aging compensation LDC1314 enable the performance and reliability benefits of inductive sensing to be realized at minimal• Multi-channel remote sensing provides lowest cost and power. The products are easy to use, onlysystem cost requiring that the sensor frequency be within 1 kHz• Pin-compatible medium and high-resolution and 10 MHz to begin sensing. The wide 1 kHz to 10options MHz sensor frequency range also enables use of very small PCB coils, further reducing sensing– LDC1312/4: 2/4-ch 12-bit LDC solution cost and size.– LDC1612/4: 2/4-ch 28-bit LDC The LDC1312 and LDC1314 offer well-matched• Supports wide sensor frequency range of 1kHz to channels, which allow for differential and ratiometric10MHz measurements. This enables designers to use one• Power consumption: channel to compensate their sensing for – 35 µA Low Power Sleep Mode environmental and aging conditions such as temperature, humidity, and mechanical drift. Given– 200 nA Shutdown Mode their ease of use, low power, and low system cost• 3.3V operation these products enable designers to greatly improve• Support internal or external reference clock on existing sensing solutions and to introduce brand
Immune to DC magnetic fields and magnets new sensing capabilities to products in all markets, especially consumer and industrial applications. Inductive sensing offers better performance,2 Applications reliability, and flexibility than competitive sensing• Knobs in consumer, appliances, and automotive technologies at lower system cost and power.
Linear and rotational encoders The LDC1312 and LDC1314 are easily configured via• Buttons in home electronics, wearables, an I2C interface. The two-channel LDC1312 is manufacturing, and automotive available in a WSON-12 package and the four- channel LDC1314 is available in a WQFN-16• Keypads in manufacturing and appliances package.• Slider buttons in consumer products
Metal detection in industrial and automotive Device Information(1)
POS and EPOS PART NUMBER PACKAGE BODY SIZE (NOM)
Flow meters in consumer and appliances LDC1312 WSON-12 4 mm × 4 mm LDC1314 WQFN-16 4 mm × 4 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic Measurement Precision vs. Target Distance An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LDC1312,LDC1314 SNOSCZ0 – DECEMBER 2014 www.ti.com Table of Contents

4 Revision History

December 2014 * Initial release.

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5 Pin Configuration and Functions

TYPE(1) DESCRIPTION NAME NO. SCL 1 I I2C Clock input SDA 2 I/O I2C Data input/output CLKIN 3 I Master Clock input. Tie this pin to GND if internal oscillator is selected ADDR I2C Address selection pin: when ADDR=L, I2C address = 0x2A, when ADDR=H, I2C address =4 I 0x2B. INTB 5 O Configurable Interrupt output pin SD 6 I Shutdown input VDD 7 P Power Supply GND 8 G Ground IN0A 9 A External LC sensor 0 connection IN0B 10 A External LC sensor 0 connection IN1A 11 A External LC sensor 1 connection IN1B 12 A External LC sensor 1 connection IN2A 13 A External LC sensor 2 connection (LDC1314 only) IN2B 14 A External LC sensor 2 connection (LDC1314 only) IN3A 15 A External LC sensor 3 connection (LDC1314 only) IN3B 16 A External LC sensor 3 connection (LDC1314 only) DAP(2) DAP N/A Connect to Ground (1) I = Input, O = Output, P=Power, G=Ground, A=Analog (2) There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the GND pin of the device. Although the DAP can be left floating, for best performance the DAP should be connected to the same potential as the device's GND pin. Do not use the DAP as the primary ground for the device. The device GND pin must always be connected to ground. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LDC1312 LDC1314

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6 Specifications

6.1 Absolute Maximum Ratings

VDD Supply Voltage Range 5 V Vi Voltage on any pin -0.3 VDD+0.3 V IA Input current on any INx pin -8 8 mA ID Input current on any Digital pin -5 5 mA Tj Junction Temperature -55 150 °C Tstg Storage temperature range -65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

LDC1312 in WSON-12 package Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±250 C101(2) LDC1314 in QFN-16 package Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±250 C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V MIN NOM MAX UNIT VDD Supply Voltage 2.7 3.6 V TA Operating Temperature -40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) WSON WQFN UNIT

12 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 50 38 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics(1)

Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V PARAMETER TEST CONDITIONS(2) MIN(3) TYP(4) MAX(3) UNIT POWER VDD Supply Voltage TA = -40°C to +125°C 2.7 3.6 V IDD Supply Current (not including CLKIN = 10MHz (6) 2.1 mAsensor current)(5) IDDSL Sleep Mode Supply Current(5) 35 60 µA ISD Shutdown Mode Supply 0.2 1 µACurrent(5) SENSOR ISENSORMAX Sensor Maximum Current drive HIGH_CURRENT_DRV = b0 1.5 mA DRIVE_CURRENT_CHx = 0xF800RP Sensor RP 1 100 kΩ IHDSENSORMAX High current sensor drive mode: HIGH_CURRENT_DRV = b1 6 mASensor Maximum Current DRIVE_CURRENT_CH0 = 0xF800 Channel 0 onlyRP_HD_MIN Minimum sensor RP 250 Ω fSENSOR Sensor Resonance Frequency TA = -40°C to +125°C 0.001 10 MHz VSENSORMAX Maximum oscillation amplitude 1.8 V(peak) NBITS Number of bits RESET_DEV.OUTPUT_GAIN=b00 12 bits RCOUNT ≥ 0x0400 fCS Maximum Channel Sample Rate single active channel continuous 13.3 kSPSconversion, SCL=400kHz CIN Sensor Pin input capacitance 4 pF MASTER CLOCK fCLKIN External Master Clock Input TA = -40°C to +125°C 2 40 MHzFrequency (CLKIN) CLKINDUTY_MIN External Master Clock minimum 40%acceptable duty cycle (CLKIN) CLKINDUTY_MAX External Master Clock maximum 60%acceptable duty cycle (CLKIN) VCLKIN_LO CLKIN low voltage threshold 0.3*VDD V VCLKIN_HI CLKIN high voltage threshold 0.7*VD VD fINTCLK Internal Master Clock Frequency 35 43.4 55 MHzrange TCf_int_μ Internal Master Clock -13 ppm/°CTemperature Coefficient mean TIMING CHARACTERISTICS tWAKEUP Wake-up Time from SD high-low 2 mstransition to I2C readback (1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Register values are represented as either binary (b is the prefix to the digits), or hexadecimal (0x is the prefix to the digits). Decimal values have no prefix. (3) Limits are ensured by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. (4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. (5) I2C read/write communication and pull-up resistors current through SCL, SDA not included. (6) Sensor inductor: 2 layer, 32 turns/layer, 14mm diameter, PCB inductor with L=19.4µH, RP=5.7kΩ at 2MHz Sensor capacitor: 330pF 1% COG/NP0 Target: Aluminum, 1.5mm thickness Channel = Channel 0 (continuous mode) CLKIN = 40MHz, CHx_FIN_DIVIDER = b0000, CHx_FREF_DIVIDER = b00 0000 0001 CH0_RCOUNT = 0xFFFF, SETTLECOUNT_CH0 = 0x0100 RP_OVERRIDE = b1, AUTO_AMP_DIS = b1, DRIVE_CURRENT_CH0 = 0x9800 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LDC1312 LDC1314

6.6 Switching Characteristics - I2C

(1) This parameter is specified by design and/or characterization and is not tested in production. Figure 1. I2C Timing

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6.7 Typical Characteristics

Figure 2. Active Mode IDD vs. Temperature Figure 3. Active Mode IDD vs. VDD Figure 4. Sleep Mode IDD vs. Temperature Figure 5. Sleep Mode IDD vs. VDD Figure 6. Shutdown Mode IDD vs. Temperature Figure 7. Shutdown Mode IDD vs. VDD

Figure 8. Internal Oscillator Frequency vs. Temperature Figure 9. Internal Oscillator Frequency vs. VDD

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40 MHz40 MHz

7 Detailed Description

7.1 Overview

that is proportional to frequency. This frequency measurement can be converted to an equivalent inductance.

7.2 Functional Block Diagram

Figure 10. Block Diagrams for the LDC1312 (left) and LDC1314 (right) current, using the SD pin. The INTB pin may be configured to notify the host of changes in system status.

7.3 Feature Description

7.3.1 Clocking Architecture

Figure 11 shows the clock dividers and multiplexers of the LDC.

Figure 11. Clocking Diagram Table 1. Clock Configuration Requirements

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Table 2 shows the clock configuration registers for all channels. Table 2. Clock Configuration Registers

7.3.2 Multi-Channel and Single Channel Operation

The multi-channel package of the LDC enables the user to save board space and support flexible system design. that are used to configure either multi-channel or single channel modes. Table 3. Single and Multi-Channel Configuration Registers

The following table illustrates the registers that contain the fixed point sample values for each channel. Table 4. LDC1314/1312 Sample Data Registers 0 DATA_MSB_CH0, addr 0x00 DATA0 [11:0] 12 MSBs of the 12 bit result. 1 DATA_MSB_CH1, addr 0x02 DATA1 [11:0] 12 MSBs of the 12 bit result. 2 DATA_MSB_CH2, addr 0x04 DATA2 [11:0] 12 MSBs of the 12 bit result. 3 DATA_MSB_CH3, addr 0x06 DATA3 [11:0] 12 MSBs of the 12 bit result. (1) Channels 2 and 3 available for LDC1314 only. is the sum of 3 parts: sensor activation time + conversion time + channel switch delay. Table 5 illustrates the registers and values for configuring the settling time for each channel. Figure 12. Multi-channel Mode Sequencing Figure 13. Single-channel Mode Sequencing

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Table 5. Settling Time Register Configuration

0 SETTLECOUNT_CH0, addr 0x10 CH0_SETTLECOUNT (15:0) (CH0_SETTLECOUNT*16)/fREF0

1 SETTLECOUNT_CH1, addr 0x11 CH1_SETTLECOUNT (15:0) (CH1_SETTLECOUNT*16)/fREF1

2 SETTLECOUNT_CH2, addr 0x12 CH2_SETTLECOUNT (15:0) (CH2_SETTLECOUNT*16)/fREF2

3 SETTLECOUNT_CH3, addr 0x13 CH3_SETTLECOUNT (15:0) (CH3_SETTLECOUNT*16)/fREF3

(1) Channels 2 and 3 are available only in the LDC1314. (2) fREFx is the reference frequency configured for the channel.

fSENSORx = Frequency of the Sensor on Channel x
fREFx = Reference frequency for Channel x
QSENSORx = Quality factor of the sensor on Channel x. Q is estimated by: (4) (5) Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08, program the register to 7 or higher). L, RP and C values can be obtained by using Texas Instrument’s WEBENCH® for the coil design. The conversion time represents the number of reference clock cycles used to measure the sensor frequency. It is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is: tCx = (CHx_RCOUNT ˣ 16 + 4) /fREFx (6) The reference count value must be chosen to support the required number of effective bits (ENOB). For example, if an ENOB of 13 bits is required, then a minimum conversion time of 213 = 8192 clock cycles is required. 8192 clock cycles correspond to a CHx_RCOUNT value of 0x0200.

Table 6. Conversion Time Configuration Registers, Channels 0 - 3(1)

0 RCOUNT_CH0, addr 0x08 CH0_RCOUNT (15:0) (CH0_RCOUNT*16)/fREF0

1 RCOUNT_CH1, addr 0x09 CH1_RCOUNT (15:0) (CH1_RCOUNT*16)/fREF1

2 RCOUNT_CH2, addr 0x0A CH2_RCOUNT (15:0) (CH2_RCOUNT*16)/fREF2

3 RCOUNT_CH3, addr 0x0B CH3_RCOUNT (15:0) (CH3_RCOUNT*16)/fREF3

(1) Channels 2 and 3 are available only for LDC1314. also available for interrupt driven system designs (see the STATUS register description in Register Maps). be so large that it masks the LSBs which are changing.

Table 7. Frequency Offset Registers

0 OFFSET_CH0, addr 0x0C CH0_OFFSET [ 15:0 ] fOFFSET0 = CH0_OFFSET * (fREF0/216)

1 OFFSET_CH1, addr 0x0D CH1_OFFSET [ 15:0 ] fOFFSET1 = CH1_OFFSET * (fREF1/216)

2 OFFSET_CH2, addr 0x0E CH2_OFFSET [ 15:0 ] fOFFSET2 = CH2_OFFSET * (fREF2/216)

3 OFFSET_CH3, addr 0x0F CH3_OFFSET [ 15:0 ] fOFFSET3 = CH3_OFFSET * (fREF3/216)

will be lost when gain is applied. Table 8. Output Gain Register (1) Channels 2 and 3 are available for LDC1314 only. reported for each possible gain setting. Figure 14. Conversion Data Output Gain

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DATAx = Conversion result from the DATA_CHx register
CHx_OFFSET = Offset value set in the OFFSET_CHx register
OUTPUT_GAIN = output multiplication factor set in the RESET_DEVICE.OUTPUT_GAIN register (8)

7.3.3 Current Drive Control Registers

last column of the table should be followed. should only be used during system prototyping. recommended for low-precision applications. register bit to b1 to enable this mode. Table 9. Current Drive Control Registers CONFIG, addr 0x1A SENSOR_ACTIVATE_SEL [11] Sets current drive for sensor activation. AUTO_AMP_DIS [10] Disables Automatic amplitude correction. b1 = Increased current drive (> 1.5 mA)0 for Ch 0 in single channel mode only. Cannot be used in multi-channel mode. calibration. Not used for normal operation. calibration. Not used for normal operation. calibration. Not used for normal operation. (1) Channels 2 and 3 are available for LDC1314 only.

Table 9. Current Drive Control Registers (continued) calibration. Not used for normal operation. Figure 15. IDRIVE vs Rp

7.3.4 Device Status Registers

The registers listed in Table 10 may be used to read device status. Table 10. Status Registers Refer to Register Maps section12 fields are available thatAll STATUS, addr 0x18 for a description of the individualcontain various status bits [ 15:0 ] status bits. 15:0 ] error configuration bits. (1) Channels 2 and 3 are available for LDC1314 only.

The error or status register must be unmasked by enabling the appropriate register bit in the
The INTB function must be enabled by setting CONFIG.INTB_DIS to 0

DATA_CHx register is read. Reading also de-asserts INTB.

Device enters Shutdown Mode (SD is asserted)

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I2C read of the STATUS register: Reading the STATUS register will clear any error status bit set in STATUS

Setting register CONFIG.INTB_DIS to b1 disables the INTB function and holds the INTB pin high.

7.3.5 Input Deglitch Filter

example, if the maximum sensor frequency is 2.0 MHz, choose MUX_CONFIG.DEGLITCH = b100 (3.3 MHz). Table 11. Input deglitch filter register (1) Channels 2 and 3 are available for LDC1314 only.

7.4 Device Functional Modes

7.4.1 Startup Mode

configured, exit Sleep Mode by setting CONFIG.SLEEP_MODE_EN to b0. return the device to Sleep Mode, change the appropriate register, and then exit Sleep Mode.

7.4.2 Normal (Conversion) Mode

and generating sample outputs for the active channel(s).

7.4.3 Sleep Mode

register contents are maintained. To exit Sleep Mode, set the CONFIG.SLEEP_MODE_EN register field to 0. error condition and de-assert the INTB pin.

7.4.4 Shutdown Mode

When the SD pin is set to high, the LDC will enter Shutdown Mode. Shutdown Mode is the lowest power state. write from the device via the I2C interface.

7.4.4.1 Reset

return to their default value. This register bit will always return 0b when read.

7.5 Programming

The LDC device uses an I2C interface to access control and data registers.

7.5.1 I2C Interface Specifications

Figure 16. I2C Write Register Sequence Figure 17. I2C Read Register Sequence

7.6 Register Maps

7.6.1 Register List

read and write capability, a ‘R’indicates read-only, and a ‘W’indicates write-only. Figure 18. Register List

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LDC1312,LDC1314 www.ti.com SNOSCZ0 – DECEMBER 2014 ADDRESS NAME DEFAULT VALUE DESCRIPTION 0x06 DATA_CH3 0x0000 Channel 3 Conversion Result and Error Status (LDC1314 only) 0x08 RCOUNT_CH0 0x0080 Reference Count setting for Channel 0 0x09 RCOUNT_CH1 0x0080 Reference Count setting for Channel 1 0x0A RCOUNT_CH2 0x0080 Reference Count setting for Channel 2. (LDC1314 only) 0x0B RCOUNT_CH3 0x0080 Reference Count setting for Channel 3.(LDC1314 only) 0x0C OFFSET_CH0 0x0000 Offset value for Channel 0 0x0D OFFSET_CH1 0x0000 Offset value for Channel 1 0x0E OFFSET_CH2 0x0000 Offset value for Channel 2 (LDC1314 only) 0x0F OFFSET_CH3 0x0000 Offset value for Channel 3 (LDC1314 only) 0x10 SETTLECOUNT_CH0 0x0000 Channel 0 Settling Reference Count 0x11 SETTLECOUNT_CH1 0x0000 Channel 1 Settling Reference Count 0x12 SETTLECOUNT_CH2 0x0000 Channel 2 Settling Reference Count (LDC1314 only) 0x13 SETTLECOUNT_CH3 0x0000 Channel 3 Settling Reference Count (LDC1314 only) 0x14 CLOCK_DIVIDERS_C 0x0000 Reference and Sensor Divider settings for Channel 0 0x15 CLOCK_DIVIDERS_C 0x0000 Reference and Sensor Divider settings for Channel 1 0x16 CLOCK_DIVIDERS_C 0x0000 Reference and Sensor Divider settings for Channel 2 (LDC1314 only) 0x17 CLOCK_DIVIDERS_C 0x0000 Reference and Sensor Divider settings for Channel 3 (LDC1314 only) 0x18 STATUS 0x0000 Device Status Report 0x19 ERROR_CONFIG 0x0000 Error Reporting Configuration 0x1A CONFIG 0x2801 Conversion Configuration 0x1B MUX_CONFIG 0x020F Channel Multiplexing Configuration 0x1C RESET_DEV 0x0000 Reset Device 0x1E DRIVE_CURRENT_CH 0x0000 Channel 0 sensor current drive configuration 0x1F DRIVE_CURRENT_CH 0x0000 Channel 1 sensor current drive configuration 0x20 DRIVE_CURRENT_CH 0x0000 Channel 2 sensor current drive configuration (LDC1314 only) 0x21 DRIVE_CURRENT_CH 0x0000 Channel 3 sensor current drive configuration (LDC1314 only) 0x7E MANUFACTURER_ID 0x5449 Manufacturer ID 0x7F DEVICE_ID 0x3054 Device ID Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LDC1312 LDC1314

7.6.2 Address 0x00, DATA_CH0

Figure 19. Address 0x00, DATA_CH0 Table 12. Address 0x00, DATA_CH0 Field Descriptions

7.6.3 Address 0x02, DATA_CH1

Figure 20. Address 0x02, DATA_CH1 Table 13. Address 0x02, DATA_CH1 Field Descriptions

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7.6.4 Address 0x04, DATA_CH2 (LDC1314 only)

Figure 21. Address 0x04, DATA_CH2 Table 14. Address 0x04, DATA_CH2 Field Descriptions

7.6.5 Address 0x06, DATA_CH3 (LDC1314 only)

Figure 22. Address 0x06, DATA_CH3 Table 15. Address 0x06, DATA_CH3 Field Descriptions

7.6.6 Address 0x08, RCOUNT_CH0

Figure 23. Address 0x08, RCOUNT_CH0

Table 16. Address 0x08, RCOUNT_CH0 Field Descriptions

7.6.7 Address 0x09, RCOUNT_CH1

Figure 24. Address 0x09, RCOUNT_CH1 Table 17. Address 0x09, RCOUNT_CH1 Field Descriptions

7.6.8 Address 0x0A, RCOUNT_CH2 (LDC1314 only)

Figure 25. Address 0x0A, RCOUNT_CH2 Table 18. Address 0x0A, RCOUNT_CH2 Field Descriptions

7.6.9 Address 0x0B, RCOUNT_CH3 (LDC1314 only)

Figure 26. Address 0x0B, RCOUNT_CH3

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Table 19. Address 0x0B, RCOUNT_CH3 Field Descriptions

7.6.10 Address 0x0C, OFFSET_CH0

Figure 27. Address 0x0C, CH0_OFFSET Table 20. CH0_OFFSET Field Descriptions

7.6.11 Address 0x0D, OFFSET_CH1

Figure 28. Address 0x0D, OFFSET_CH1 Table 21. Address 0x0D, OFFSET_CH1 Field Descriptions

7.6.12 Address 0x0E, OFFSET_CH2 (LDC1314 only)

Figure 29. Address 0x0E, OFFSET_CH2 Table 22. Address 0x0E, OFFSET_CH2 Field Descriptions

7.6.13 Address 0x0F, OFFSET_CH3 (LDC1314 only)

Figure 30. Address 0x0F, OFFSET_CH3 Table 23. Address 0x0F, OFFSET_CH3 Field Descriptions

7.6.14 Address 0x10, SETTLECOUNT_CH0

Figure 31. Address 0x10, SETTLECOUNT_CH0 Table 24. Address 0x11, SETTLECOUNT_CH0 Field Descriptions stabilize before initiation of a conversion on Channel 0.

7.6.15 Address 0x11, SETTLECOUNT_CH1

Figure 32. Address 0x11, SETTLECOUNT_CH1

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Table 25. Address 0x12, SETTLECOUNT_CH1 Field Descriptions stabilize before initiation of a conversion on a Channel 1.

7.6.16 Address 0x12, SETTLECOUNT_CH2 (LDC1314 only)

Figure 33. Address 0x12, SETTLECOUNT_CH2 Table 26. Address 0x12, SETTLECOUNT_CH2 Field Descriptions stabilize before initiation of a conversion on Channel 2.

7.6.17 Address 0x13, SETTLECOUNT_CH3 (LDC1314 only)

Figure 34. Address 0x13, SETTLECOUNT_CH3 Table 27. Address 0x13, SETTLECOUNT_CH3 Field Descriptions stabilize before initiation of a conversion on Channel 3.

7.6.18 Address 0x14, CLOCK_DIVIDERS_CH0

Figure 35. Address 0x14, CLOCK_DIVIDERS_CH0 Table 28. Address 0x14, CLOCK_DIVIDERS_CH0 Field Descriptions 0000 Channel 0 Input Divider Sets the divider for Channel 0 input. 15:12 CH0_FIN_DIVIDER R/W b0000: Reserved. Do not use. 11:10 RESERVED R/W 00 Reserved. Set to b00. 0000 reference. Use this to scale the maximum conversion frequency. 9:0 CH0_FREF_DIVIDER R/W b00’0000’0000: Reserved. Do not use.

7.6.19 Address 0x15, CLOCK_DIVIDERS_CH1

Figure 36. Address 0x15, CLOCK_DIVIDERS_CH1 Table 29. Address 0x15, CLOCK_DIVIDERS_CH1 Field Descriptions 0000 Channel 1 Input Divider Sets the divider for Channel 1 input. FIN.15:12 CH1_FIN_DIVIDER R/W b0000: Reserved. Do not use. 11:10 RESERVED R/W 00 Reserved. Set to b00. 0000 reference. Use this to scale the maximum conversion frequency. 9:0 CH1_FREF_DIVIDER R/W b00’0000’0000: Reserved. Do not use.

7.6.20 Address 0x16, CLOCK_DIVIDERS_CH2 (LDC1314 only)

Figure 37. Address 0x16, CLOCK_DIVIDERS_CH2

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Table 30. Address 0x16, CLOCK_DIVIDERS_CH2 Field Descriptions 15:12 CH2_FIN_DIVIDER R/W 0000 Channel 2 Input Divider Sets the divider for Channel 2 input. Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz. b0000: Reserved. Do not use. 0000 reference. Use this to scale the maximum conversion frequency. b00’0000’0000: Reserved. Do not use.

7.6.21 Address 0x17, CLOCK_DIVIDERS_CH3 (LDC1314 only)

Figure 38. Address 0x17, CLOCK_DIVIDERS_CH3 Table 31. Address 0x17, CLOCK_DIVIDERS_CH3 15:12 CH3_FIN_DIVIDER R/W 0000 Channel 3 Input Divider Sets the divider for Channel 3 input. Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz. b0000: Reserved. Do not use. 0000 reference. Use this to scale the maximum conversion frequency.

7.6.22 Address 0x18, STATUS

Figure 39. Address 0x18, STATUS

Table 32. Address 0x18, STATUS Field Descriptions to the Error Channel is read. b00: Channel 0 is source of flag or error. b01: Channel 1 is source of flag or error. b10: Channel 2 is source of flag or error (LDC1314 only). b11: Channel 3 is source of flag or error (LDC1314 only).

13 ERR_UR R 0 Conversion Under-range Error

last read of the STATUS register. channel is the source of this error. 12 ERR_OR R 0 Conversion Over-range Error. read of the STATUS register. channel is the source of this error.

11 ERR_WD R 0 Watchdog Timeout Error

read of the STATUS register. b1: An active channel has generated a Watchdog Timeout error. is the source of this error.

10 ERR_AHE R 0 Amplitude High Error

b1: An active channel has generated an Amplitude High error. is the source of this error.

9 ERR_ALE R 0 Amplitude Low Error

b1: An active channel has generated an Amplitude Low error. is the source of this error.

8 ERR_ZC R 0 Zero Count Error

for all active channels is now available.

3 CH0_UNREADCONV R 0 Channel 0 Unread Conversion b0: No unread conversion is

b1: An unread conversion is present for Channel 0. Read Register DATA_CH0 to retrieve conversion results.

2 CH1_ UNREADCONV R 0 Channel 1 Unread Conversion b0: No unread conversion is

b1: An unread conversion is present for Channel 1. Read Register DATA_CH1 to retrieve conversion results.

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Table 32. Address 0x18, STATUS Field Descriptions (continued)

1 CH2_ UNREADCONV R 0 Channel 2 Unread Conversion b0: No unread conversion is

b1: An unread conversion is present for Channel 2.

0 CH3_ UNREADCONV R 0 Channel 3 Unread Conversion

b0: No unread conversion is present for Channel 3. b1: An unread conversion is present for Channel 3.

7.6.23 Address 0x19, ERROR_CONFIG

Figure 40. Address 0x19, ERROR_CONFIG Table 33. Address 0x19, ERROR_CONFIG

15 UR_ERR2OUT R/W 0 Under-range Error to Output Register

14 OR_ERR2OUT R/W 0 Over-range Error to Output Register

b0: Do not report Over-range errors in the DATA_CHx registers.

13 WD_ ERR2OUT R/W 0 Watchdog Timeout Error to Output Register

channel that generated the error.

12 AH_ERR2OUT R/W 0 Amplitude High Error to Output Register

channel that generated the error.

11 AL_ERR2OUT R/W 0 Amplitude Low Error to Output Register

channel that generated the error.

7 UR_ERR2INT R/W 0 Under-range Error to INTB

updating STATUS.ERR_UR register field.

Table 33. Address 0x19, ERROR_CONFIG (continued)

6 OR_ERR2INT R/W 0 Over-range Error to INTB

updating STATUS.ERR_OR register field.

5 WD_ERR2INT R/W 0 Watchdog Timeout Error to INTB b0: Do not report Under-range

errors by asserting INTB pin and STATUS register. updating STATUS.ERR_WD register field.

4 AH_ERR2INT R/W 0 Amplitude High Error to INTB b0: Do not report Amplitude High

errors by asserting INTB pin and STATUS register. updating STATUS.ERR_AHE register field.

3 AL_ERR2INT R/W 0 Amplitude Low Error to INTB b0: Do not report Amplitude Low

errors by asserting INTB pin and STATUS register. updating STATUS.ERR_ALE register field.

2 ZC_ERR2INT R/W 0 Zero Count Error to INTB b0: Do not report Zero Count errors by

asserting INTB pin and STATUS register. updating STATUS. ERR_ZC register field.

1 Reserved R/W 0 Reserved (set to b0)

0 DRDY_2INT R/W 0 Data Ready Flag to INTB b0: Do not report Data Ready Flag by

asserting INTB pin and STATUS register. STATUS. DRDY register field.

7.6.24 Address 0x1A, CONFIG

Figure 41. Address 0x1A, CONFIG Table 34. Address 0x1A, CONFIG Field Descriptions

13 SLEEP_MODE_EN R/W 1 Sleep Mode Enable

Enter or exit low power Sleep Mode. b1: Device is in Sleep Mode.

30 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated

Table 34. Address 0x1A, CONFIG Field Descriptions (continued)

12 RP_OVERRIDE_EN R/W 0 Sensor RP Override Enable

11 SENSOR_ACTIVATE_SEL R/W 1 Sensor Activation Mode Selection. Set the mode for sensor initialization. sensor current for a shorter sensor activation time. activation to minimize power consumption.

10 AUTO_AMP_DIS R/W 0 Automatic Sensor Amplitude Correction Disable

algorithm and stop the updating of the CHx_INIT_IDRIVE field.

9 REF_CLK_SRC R/W 0 Select Reference Frequency Source b0: Use Internal oscillator

8 RESERVED R/W 0 Reserved. Set to b0.

7 INTB_DIS R/W 0 INTB Disable

b0: INTB pin will be asserted when status register updates.

6 HIGH_CURRENT_DRV R/W 0 High Current Sensor Drive

b1: The LDC will drive channel 0 with current >1.5mA.

7.6.25 Address 0x1B, MUX_CONFIG

Figure 42. Address 0x1B, MUX_CONFIG Table 35. Address 0x1B, MUX_CONFIG Field Descriptions

15 AUTOSCAN_EN R/W 0 Auto-Scan Mode Enable

CONFIG.ACTIVE_CHAN register field. MUX_CONFIG.RR_SEQUENCE register field.

Table 35. Address 0x1B, MUX_CONFIG Field Descriptions (continued) 2:0 DEGLITCH R/W 111 Input deglitch filter bandwidth.

7.6.26 Address 0x1C, RESET_DEV

Figure 43. Address 0x1C, RESET_DEV Table 36. Address 0x1C, RESET_DEV Field Descriptions

15 RESET_DEV R/W 0 Device Reset

Write b1 to reset the device. Will always readback 0.

7.6.27 Address 0x1E, DRIVE_CURRENT_CH0

Figure 44. Address 0x1E, DRIVE_CURRENT_CH0

32 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated

Table 37. Address 0x1E, DRIVE_CURRENT_CH0 Field Descriptions conversion time of Channel 0 sensor clock. RP_OVERRIDE_EN bit must be set to 1. initial Amplitude Calibration phase. sensor clock if the AUTO_AMP_DIS field is NOT set.

7.6.28 Address 0x1F, DRIVE_CURRENT_CH1

Figure 45. Address 0x1F, DRIVE_CURRENT_CH1 Table 38. Address 0x1F, DRIVE_CURRENT_CH1 Field Descriptions conversion time of Channel 1 sensor clock. RP_OVERRIDE_EN bit must be set to 1. initial Amplitude Calibration phase. sensor clock if the AUTO_AMP_DIS field is NOT set.

7.6.29 Address 0x20, DRIVE_CURRENT_CH2 (LDC1314 only)

Figure 46. Address 0x20, DRIVE_CURRENT_CH2 Table 39. Address 0x20, DRIVE_CURRENT_CH2 Field Descriptions + conversion time of Channel 2 sensor clock. RP_OVERRIDE_EN bit must be set to 1.

Table 39. Address 0x20, DRIVE_CURRENT_CH2 Field Descriptions (continued) initial Amplitude Calibration phase. sensor clock if the AUTO_AMP_DIS field is NOT set.

7.6.30 Address 0x21, DRIVE_CURRENT_CH3 (LDC1314 only)

Figure 47. Address 0x21, DRIVE_CURRENT_CH3 Table 40. DRIVE_CURRENT_CH3 Field Descriptions + conversion time of Channel 3 sensor clock. RP_OVERRIDE_EN bit must be set to 1. initial Amplitude Calibration phase. sensor clock if the AUTO_AMP_DIS field is NOT set.

7.6.31 Address 0x7E, MANUFACTURER_ID

Figure 48. Address 0x7E, MANUFACTURER_ID Table 41. Address 0x7E, MANUFACTURER_ID Field Descriptions

7.6.32 Address 0x7F, DEVICE_ID

Figure 49. Address 0x7F, DEVICE_ID

Table 42. Address 0x7F, DEVICE_ID Field Descriptions

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Theory of Operation

8.1.1.1 Conductive Objects in an EM Field

current) on the surface of the conductor. Figure 50. Conductor in AC Magnetic Field sensor and the target as coupled coils.

8.1.1.2 L-C Resonators

L-C construction, as shown in Figure 51.

2 LC Q LC 2 LCQ

Figure 51. Electrical Model of the L-C Tank Sensor In brief, an oscillator is constructed by combining a frequency selective circuit with a gain block in a closed loop.

C is the sensor capacitance (CTANK + CPAR)
L is the inductance (9) The value of RP can be approximated using: where

and C are calculated. See http://www.ti.com/webench. coil (23 turns, 4-mil trace width, 4-mil spacing between traces, 1-oz copper thickness, FR4). Figure 52. Example RP vs. Distance with a 14-mm PCB Coil and 2mm Thick Stainless Steel Target It is important to configure the LDC current drive so that the sensor will still oscillate at the minimum RP value. Registers for details on setting the current drive.

L(d) is the measured sensor inductance, for a distance d between the sensor coil and target
Linf is the inductance of the sensing coil without a conductive target (target at infinite distance)
M(d) is the mutual inductance
fSENSOR = sensor oscillation frequency for a distance d between the sensor coil and target
C = CTANK + CPAR (11) Figure 53 shows an example of variation in sensor frequency and inductance as a function of distance for a 14- mm diameter PCB coil (23 turns, 4-mil trace width, 4-mil spacing between traces, 1-oz copper thickness, FR4).

Figure 53. Example Sensor Frequency, Inductance vs. Target Distance geometries. Note that the additional temperature drift of the sensor capacitor must also be taken into account.

8.2 Typical Application

connecting a reference coil. Figure 54. Example Multi-Channel Application - LDC1312

LDC1312,LDC1314 SNOSCZ0 – DECEMBER 2014 www.ti.com Typical Application (continued)

8.2.1 Design Requirements

Design example in which Sensor 0 is used for proximity measurement and Sensor 1 is used for temperature compensation:
using WEBENCH for coil design
Target distance = 0.1 cm
Distance resolution = 0.2 µm
Target diameter = 1 cm
Target material = stainless steel (SS416)
Number of PCB layers for the coil = 2
The application requires 1kSPS ( TSAMPLE = 1000 µs)

8.2.2 Detailed Design Procedure

The target distance, resolution and diameter are used as inputs to WEBENCH to design the sensor coil, The resulting coil design is a 2 layer coil, with an area of 2.5 cm2, diameter of 1.77 cm, and 39 turns. The values for RP, L and C are: RP = 6.6 kΩ, L = 43.9 µH, C = 100 pF. Using L and C, fSENSOR = 1/2π√(LC) = 1/2π√(43.9*10-6 * 100*10-12) = 2.4 MHz Using a system master clock of 40 MHz applied to the CLKIN pin allows flexibility for setting the internal clock frequencies. The sensor coil is connected to channel 0 (IN0A and IN0B pins). After powering on the LDC, it will be in Sleep Mode. Program the registers as follows (example sets registers for channel 0 only; channel 1 registers can use equivalent configuration): 1. Set the dividers for channel 0. (a) Because the sensor freqeuncy is less than 8.75 MHz, the sensor divider can be set to 1, which means setting field CH0_FIN_DIVIDER to 0x1. By default, fIN0 = fSENSOR = 2.4MHz. (b) The design constraint for fREF0 is > 4 × fSENSOR. A 20 MHz reference frequency satisfies this constraint, so the reference divider should be set to 2. This is done by setting the CH0_FREF_DIVIDER field to 0x02. (c) The combined value for Chan. 0 divider register (0x14) is 0x1002. 2. Program the settling time for Channel 0. The calculated Q of the coil is 10(see Multi-Channel and Single Channel Operation). (a) CH0_SETTLECOUNT ≥ Q × fREF0 / (16 × fSENSOR0) → 5.2, rounded up to 6. To provide margin to account for system tolerances, a higher value of 10 is chosen. (b) Register 0x10 should be programmed to a minimum of 10. (c) The settle time is: (10 x 16)/20,000,000 = 8 µs (d) The value for Chan. 0 SETTLECOUNT register (0x10) is 0x000A. 3. The channel switching delay is ~1μs for fREF = 20 MHz (see Multi-Channel and Single Channel Operation) 4. Set the conversion time by the programming the reference count for Channel 0. The budget for the conversion time is : TSAMPLE – settling time – channel switching delay = 1000 – 8 – 1 = 991 µs (a) To determine the conversion time register value, use the following equation and solve for CH0_RCOUNT: Conversion Time (tC0)= (CH0_RCOUNTˣ16)/fREF0. (b) This results in CH0_RCOUNT having a value of 1238 decimal (rounded down) (c) Set the CH0_RCOUNT register (0x08) to 0x04D6. 5. Use the default values for the ERROR_CONFIG register (address 0x19). By default, no interrupts are enabled 6. Sensor drive current: to set the CH0_IDRIVE field value, read the value from Figure 15 using RP = 6.6 kΩ. In this case the IDRIVE value should be set to 18 (decimal). The INIT_DRIVE current field should be set to 0x00. The combined value for the DRIVE_CURRENT_CH0 register (addr 0x1E) is 0x9000. 7. Program the MUX_CONFIG register (a) Set the AUTOSCAN_EN to b1 bit to enable sequential mode (b) Set RR_SEQUENCE to b00 to enable data conversion on two channels (channel 0, channel 1) (c) Set DEGLITCH to b100 to set the input deglitch filter bandwidth to 3.3MHz, the lowest setting that exceeds the oscillation tank frequency. (d) The combined value for the MUX_CONFIG register (address 0x1B) is 0x820C

Product Folder Links: LDC1312 LDC1314

Finally, program the CONFIG register as follows:

(a) Set the ACTIVE_CHAN field to b00 to select channel 0. (b) Set SLEEP_MODE_EN field to b0 to enable conversion. (c) Set RP_OVERRIDE_EN to b1 to disable auto-calibration. (f) Set the REF_CLK_SRC field to b1 to use the external clock source. (g) Set the other fields to their default values. (h) The combined value for the CONFIG register (address 0x1A) is 0x1601.

8.2.3 Recommended Initial Register Configuration Values

Table 43. Recommended Initial Register Configuration Values (Single-channel operation) Table 44. Recommended Initial Register Configuration Values (Multi-channel operation)

Table 44. Recommended Initial Register Configuration Values (Multi-channel operation) (continued) configuration is not permitted while the LDC is in active mode.

8.2.4 Application Curves

Sensor inductor: 2 layer, 32 turns/layer, 14mm diameter, PCB inductor with L=19.4 µH, RP=5.7 kΩ at 2 MHz
Sensor capacitor: 330pF 1% COG/NP0
Target: Aluminum, 1.5 mm thickness
Channel = Channel 0 (continuous mode)
CLKIN = 40MHz, CHx_FIN_DIVIDER = 0x01, CHx_FREF_DIVIDER = 0x001
CH0_RCOUNT = 0xFFFF, SETTLECOUNT_CH0 = 0x0100
RP_OVERRIDE = 1, AUTO_AMP_DIS = 1, DRIVE_CURRENT_CH0 = 0x9800

Figure 55. Typical Output Code vs. Target Distance (0 to Figure 56. Measurement precision in Distance vs. Target

8.2.5 Inductor Self-Resonant Frequency

capacitance is not well-controlled or stable, it is recommended that: fSENSOR < 0.8 × fSR. Figure 57. Example Coil Inductance vs. Frequency

LDC1312,LDC1314 www.ti.com SNOSCZ0 – DECEMBER 2014 In Figure 57, the inductor has a SRF at 6.38 MHz; therefore the inductor should not be operated above 0.8×6.38 MHz, or 5.1 MHz.

9 Power Supply Recommendations

The LDC requires a voltage supply within 2.7 V and 3.6 V. A multilayer ceramic bypass X7R capacitor of 1μF between the VDD and GND pins is recommended. If the supply is located more than a few inches from the LDC, additional bulk capacitance may be required in addition to the ceramic bypass capacitor. An electrolytic capacitor with a value of 10μF is a typical choice.
The optimum placement is closest to the VDD and GND terminals of the device. Care should be taken to minimize the loop area formed by the bypass capacitor connection, the VDD terminal, and the GND terminal of the IC. See Figure 58 and Figure 58 for a layout example.

10 Layout

10.1 Layout Guidelines

Avoid long traces to connect the sensor to the LDC. Short traces reduce parasitic capacitances between sensor inductor and offer higher system performance.

10.2 Layout Example

Figure 58. Example PCB Layout: Top Layer (Signal)

Figure 59. Example PCB Layout: Mid-layer 1 (GND)

Figure 60. Example PCB Layout: Mid-layer 2 (Power)

Figure 61. Example PCB Layout: Bottom Layer (Signal)

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

Texas Instruments' WEBENCH tool: http://www.ti.com/webench

11.2 Documentation Support

11.2.1 Related Documentation

LDC1000 Temperature Compensation (SNAA212)

11.3 Related Links

resources, tools and software, and quick access to sample or buy. Table 45. Related Links

11.4 Trademarks

WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 18-Dec-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LDC1312DNTR ACTIVE WSON DNT 12 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LDC1312 LDC1312DNTT ACTIVE WSON DNT 12 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LDC1312 LDC1314RGHR ACTIVE WQFN RGH 16 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LDC1314 LDC1314RGHT ACTIVE WQFN RGH 16 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LDC1314 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 18-Dec-2014 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2014 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LDC1312DNTR WSON DNT 12 4500 367.0 367.0 35.0 LDC1312DNTT WSON DNT 12 250 210.0 185.0 35.0 LDC1314RGHR WQFN RGH 16 4500 367.0 367.0 35.0 LDC1314RGHT WQFN RGH 16 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2014 Pack Materials-Page 2

DNT0012B WSON - 0.8mm max height SON (PLASTIC SMALL OUTLINE - NO LEAD) www.ti.com MECHANICAL DATA 4214928/A 03/2013 SDA12B (Rev A) 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to a thermal pad on the board for thermal and mechanical performance. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). NOTES:

www.ti.com PACKAGE OUTLINE C 16X 0.3 0.2 2.6 0.1 12X 0.5 16X 0.5 0.3 1.5

0.8 MAX

A 4.1 3.9 B 4.1 3.9 0.3 0.2 0.5 0.3 (0.1) TYP 4214978/A 10/2013 WQFN - 0.8 mm max heightRGH0016A WQFN PIN 1 INDEX AREA SEATING PLANE 4 9 5 8 16 13(OPTIONAL) PIN 1 ID DETAIL SEE TERMINAL NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

0.1 C A B

0.05 C SCALE 3.500 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT ( 2.6)

0.07 MIN

0.07 MAX

16X (0.6) 16X (0.25) (3.8) (3.8) 5X ( ) VIA 0.2 12X (0.5) (0.25) TYP (1) (1) 4214978/A 10/2013 WQFN - 0.8 mm max heightRGH0016A WQFN SYMM SEE DETAILS 5 8 1316 SYMM LAND PATTERN EXAMPLE SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL SOLDER MASK DEFINED METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (3.8) 16X (0.6) 16X (0.25) 4X (1.15) (0.25) TYP 12X (0.5) (3.8) (0.675) (0.675) 4214978/A 10/2013 WQFN - 0.8 mm max heightRGH0016A WQFN NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM TYP METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED SOLDER COVERAGE BY AREA SCALE:15X 5 8 1316 SYMM

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Product Information

LDC1312DNTT specifications and overview.

Summary

Multi-Channel 12-Bit Inductance to Digital Converter (LDC) for Inductive Sensing

Description

Multi-Channel 12-Bit Inductance to Digital Converter (LDC) for Inductive Sensing

Source title LDC1312DNTT Datasheet(PDF) - Texas Instruments

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