LDC1000-Q1_16 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 40
Technical content
LDC Output (Rp) 0.25 0.5 0.75 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LDC1000-Q1 SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 LDC1000-Q1InductancetoDigitalConverter
1 Features 3 Description
Inductive sensing is a contactless, short-range 1• Qualified for Automotive Applications sensing technology that enables low-cost, high-• AEC-Q100 Qualified With the Following Results: resolution sensing of conductive targets in the – Device Temperature Grade 0: –40°C to 150°C presence of dust, dirt, oil, and moisture, making this Ambient Operating Temperature Range E technology extremely reliable in harsh environments. Using a coil that can be created for example on a– Device Temperature Grade 1: –40°C to 125°C PCB as a sensing element, the LDC1000-Q1 deviceAmbient Operating Temperature Range Q enables ultra-low cost system solutions.– Device HBM ESD Classification Level 2 Inductive sensing technology enables precise– Device CDM ESD Classification Level C6 measurement of linear or angular position,
- Magnet-Free Operation displacement, motion, compression, vibration, metal composition, and many other applications in markets• Sub-Micron Precision including automotive, consumer, computer, industrial,• Adjustable Sensing Range (through Coil Design) medical, and communications. Inductive sensing• Lower System Cost offers better performance and reliability at lower cost
- Remote Sensor Placement (Decoupling the LDC than other competitive solutions. from Harsh Environments) The LDC1000-Q1 device is the first automotive-
- High Durability (by Virtue of Contact-Less qualified LDC, offering the benefits of inductive Operation) sensing in a low-power, small-footprint solution. The product is available in a 16-pin TSSOP package and• Insensitivity to Environmental Interference (such offers several modes of operation. An SPI interfaceas Dirt, Dust, Water, Oil) simplifies connection to an MCU.• Supply Voltage, Analog: 4.75 to 5.25 V
- Supply Voltage, IO: 1.8 to 5.25 V Device Information(1)
- Supply Current (Without LC Tank): 1.7 mA PART NUMBER PACKAGE BODY SIZE (NOM)
- RP Resolution: 16-bit LDC1000-Q1 TSSOP (16) 5.00 mm × 4.40 mm
- L Resolution: 24-bit (1) For all available packages, see the orderable addendum at the end of the data sheet.• LC Frequency Range: 5 kHz to 5 MHz Typical Application — Axial Distance Sensing2 Applications
- Drive-by-Wire Systems
- Gear-Tooth Counting
- Flow Meters
- Push-Button Switches
- Rotational Position Sensor
- Linear Position Sensor
- Pedal Position Sensor
- Throttle Position Sensor An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 www.ti.com Table of Contents
4 Revision History
Changes from Revision A (September 2014) to Revision B Page Changes from Original (September 2014) to Revision A Page
2 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: LDC1000-Q1
www.ti.com SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014
5 Pin Configuration and Functions
TYPE(1) DESCRIPTION NO. NAME 1 SCLK DI SPI clock input. The SCLK pin is used to clock-out and clock-in the data from or into the chip SPI CSB. Multiple devices can be connected on the same SPI bus and the CSB pin can be used to2 CSB DI select which device is communicated with. SPI Slave Data In (Master Out Slave In). This pin should be connected to the Master Out Slave In of3 SDI DI the master device.
4 VIO P Digital IO Supply
5 SDO DO SPI Slave Data Out (Master In Slave Out). This pin is high-Z when the CSB pin is high.
6 DGND P Digital ground
7 CFB A LDC filter capacitor
8 CFA A LDC filter capacitor
9 INA A External LC Tank. Connect this pin to an external LC tank. 10 INB A External LC Tank. Connect this pin to an external LC tank.
11 GND P Analog ground
12 VDD P Analog supply
13 CLDO A LDO bypass capacitor. Connect a 56-nF capacitor from this pin to GND. 14 TBCLK/XIN DI/A External time-base clock and XTAL. This pin is either an external clock or is connected to a crystal. XTAL. Crystal out. Connecting an 8-Mhz crystal between the TBCLK/XIN pin and the XOUT pin with 15 XOUT A 20-pF capacitor from each pin to ground is recommended. This pin should be floating when an external clock is used. Configurable interrupt. This pin can be configured to function in three different ways (threshold detect,16 INTB DO wakeup, or DRDYB) by programing the INT pin mode register. (1) DO: Digital Output, DI: Digital Input, P: Power, A: Analog Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LDC1000-Q1
SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Analog supply voltage VDD – GND 5.5 V IO supply voltage VIO – GND 5.5 V Voltage On any pin –0.3 VDD + 0.3 V On any digital pin –0.3 VIO + 0.3 V Input Current INA and INB 8 mA Junction Temperature, TJ 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
Tstg Storage temperature range –65 150 °C Human body model (HBM), per AEC Q100-002(1) –2000 2000 V(ESD) Electrostatic discharge V Charged device model (CDM), per AEC Q100-011, all pins –1000 1000 (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD Analog supply voltage (VDD – GND) 4.75 5.25 V VIO IO supply voltage (VIO – GND) 1.8 5.25 V VDD – VIO ≥0 V Operating temperature (see the Mechanical, Grade 0 (temperature range E) –40 150 TA Packaging, and Orderable Information section for °CGrade 1 (temperature range Q) –40 125package options)
6.4 Thermal Information
THERMAL METRIC(1) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 106.3 RθJC(top) Junction-to-case (top) thermal resistance 40.8 RθJB Junction-to-board thermal resistance 51.3 °C/W ψJT Junction-to-top characterization parameter 3.6 ψJB Junction-to-board characterization parameter 50.8 RθJC(bot) Junction-to-case (bottom) thermal resistance — (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: LDC1000-Q1
www.ti.com SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014
6.5 Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 5 V, VIO = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER VDD Analog supply voltage 4.75 5 5.25 V VIO IO supply voltage VIO ≤ VDD 1.8 3.3 5.25 V Does not include the LCIDD Supply current 1.7 2.3 mAtank current IIO IO supply current Static current 14 µA IDD(LP) Low-power mode supply current Without LC tank 250 µA From POR to ready-to- t(start) Start-up time convert. Crystal not used 2 ms for frequency counter LDC fsensor_min Minimum sensor frequency 5 kHz fsensor_max Maximum sensor frequency 5 MHz Asensor_min Minimum sensor amplitude 1 VPP Asensor_max Maximum sensor amplitude 4 VPP Oscillation start-up time trec Recovery time after RP under-range 10 1 / fsensor condition ZRP_min Minimum sensor RP range 798 Ω RRP_max Maximum sensor RP range 3.93 MΩ RRP_res RP measurement resolution 16 Bits Minimum programmabletres(min) Minimum response time 192 × 1 / fsensor ssettling time of digital filter Maximum programmabletres(max) Maximum response time 6144 × 1 / fsensor ssettling time of digital filter EXTERNAL CLOCK AND CRYSTAL FOR FREQUENCY COUNTER fref Crystal frequency 8 MHz txtalst Crystal startup time 30 ms External clock frequency 8 MHz External clock input high voltage VIO V DIGITAL I/O CHARACTERISTICS 0.8 ×VIH Logic 1 input voltage VVIO VIL Logic 0 input voltage 0.2 × VIO V VOH Logic 1 output voltage I(SOURCE) = 400 µA VIO– 0.3 V VOL Logic 0 output voltage I(SINK) = 400 µA 0.3 V IlkgIO Digital IO leakage current –500 500 nA Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LDC1000-Q1
6.6 Timing Requirements
Figure 1. Write Timing Diagram Figure 2. Read Timing Diagram
6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
6.7 Typical Characteristics
Figure 3. RP vs Distance Figure 4. Proximity Data vs Distance
L C Frequency Counter TBCLK/XIN XOUT Threshold Detector Frequency Counter Data Register Proximity Data RegisterLDC CSB LDC1000-Q1 SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 www.ti.com
7 Detailed Description
7.1 Overview
The LDC1000-Q1 device is an inductance-to-digital converter that simultaneously measures the impedance and resonant frequency of an LC resonator. The device accomplishes this task by regulating the oscillation amplitude in a closed-loop configuration to a constant level, while monitoring the energy dissipated by the resonator. By monitoring the amount of power injected into the resonator, the LDC1000-Q1 device can determine the value of RP. When the value is determined, the device returns this as a digital value which is inversely proportional to RP. In addition, the LDC1000-Q1 device also measure the oscillation frequency of the LC circuit. This frequency is used to determine the inductance of the LC circuit. The device outputs a digital value that is inversely proportional to frequency. The threshold detector block provides a comparator with hysteresis. With the threshold registers programed and comparator enabled, the proximity data register is compared with threshold registers and INTB pin indicates the output. The device has a simple 4-wire SPI interface. The INTB pin provides multiple functions which are programmable with SPI. The device has separate analog and I/O supplies. The analog supply operates at 5 V and the I/O operates at 1.8 to 5 V. The integrated LDO requires a 56-nF capacitor connected from the CLDO pin to GND.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Inductive Sensing
An alternating current (AC) flowing through a coil generates an AC magnetic field. If a conductive material, such as a metal target, is brought into the vicinity of the coil, this magnetic field induces circulating currents (eddy currents) on the surface of the target. These eddy currents are a function of the distance, size, and composition of the target. These eddy currents then generate a magnetic field that opposes the original field generated by the coil. This mechanism is best compared to a transformer, where the coil is the primary core and the eddy current is the secondary core. The inductive coupling between both cores depends on distance and shape. Hence the resistance and inductance of the secondary core (eddy current), shows up as a distant dependent resistive and inductive component on the primary side (coil). Figure 5 through Figure 8 show a simplified circuit model.
8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: LDC1000-Q1
Figure 8. Equivalent Resistance of rs in Parallel With LC Tank Figure 9. Typical RP versus Distance With a 14-mm PCB Coil
7.3.2 Measuring Parallel Resonance Impedance and Inductance with LDC1000-Q1
determine the inductance of the LC circuit. The oscillation frequency is returned as a digital value. of Rp_Min and Rp_Max section for how to set these registers.
10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 www.ti.com Feature Description (continued)
7.3.2.1 Measuring Inductance
The LDC1000-Q1 device measures the frequency of the oscillation of the sensor by a frequency counter. The frequency counter timing is set by an external clock or crystal. Either the external clock (8 MHz typical) from a microcontroller can be provided on the TBCLK/XIN pin or a crystal can be connected on the TBCLK/XIN and XOUT pins. The clock mode is controlled through clock configuration register (address 0x05). The sensor resonance frequency is derived from the frequency-counter register value (see the Frequency Counter LSB (offset = 0x23) [reset = NA] section through the Frequency Counter MSB (offset = 0x25) [reset = NA] section) as shown in Equation 7. fsensor = (1/3) × (fext / fcount) × tres where
- fsensor is the sensor frequency
- fext is the frequency of the external clock or crystal
- fcount is the value obtained from the Frequency Counter Data register (see the Frequency Counter LSB (offset = 0x23) [reset = NA] section through the Frequency Counter MSB (offset = 0x25) [reset = NA] section)
- tres is the programmed response time (see the LDC Configuration (offset = 0x04) [reset = 0x1B] section) (7) The inductance in H can be calculated with Equation 8. L=1 / [C × (2 × π × fsensor)2] where
- C is the parallel capacitance of the resonator (8)
7.3.2.1.1 Example
If the following values are selected, fext = 6 Mhz, tres = 6144, C = 10 0pF, and measured fcount = 3000 (decimal) (see the Frequency Counter LSB (offset = 0x23) [reset = NA] section through the Frequency Counter MSB (offset = 0x25) [reset = NA] section) then: fsensor = 1/3 × (6000000 / 3000) × (6144) = 4.096 MHz (9) Now use Equation 10. L = 1 / [C × (2 × π × fsensor)2] where
- L = 15.098 µH (10) The accuracy of measurement largely depends upon the choice of the external time-base clock (TBCLK) or the crystal oscillator (XIN and XOUT).
7.4 Device Functional Modes
7.4.1 INTB Pin Modes
The INTB pin is a configurable output pin which can be used to drive an interrupt on an MCU. The LDC1000-Q1 device provides three different modes on the INTB pin which include: 1. Comparator mode 2. Wake-up mode 3. DRDY mode The LDC1000-Q1 device has a built-in high trigger and low trigger threshold registers that can be a comparator with programmable hysteresis or a special mode that is used to wake-up an MCU. The following sections describe these modes in detail.
7.4.1.1 Comparator Mode
In the comparator mode, the INTB pin is asserted or de-asserted when the proximity register value increases above the threshold high registers or decreases below the threshold low registers respectively. In this mode, the function of the LDC1000-Q1 device is a proximity switch with programmable hysteresis.
12 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: LDC1000-Q1
Figure 13. Behavior of the INTB Pin in Comparator Mode
7.4.1.2 Wake-Up Mode
registers and is deasserted when wake-up mode is disabled in the INTB pin mode register. This mode can wake-up an MCU that is in sleep mode to conserve power. Figure 14. Behavior of the INTB Pin in Wake-Up Mode
7.4.1.3 DRDYB Mode
Figure 15. Behavior of the INTB Pin in DRDYB Mode
7.5 Programming
7.5.1 Digital Interface
device is an SPI slave device and does not initiate any transactions.
7.5.1.1 SPI Description
Figure 16. Serial Interface Protocol
14 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
www.ti.com SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 Programming (continued) Each assertion of the chip select bar (CSB) begins a new register access. The R/W bit in the command field configures the direction of the access. A value of 0 indicates a write operation and a value of 1 indicates a read operation. All output data is driven on the falling edge of the serial clock SCLK, and all input data is sampled on the rising edge of the serial clock SCLK. Data is written into the register on the rising edge of the 16th clock. Deasserting the CSB pin after the 16th clock is required. No data write occurs if the CSB pin is deasserted before the 16th clock.
7.5.1.2 Extended SPI Transactions
A transaction can be extended to multiple registers by keeping the CSB pin asserted beyond the stated 16 clocks. In this mode, the register addresses increment automatically. The CSB pin must be asserted during 8 × (1+ N) clock cycles of SCLK, where N is the amount of bytes to write or read during the transaction. During an extended read access, the SDO pin outputs register contents every 8 clock cycles after the initial 8 clocks of the command field. During an extended write access, the data is written to the registers every 8 clock cycles after the initial 8 clocks of the command field. Extended transactions can be used to read 16-bits of proximity data and 24-bits of frequency data all in one SPI transaction by initiating a read from register 0x21. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LDC1000-Q1
7.6 Register Map
Table 1. Register Map(1)(2) (1) Values of bits which are unused should be set to default values only. (3) When the device is in active mode (the PWR_MODE bit is SET), registers 0x01 through 0x05 are read only (R).
16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
7.6.1 Register Description
7.6.1.1 Revision ID (offset = 0x00) [reset = 0x80]
Figure 17. Revision ID Register Table 2. Revision ID Field Descriptions
7.6.1.2 Rp_MAX (offset = 0x01) [reset = 0x0E]
Figure 18. Rp_MAX Register Table 3. Rp_MAX Field Descriptions 7-0 Rp Maximum R/W 0x0E Maximum RP that the LDC1000-Q1 device must measure. Configures the input dynamic range of the LDC1000-Q1 device.
18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
7.6.1.3 Rp_MIN (offset = 0x02) [reset = 0x14]
Figure 19. Rp_MIN Register Table 4. Rp_MIN Field Descriptions 7-0 Rp Minimum R/W 0x014 Minimum RP that the LDC1000-Q1 device must measure. Configures the input dynamic range of the LDC1000-Q1 device.
7.6.1.4 Sensor Frequency (offset = 0x03) [reset = 0x45]
Figure 20. Sensor Frequency Register Table 5. Sensor Frequency Field Descriptions
- N = Register Value. Round to nearest value.
- f = 20% below resonating frequency, Hz (11) Example: Sensor frequency (fsensor) = 1 MHz f = 0.8 × 1 MHz = 800 KHz (12) N = 68.94 × log10(800 KHz / 2000) = Round to nearest whole number (179.38) = 179 (Value to be programmed in the sensor frequency register) (13)
7.6.1.5 LDC Configuration (offset = 0x04) [reset = 0x1B]
Figure 21. LDC Configuration Register Table 6. LDC Configuration Field Descriptions
20 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
7.6.1.6 Clock Configuration (offset = 0x05) [reset = 0x01]
Figure 22. Clock Configuration Register Table 7. Clock Configuration Field Descriptions
1 CLK_SEL R/W 0x01 1:External crystal used for frequency counter (XIN or
0:Enable External time base clock.
7.6.1.7 Comparator Threshold High LSB (offset = 0x06) [reset = 0xFF]
Figure 23. Comparator Threshold High LSB Register Table 8. Comparator Threshold High LSB Field Descriptions updating the threshold high register.
7.6.1.8 Comparator Threshold High MSB (offset = 0x07) [reset = 0xFF]
Figure 24. Comparator Threshold High MSB Register Table 9. Comparator Threshold High MSB Field Descriptions register write register 0x06 first and then 0x07.
7.6.1.9 Comparator Threshold Low LSB (offset = 0x08) [reset = 0x00]
Figure 25. Comparator Threshold Low LSB Register Table 10. Comparator Threshold Low LSB Field Descriptions
7.6.1.10 Comparator Threshold Low MSB (offset = 0x09) [reset = 0x00]
Figure 26. Comparator Threshold Low MSB Register Table 11. Comparator Threshold Low MSB Field Descriptions address 0x08 first and then 0x09.
7.6.1.11 INTB Pin Configuration (offset = 0x0A) [reset = 0x00]
Figure 27. INTB Pin Configuration Register Table 12. INTB Pin Configuration Field Descriptions
22 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
7.6.1.12 Power Configuration (offset = 0x0B) [reset = 0x00]
Figure 28. Power Configuration Register Table 13. Power Configuration Field Descriptions
0 PWR_MODE R/W 0x00 0: Stand-by mode
7.6.1.13 Status (offset = 0x20) [reset = NA]
Figure 29. Status Register Table 14. Status Field Descriptions
7 OSC status R NA 1: Indicates that the oscillator is overloaded and has stopped
6 Data Ready R NA 0: Data is ready to be read
4 Comparator R NA 0: Proximity data is more than the threshold high value
7.6.1.14 Proximity Data LSB (offset = 0x21) [reset = NA]
Figure 30. Proximity Data LSB Register Table 15. Proximity Data LSB Field Descriptions
7.6.1.15 Proximity Data MSB (offset = 0x22) [reset = NA]
Figure 31. Proximity Data MSB Register Table 16. Proximity Data MSB Field Descriptions
7.6.1.16 Frequency Counter LSB (offset = 0x23) [reset = NA]
Figure 32. Frequency Counter LSB Register Table 17. Frequency Counter LSB Field Descriptions
7.6.1.17 Frequency Counter Mid-Byte (offset = 0x24) [reset = NA]
Figure 33. Frequency Counter Mid-Byte Register Table 18. Frequency Counter Mid-Byte Field Descriptions
24 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
7.6.1.18 Frequency Counter MSB (offset = 0x25) [reset = NA]
Figure 34. Frequency Counter MSB Register Table 19. Frequency Counter MSB Field Descriptions(1) (1) Care must be taken to ensure that the proximity data[15:0] and Frequency Counter[23:0] registers are all from same conversion. conversions, these registers are not updated until another read is initiated on 0x21.
SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 www.ti.com
8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Calculation of Rp_Min and Rp_Max
Different sensing applications may have a different ranges of the resonance impedance RP to measure. The LDC1000-Q1 measurement range of RP is controlled by setting two registers: Rp_MIN and Rp_MAX. For a given application, RP must never be outside the range set by these register values, otherwise the measured value will be clipped. For optimal sensor resolution, the range of Rp_MIN to Rp_MAX should not be unnecessarily large. The following procedure is recommended to determine the Rp_MIN and Rp_MAX register values.
8.1.1.1 Rp_MAX
Rp_MAX sets the upper limit of the LDC1000-Q1 resonant impedance input range.
- Configure the sensor such that the eddy-current losses are minimized. As an example, for a proximity sensing application, set the distance between the sensor and the target to the maximum sensing distance.
- Measure the resonant impedance RP using an impedance analyzer.
- Multiply RP by 2 and use the next higher value from the register settings listed in Table 3. For example, if RP is measured at 18 kΩ, 18000 × 2 = 36000. Referring to Table 3, 38.785 kΩ is the smallest value larger than 36 kΩ; therefore Rp_MAX should be set to 0x11. Setting Rp_MAX to a value not listed in Table 3 can result in indeterminate behavior.
8.1.1.2 Rp_MIN
Rp_MIN sets the lower limit of the LDC1000-Q1 resonant impedance input range.
- Configure the sensor such that the eddy current losses are maximized. As an example, for a proximity sensing application, set the distance between the sensor and the metal target to the minimum sensing distance.
- Measure the resonant impedance RP using an impedance analyzer.
- Divide the RP value by 2 and then select the next lower RP value from the register settings listed in Table 4. For example, if RP at 1 mm is measured to be 5 kΩ, 5000 / 2 = 2500. Referring to Table 4, 2.394 kΩ is the smallest value smaller than 2.5 kΩ which corresponds to an Rp_MIN value of 0x3B. Setting Rp_MIN to a value not listed on Table 4 can result in indeterminate behavior. In addition, Rp_MIN powers on with a default value of 0x14 which must be set to a value from Table 4 prior to powering on the LDC.
8.1.2 Output Data Rate
The output data rate of the LDC1000-Q1 device depends on the sensor frequency, fsensor and the Response Time[2-0] field in the LDC configuration register (address: 0x04). Output data rate = fsensor / (Response Time[2-0] / 3) in SPS (samples per second) (14)
8.1.2.1 Example
If the following values are selected, fsensor= 5 Mhz and Response Time[2-0] = 192, then: Output data rate = 5 MHz / (192 / 3) = 78.125 KSPS (15)
26 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: LDC1000-Q1
www.ti.com SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 Application Information (continued)
8.1.3 Selecting a Filter Capacitor (CFA and CFB Pins)
The filter capacitor is critical to the operation of the LDC1000-Q1 device. The capacitor should be low leakage, temperature stable, and it must not generate any piezoelectric noise (the dielectrics of many capacitors exhibit piezoelectric characteristics and any such noise is coupled directly through RP into the converter). The optimal capacitance values range from 20 pF to 100 nF. The value of the capacitor is based on the time constant and resonating frequency of the LC tank. If a ceramic capacitor is used, then a C0G (or NP0) grade dielectric is recommended. The voltage rating should be 10 V or higher. The traces connecting the CFA and CFB pins to the capacitor should be as short as possible to minimize any parasitics. For optimal performance, the selected filter capacitor, connected between the CFA and CFB pins, must be as small as possible but large enough such that the active filter does not saturate. The size of this capacitor depends on the time constant of the sense coil, which is given by L / rs (L = inductance, rs = series resistance of the inductor at oscillation frequency). The larger this time constant, the larger filter capacitor is required. Therefore the time constant reaches the maximum when there is no target present in front of the sensing coil. Use the following procedure to find the optimal filter capacitance: 1. Use with a large filter capacitor. For a ferrite core coil, a value of 10 nF is generally large enough. For an air coil or PCB coil, a value of 100 pF is generally large enough. 2. Power on the LDC and set the desired register values. 3. Minimize the eddy currents losses by ensuring maximum clearance between the target and the sensing coil. 4. Observe the signal on the CFB pin using a scope. Because this node is very sensitive to capacitive loading, the use of an active probe is recommended. As an alternative, a passive probe with a 1-kΩ series resistance between the tip and the CFB pin can be used. 5. Vary the values of the filter capacitor until the signal observed on the CFB pin has an amplitude of approximately 1 VPP. This signal scales linearly with the reciprocal of the filter capacitance. For example, if a 100-pF filter capacitor is applied and the signal observed on the CFB pin has a peak-to-peak value of 200 mV, the desired 1-VPP value is obtained using a filter capacitor value that is calculated with Equation 16. 200 mV / 1 V × 100 pF = 20 pF (16) Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LDC1000-Q1
8.2 Typical Application
Figure 35. Typical Application Schematic Figure 36. Linear Position Sensing
28 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Figure 37. Angular Position Sensing
8.2.1 Design Requirements
For this design example, use the following as the input parameters. Table 20. Design Parameters
8.2.2 Detailed Design Procedure
8.2.2.1 Sensor and Target
In this example, consider a sensor with the characteristics listed in Table 21. Table 21. Sensor Characteristics
The target material used is stainless steel.
8.2.2.2 Calculating a Sensor Capacitor
sensor frequency in order to achieve an output data rate of 78 KSPS per the design parameter. using Equation 17 is 4.99 MHz. Use Equation 18 to calculate the sensor capacitor as 55 pF with a sensor inductance of 18 µH.
8.2.2.3 Selecting a Filter Capacitor
Use the steps listed in the Selecting a Filter Capacitor (CFA and CFB Pins) section to calculate a filter capacitor. Figure 38. Waveform on CFB With 100 pF Figure 39. Waveform on CFB With 20 pF
8.2.2.4 Setting Rp_MIN and Rp_MAX
- Then 27.704 kΩ is the nearest value larger than 25 kΩ. Referring to Table 3, this value corresponds to a
To calculate the value for the Rp_MAX register, use the following value: Rp at 1 mm is 5 kΩ, 5000 / 2 = 2500.
8.2.2.5 Calculating Minimum Sensor Frequency
Use Equation 19 to calculate the minimum sensor frequency.
- N is 227.51 (19)
30 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
which is used to wake up the internal circuit when the sensor is saturated.
8.2.3 Application Curves
Figure 41. Inductance vs DistanceFigure 40. RP vs Distance
SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 www.ti.com
9 Power Supply Recommendations
The LDC1000-Q1 device is designed to operate from an analog supply range of 4.75 to 5.25 V and digital I/O supply range of 1.8 to 5.25 V. The analog supply voltage should be greater than or equal to the digital supply voltage for proper operation of the device. The supply voltage should be well regulated. If the supply is located more than a few inches from the LDC1000-Q1 device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
Use the following guidelines:
- Bypass the VDD and VIO pin to ground with a low ESR ceramic bypass capacitor. A ceramic X7R dielectric capacitor with a value of 0.1 µF is recommend.
- Place the VDD, VIO, GND, and DGND pins as close to the device as possible. Take care to minimize the loop area formed by the bypass capacitor connection and the VDD, VIO, GND, and DGND pins of the IC. See Figure 42 for a PCB layout example.
- Bypass the CLDO pin to the digital ground (DGND) with a ceramic bypass capacitor with a value of 56 nF.
- Connect the filter capacitor that is selected using the procedure listed in the Selecting a Filter Capacitor (CFA and CFB Pins) section between the CFA and CFB pins. Place the capacitor close to the CFA and CFB pins. Do not use any ground or power planes below the capacitor and the trace connecting the capacitor and the CFx pins.
- Use two separate ground planes for the ground (GND) and digital ground (DGND) for a star connection as recommended. See Figure 42 for a PCB layout example.
32 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: LDC1000-Q1
10.2 Layout Example
Figure 42. LDC10xx Board Layout
SLOS886B –SEPTEMBER 2014–REVISED OCTOBER 2014 www.ti.com
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: LDC1000-Q1
www.ti.com 8-Oct-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LDC1000EPWRQ1 ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 150 LDC1000E LDC1000QPWRQ1 ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LDC1000Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 8-Oct-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LDC1000-Q1 :
- Catalog: LDC1000 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2016 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LDC1000EPWRQ1 TSSOP PW 16 2500 367.0 367.0 35.0 LDC1000QPWRQ1 TSSOP PW 16 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2016 Pack Materials-Page 2
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated