ld56050 STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 21

Technical content

Datasheet sections

  • 1 Diagram
  • 2 Pin configuration
  • 3 Typical application
  • 4 Maximum ratings
  • 5 Electrical characteristics
  • 6 Application information
  • 6.1 VBIAS pin voltage requirements
  • 6.2 Output discharge function
  • 6.3 Short circuit and current limitation
  • 6.4 Thermal protection
  • 6.5 Input and output capacitors
  • 7 Typical characteristics
  • 8 Package information
  • 9 Ordering information

Features

  • Input voltage from 0.8 to 5.5 V
  • Bias supply pin
  • Ultra low-dropout voltage (80 mV typ. at 500 mA load)
  • Low ground current (27 μA typ. at no-load)
  • Output voltage tolerance: ± 1.5% overtemperature, 0.5% at 25 °C
  • 500 mA guaranteed output current
  • 50 mV output voltage step available from 0.8 V to 3.6 V
  • Logic-controlled electronic shutdown
  • Internal current limit with foldback
  • Thermal shutdown
  • Output active discharge function
  • Available in DFN4 1.2 x 1.2 mm package
  • Temperature range: -40 °C to 85 °C

Applications

  • Mobile phones
  • Tablets
  • Battery-powered systems
  • Camera supply

Description

The LD56050 is a high accuracy voltage regulator, which provides 0.5 A of current. It is equipped with an NMOS pass transistor, whose gate is biased by a dedicated pin, thus allowing an ultra low-drop performance even at very low input voltages. It is available in DFN4 1.2 x 1.2 package, allowing the maximum space saving. The device is stabilized with a small ceramic capacitor on the output. The ultra low- drop, low quiescent current and short circuit current foldback make the LD56050 suitable for low power battery-operated applications. An enable logic control function puts the LD56050 in shutdown mode allowing a total current consumption lower than 0.1 µA. Thermal protection is also included. Maturity status link LD56050 500 mA ultra-low dropout linear regulator with bias supply LD56050 Datasheet DS12441 - Rev 2 - April 2018 For further information contact your local STMicroelectronics sales office.

1 Diagram

Figure 2. Block diagram Note: (*) Output discharge MOSFET.

2 Pin configuration

Figure 3. Pin connection (top view) Table 1. Pin description

1 VOUT Output voltage

2 VBIAS Bias supply input

3 EN Enable pin logic input: low = shutdown, high = active. Not internally pulled-up. Don't leave floating.

4 VIN Input voltage (power element)

5 GND Common ground

3 Typical application

Figure 4. Typical application circuit Table 2. Typical bill of material

4 Maximum ratings

Table 3. Absolute maximum ratings operation under these conditions is not implied. All values are referred to GND. Table 4. Thermal data Table 5. ESD performance

5 Electrical characteristics

VBIAS = 2.7 V or VOUT + 1.6 V (whichever is greater); VIN = VOUT(NOM) + 0.3 V; IOUT = 1 mA; CIN = 1 µF, COUT = 2.2 µF; VEN = 1 V; typical values are at TJ = 25 °C; min./max. values are at -40 °C ≤ TJ ≤ 85 °C, unless otherwise specified. Table 6. Electrical characteristics

Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit RON Output voltage discharge MOSFET 110 Ω VEN Enable input logic low 0.4 V Enable input logic high 0.9 IEN Enable pin input current VEN = 5.5 V 400 nA TON (2) Turn on time VOUT(NOM) = 1.0 V 110 µs TSHDN Thermal shutdown 160 Hysteresis 20 COUT Output capacitor 1 2.2 22 µF 1. Not applicable for V OUT(NOM) ≥ 5.0 V. 2. Turn-on time is time measured between the enable input just exceeding V EN high value and the output voltage just reaching 98% of its nominal value. Note: Values over the temperature range are guaranteed by design and correlation and not tested in production. LD56050

6 Application information

6.1 VBIAS pin voltage requirements

The bias input is the supply of the internal driving and control circuitry. In order to ensure proper biasing of the N- channel power element, the bias pin must have a minimum voltage of 2.4 V and 1.6 V (typically) higher than the output. If VIN supply voltage meets these requirements then the bias pin can be tied to VIN.

6.2 Output discharge function

The LD56050 integrates a MOSFET connected between VOUT and GND. This transistor is activated when the EN pin goes to low logic level and has the function to quickly discharge the output capacitor when the device is disabled by the user.

6.3 Short circuit and current limitation

The LD56050 is protected against short-circuit on the output. The load current is limited to the maximum value of ILIM when VOUT is equal to 90% of its nominal value. If the VOUT decreases even more due to a lower output load resistance then the foldback circuit starts operating limiting the current to ISC when VOUT = 0.

6.4 Thermal protection

Thermal protection acts when the junction temperature reaches 160 °C typical. At this point the output of the IC shuts down. As soon as the junction temperature falls below the thermal hysteresis value the device starts working again. In order to calculate the maximum power that the device can dissipate, keeping the junction temperature below the maximum operating value, the following formula is used: PDMAX = (85 - TAMB) / RthJA

6.5 Input and output capacitors

The LD56050 requires external capacitors to assure the regulator control loop stability. Any good quality ceramic capacitor can be used but, the X5R and the X7R are suggested since they guarantee a very stable combination of capacitance and ESR across the temperature range. Locating the input/output capacitors as close as possible to the relative pins is recommended. The LD56050 requires a VIN capacitor with a minimum value of 1 μF and a VBIAS capacitor of 100 nF minimum. These capacitors must be located as close as possible to the input pins of the device and returned to a clean analog ground. The control loop is designed to be stable with any good quality output ceramic capacitor (such as X5R/X7R types) with a minimum value of 1.0 μF and equivalent series resistance in the [3 – 300 mΩ] range. It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the full operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR variations must be taken into account in the design phase to ensure the device works in the expected stability region. LD56050

Application information

7 Typical characteristics

Figure 5. VDROP vs. temperature (VBIAS = 2.7 V) Figure 6. VDROP-BIAS vs. temperature (IOUT = 500 mA; Figure 7. VDROP vs. IOUT (VBIAS = 2.7 V) Figure 8. VDROP vs. IOUT (VBIAS = VIN) Figure 9. ISC vs. temperature (VIN = 1.4 V; VBIAS = 2.7 V) Figure 10. ILIM vs. temperature (VIN = 1.4 V; VBIAS = 2.7 V)

Figure 17. Turn-on time (IOUT = 1 mA; VBIAS = 2.7 V) Figure 18. Turn-on time at full load (IOUT = 500 mA; Figure 19. Line transient (VBIAS = 2.7 V, VIN from 1.35 V to

2.35 V; tR = 5 µs)

Figure 20. Load transient (VBIAS = 2.7 V, VIN = 1.35 V; IOUT

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LD56050

Package information

DS12441 - Rev 2 page 12/21

Figure 21. DFN4 1.2 x 1.2 package outline

Table 7. DFN4 1.2 x 1.2 mechanical data Figure 22. DFN4 1.2 x 1.2 recommended footprint Note: All dimensions are in millimeters.

Figure 23. DFN4 1.2 x 1.2 tape and reel t o c e n t r e l i n e o f p o c k e t . h o l e t o c e n t r e l i n e o f p o c k e t . ( I V ) O t h e r m a t e r i a l a v a i l a b l e . Note: Pin 1 orientation: bottom-left.

9 Ordering information

Table 8. Order code

Ordering information

DS12441 - Rev 2 page 16/21

Revision history

Table 9. Document revision history 02-Feb-2018 1 Initial release. temperature (IOUT = 500 mA; VBIAS = VIN). Added: Figure 16. Output voltage vs. junction temperature .