LD49300XX08 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 20
Technical content
Datasheet sections
- 1 Typical application circuits
- 2 Alternative application ci rcuits
- 3 Pin configuration
- 4 Diagram
- 5 Maximum ratings
- 6 Electrical characteristics
- 7 Typical characteristics
- 8 Application hints
- 8.1 Input supply voltage (V IN)
- 8.2 Bias supply voltage (V BIAS)
- 8.3 External capacitors
- 8.4 Output capacitor
- 8.5 Minimum load current
- 8.6 Power sequencing recommendations
- 8.7 Power dissipation/heatsinking
- 8.8 Heatsinking PPAK package
- 8.9 Adjustable regulator design
- 8.10 Enable
- 9 Package mechanical data
- 10 Revision history
Features
■ Input voltage range: –V I = 1.4 V to 5.5 V –V BIAS = 3 V to 6 V ■ Stable with ceramic capacitor ■ ±1.5 % initial tolerance ■ Maximum dropout voltage (VI - VO) of 400 mV over temperature ■ Adjustable output voltage down to 0.8 V ■ Ultra fast transient response (up to 10 MHz bandwidth) ■ Excellent line and load regulation specifications ■ Logic controlled shutdown option ■ Thermal shutdown and current limit protection ■ Junction temperature range: - 25 °C to 125 °C
Applications
■ Graphics processors ■ PC add-in cards ■ Microprocessor core voltage supply ■ Low voltage digital ICs ■ High efficiency linear power supplies ■ SMPS post regulators
Description
The LD49300xx is a high-bandwidth, low drop- out, 3.0 A voltage regulator, ideal for powering core voltages of low-power microprocessors. The LD49300xx implements a dual supply configuration allowing for very low output impedance and very fast transient response. The LD49300xx requires a bias input supply and a main input supply, allowing for ultra-low input voltages on the main supply rail. The input supply operates from 1.4 V to 5.5 V and the bias supply requires between 3 V and 6 V for proper operation. The LD49300xx offers fixed output voltages from 0.8 V to 1.8 V and adjustable output voltages down to 0.8 V. The LD49300xx requires a minimum output capacitance for stability, and works optimally with small ceramic capacitors. PPAK Table 1. Device summary
1 Typical application circuits
Figure 1. Adjustable version Figure 2. Fixed version with enable
2 Alternative application circuits
Figure 3. Single supply voltage solution Figure 4. LD49300xx plus DC-DC pre-regulator to reduce power dissipation
3 Pin configuration
Figure 5. Pin connections (top view) Table 2. Pin description EN Enable (Input): Logic High = Enable, Logic Low = Shutdown. ADJ Adjustable regulator feedback input. Connect to resistor voltage divider. 2V IN Input voltage which supplies current to the output power device. 3 GND Ground (TAB is connected to ground).
4 Diagram
Figure 6. Block diagram
5 Maximum ratings
Note: 1 Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. 2 All the values are referred to ground. Table 3. Absolute maximum ratings Table 4. Operating ratings
6 Electrical characteristics
Table 5. Electrical characteristics
- For V O ≤ 1 V, VBIAS dropout specification does not apply due to a minimum 3 V VBIAS input.
- Fixed output voltage version only.
7 Typical characteristics
Figure 7. Reference voltage vs. temperature Figure 8. Output voltage vs. temperature Figure 9. Load regulation vs. temperature Fi gure 10. Line regulation vs. temperature Figure 11. Output voltage vs. input voltage Figure 12. Dropout voltage (V IN-VOUT) vs.
8 Application hints
The LD49300xx is an ultra-high performance, low dropout linear regulator, designed for high current application that requires fast transient response. The LD49300xx operates from two input voltages, to reduce dropout voltage. The LD49300xx is designed so that a minimum of external component are necessary.
8.1 Input supply voltage (V IN)
VIN provides the power input current to the LD49300xx. The minimum input voltage can be as low as 1.4 V, allowing conversion from very low voltage supplies to achieve low output voltage levels with very low power dissipation.
8.2 Bias supply voltage (V BIAS)
The LD49300xx control circuitry is supplied the VBIAS pin which requires a very low bias current (3 mA typ.) even at the maximum output current level (3 A). A bypass capacitor on the bias pin is recommended to improve the performance of the LD49300xx during line and load transient. The small ceramic capacitor from V BIAS to ground reduces high frequency noise that could be injected into the control circuitry from the bias rail. In typical applications a 1 µF ceramic chip capacitor may be used. The V BIAS input voltage must be 2.1 V above the output voltage, with a minimum VBIAS input voltage of 3 V.
8.3 External capacitors
To assure regulator stability, input and output capacitors are required as shown in the typical application circuit.
8.4 Output capacitor
The LD49300xx requires a minimum output capacitance to maintain stability. A ceramic chip capacitor of at least 1 µF is required. However, specific capacitor selection could be needed to ensure the transient response. A 1 µF ceramic chip capacitor satisfies most applications but 10 µF is recommended to ensure better transient performances. In applications where the V IN level is close to the maximum operating voltage (VIN > 4 V), it is strongly recommended to use an output capacitors of, at least, 10 µF in order to avoid over-voltage stress on the Input/output power pins during short circuit conditions due to parasitic inductive effect. The output capacitor must be located as close as possible to the output pin of the LD49300xx. The ESR (equivalent series resistance) of the output capacitor must be within the "STABLE" region as shown in the typical characteristics figures. Both ceramic and tantalum capacitors are suitable.
8.5 Minimum load current
The LD49300xx does not require a minimum load to maintain output voltage regulation.
8.6 Power sequencing recommendations
In order to ensure the correct biasing and settling of the regulator internal circuitry during the startup phase, as well as to avoid overvoltage spikes at the output, it is recommended to provide for the correct power sequencing. As a general rule the V IN and VINH signals timings at startup should be chosen properly, so that they are applied to the device after the VBIAS voltage is already settled at its minimum operative value (see paragraph 8.2: Bias supply voltage (VBIAS)). This can be achieved, for instance, by avoiding too slow VBIAS rising edges (Tr > 10 ms). Provided that the above condition is satisfied, when fast VIN transient input (Tr < 100 µs) is present, a smooth startup, with limited overvoltage on the output, can be obtained by applying V IN voltage at the same time as the VBIAS voltage (refer to Figure 20, Figure 21 and Figure 22 on page 11). In the fixed voltage versions it is possible to reduce overvoltage spikes during very fast startup (Tr << 100 µs) by pulling the VINH pin up to VIN voltage (see Figure 23 on page 12).
8.7 Power dissipation/heatsinking
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: P D = VIN x IIN + VBIAS x IBIAS - VOUT x IOUT Where:
- VIN, Input supply voltage
- VBIAS, Bias supply voltage
- VOUT, Output voltage
- IOUT, Load current From this data, we can calculate the thermal resistance (θSA) required for the heat sink using the following formula: θSA = (TJ - TA/PD) - (θJC + θCS) The maximum allowed temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax - TAmax The maximum allowable value for junction to ambient thermal resistance, θJA, can be calculated using the formula: θJAmax = TRmax / PD This part is available for the PPAK package. The thermal resistance depends on the amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥100 °C/W for the PPAK package, no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required as described below.
8.8 Heatsinking PPAK package
situated with a dissipating area thermally connected through vias holes, filled by solder. a typical PCB with 1/16 in thick G10/FR4.
8.9 Adjustable regulator design
Where VOUT is the desired output voltage. performances. Even, higher values up to 100 kΩ are suitable.
8.10 Enable
not be left at high impedance. Figure 25. θJA vs. Copper Area for PPAK package
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Dim. mm. inch. A 2.2 2.4 0.0 86 0.0 94 A1 0. 9 1.1 0.0 35 0.04 3 A2 0.0 3 0.23 0.001 0.00 9 B 0.4 0.6 0.015 0.02 3 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.02 3 C2 0.4 8 0.6 0.01 9 0.023 D 6 6.2 0.2 36 0.244 D1 5.1 0.201 E 6.4 6.6 0.252 0.260 E1 4.7 0.1 85 e 1.27 0.050 G4 . 9 5.25 0.1 93 0.206 G1 2. 38 2.7 0.0 93 0.106 H 9.35 10.1 0. 368 0.397 L2 0. 8 1 0.0 31 0.039 L4 0.6 1 0.02 3 0.039 L5 1 0.039 L6 2. 8 0.110 PPAK mechanical data 0078180-E
Dim. mm. inch. A 330 12. 992 D 20.2 0.7 95 N6 0 2 . 362 T2 2 . 4 0 . 882 Tape & reel DPAK-PPAK mechanical data
Table 6. Document revision history 20-Nov-2006 1 Initial release. 01-Dec-2006 2 Add note in cover page. 30-Jun-2010 3 Modified Section 8.6: Power sequencing recommendations on page 14.