LD49150 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 20
Technical content
Datasheet sections
- 1 Typical application circuits
- 2 Alternative application circuits
- 3 Pin configuration
- 4 Diagram
- 5 Maximum ratings
- 6 Electrical characteristics
- 7 Typical characteristics
- 8 Application hints
- 8.1 Input supply voltage (V IN)
- 8.2 Bias supply voltage (V BIAS)
- 8.3 External capacitors
- 8.4 Output capacitor
- 8.5 Minimum load current
- 8.7 Power dissipation/heatsinking
- 8.8 Heatsinking PPAK package
- 8.9 Adjustable regulator design
- 8.10 Enable
- 9 Package mechanical data
- 10 Revision history
April 2007 Rev. 1 1/20 LD49150 1.5A Very low drop for low output voltage regulator Feature summary ■ Input voltage range: VI = 1.4V to 5.5V VBIAS = 3V to 6V ■ Stable with ceramic capacitor ■ ±1.5% initial tolerance ■ Maximum dropout voltage (VI - VO) of 200mV over temperature ■ Adjustable output voltage down to 0.8V ■ Ultra fast transient response (up to 10MHz bandwidth) ■ Excellent line and load regulation specifications ■ Logic controlled shutdown option ■ Thermal shutdown and current limit protection ■ Junction temperature range: –25°C to 125°C
Description
The LD49150 is a high-bandwidth, low-dropout, 1.5A voltage regulator, ideal for powering core voltages of low-power microprocessors. The LD49150 implements a dual supply configuration allowing for very low output impedance and very fast transient response. The LD49150 requires a bias input supply and a main input supply, allowing for ultra-low input voltages on the main supply rail. The input supply operates from 1.4V to 5.5V and the bias supply requires between 3V and 6V for proper operation. The LD49150 offers fixed output voltages from 0.8V to 1.8V and adjustable output voltages down to 0.8V. The LD49150 requires a minimum output capacitance for stability, and work optimally with small ceramic capacitors.
Applications
■ Graphics processors ■ PC Add-In Cards ■ Microprocessor core voltage supply ■ Low voltage digital ICs ■ High Efficiency Linear power supplies ■ SMPS post regulators PPAK Order codes Part number Package Packaging LD49150PT08R (1) 1. Adjustable Version. PP AK (Tape&Reel) 2500 parts per reel LD49150PT10R PP AK (Tape&Reel) 2500 parts per reel LD49150PT12R PP AK (Tape&Reel) 2500 parts per reel
1 Typical application circuits
Figure 1. Adjustable version Figure 2. Fixed version with Enable
2 Alternative application circuits
Figure 3. Single supply voltage solution Figure 4. LD49150 plus DC/DC pre-regulator to reduce power dissipation
3 Pin configuration
Table 1. Pin description Figure 5. Pin connections (top view) 1 EN Enable (Input): Logic High = Enable, Logic Low = Shutdown. ADJ Adjustable regulator feedback input. Connect to resistor voltage divider. 2 VIN Input voltage which supplies current to the output power device. 3 GND Ground (TAB is connected to ground).
5 VBIAS
4 Diagram
Figure 6. Block diagram
5 Maximum ratings
Table 2. Absolute maximum ratings Note: 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional Operation under these conditions is not implied. 2 All the values are referred to ground. Table 3. Operating ratings
6 Electrical characteristics
Table 4. Electrical characteristics CO = 10µF; CBIAS = 1µF; unless otherwise specified. Typical values are referred to TJ = 25°C).
- For V O ≤ 1V, VBIAS dropout specification does not apply due to a minimum 3V V BIAS input.
- Fixed output voltage version only.
7 Typical characteristics
Figure 7. Reference voltage vs temperature Figure 8. Output voltage vs temperature Figure 9. Load regulation vs temperature Figure 10. Line regulation vs temperature Figure 11. Output voltage vs input voltage Figure 12. Dropout voltage (V IN-VOUT) vs
Figure 23. V IN Start Up transient response
8 Application hints
The LD49150 is an ultra-high performance, low dropout linear regulator, designed for high current application that requires fast transient response. The LD49150 operates from two input voltages, to reduce dropout voltage. The LD49150 is designed so that a minimum of external component are necessary.
8.1 Input supply voltage (V IN)
VIN provides the power input current to the LD49150. The minimum input voltage can be as low as 1.4V, allowing conversion from very low voltage supplies to achieve low output voltage levels with very low power dissipation.
8.2 Bias supply voltage (V BIAS)
The LD49150 control circuitry is supplied the VBIAS pin which requires a very low bias current (3mA typ.) even at the maximum output current level (1.5A). A bypass capacitor on the bias pin is recommended to improve the performance of the LD49150 during line and load transient. The small ceramic capacitor from V BIAS to ground reduces high frequency noise that could be injected into the control circuitry from the bias rail. In typical applications a 1µF ceramic chip capacitor may be used. The V BIAS input voltage must be 2.1V above the output voltage, with a minimum VBIAS input voltage of 3V.
8.3 External capacitors
To assure regulator stability, input and output capacitors are required as shown in the typical application circuit.
8.4 Output capacitor
The LD49150 requires a minimum output capacitance to maintain stability. A ceramic chip capacitor of at least 1µF is required. However, specific capacitor selection could be needed to ensure the transient response. A 1µF ceramic chip capacitor satisfies most applications but 10µF is recommended to ensure better transient performances. In applications where the V IN level is close to the maximum operating voltage (VIN>4V), it is strongly recommended to use an output capacitors of, at least, 10µF in order to avoid over-voltage stress on the Input/output power pins during short circuit conditions due to parasitic inductive effect. The output capacitor must be located as close as possible to the output pin of the LD49150. The ESR (equivalent series resistance) of the output capacitor must be within the "STABLE" region as shown in the typical characteristics figures. Both ceramic and tantalum capacitors are suitable.
8.5 Minimum load current
The LD49150 does not require a minimum load to maintain output voltage regulation.
8.6 V IN and VBIAS power sequencing
In common applications where the power on transient of VIN and VBIAS voltages are not particularly fast (Tr>100µs), no power sequencing is required. Where voltage transient input (Tr<100µs) is very fast, it is recommended to have the VIN voltage present before or, at least, at the same time as the VBIAS voltage in order to avoid overvoltage spikes during the power on transient (refer to the figures in the typical characteristics). Where VIN transient input (Tr<<100µs) is very fast for the fixed VOUT versions, it is possible to avoid start-up overvoltage spikes by pulling the VINH pin up to VIN voltage (refer to relative typical characteristics figures at pages 11 and 12).
8.7 Power dissipation/heatsinking
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: P D = VIN x IIN + VBIAS x IBIAS - VOUT x IOUT Where:
- VIN, Input supply voltage
- VBIAS, Bias supply voltage
- VOUT, Output voltage
- IOUT, Load current From this data, we can calculate the thermal resistance (θSA) required for the heat sink using the following formula: θSA = (TJ - TA/PD) - (θJC + θCS) The maximum allowed temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax - TAmax The maximum allowable value for junction to ambient thermal resistance, θJA, can be calculated using the formula: θJAmax = TRmax / PD This part is available for the PPAK package. The thermal resistance depends on the amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥100 °C/W for the PPAK package, no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required as described below.
8.8 Heatsinking PPAK package
with a dissipating area thermally connected through vias holes, filled by solder. typical PCB with 1/16 in thick G10/FR4.
8.9 Adjustable regulator design
Where VOUT is the desired output voltage. It is suggested to use R1 values lower than 10KΩ to obtain better load transient performances. Even, higher values up to 100KΩ are suitable.
8.10 Enable
Figure 24. θJA vs Copper Area for PPAK package
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
DIM. mm. inch A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.4 0.6 0.015 0.023 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 D1 5.1 0.201 E 6.4 6.6 0.252 0.260 E1 4.7 0.185 e 1.27 0.050 G 4.9 5.25 0.193 0.206 G1 2.38 2.7 0.093 0.106 H 9.35 10.1 0.368 0.397 L2 0.8 1 0.031 0.039 L4 0.6 1 0.023 0.039 L5 1 0.039 L6 2.8 0.110 PPAK MECHANICAL DATA 0078180-E
DIM. mm. inch A 330 12.992 D 20.2 0.795 N 60 2.362 T 22.4 0.882 Tape & Reel DPAK-PPAK MECHANICAL DATA
Table 5. Revision history 18-Apr-2007 1 Initial release.