LD39050XX STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Datasheet sections
- 1 Diagrams
- 2 Pin configuration
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Typical performance characteristi cs
- 6 Application information
- 6.1 Power dissipation
- 6.2 Enable function
- 6.3 Power Good function
- 7 Package mechanical data
- 8 Different output voltag e versions of the LD39050xx
- 9 Revision history
Features
■ Input voltage from 1.5 to 5.5 V ■ Ultra low dropout voltage (200 mV typ. at 500 mA load) ■ Very low quiescent current (20 µA typ. at no load, 100 µA typ. at 500 mA load, 1 µA max in off mode) ■ Very low noise without bypass capacitor ■ Output voltage tolerance: ± 2.0 % @ 25 °C ■ 500 mA guaranteed output current ■ Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and ADJ from 0.8 V ■ Logic-controlled electronic shutdown ■ Compatible with ceramic capacitor C OUT = 1 µF ■ Internal current and thermal limit ■ Package DFN6 (3 x 3 mm) ■ Temperature range: -40 °C to 125 °C
Description
The LD39050 provides 500 mA maximum current from an input voltage ranging from 1.5 V to 5.5 V with a typical dropout voltage of 200 mV. Stability is provided using ceramic capacitors. The ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery-powered applications. Power supply rejection is 65 dB at low frequencies and starts to roll off at 10 kHz. An Enable logic control function puts the LD39050 in shut-down mode allowing a total current consumption lower than 1 µA. The device also includes short-circuit constant current limiting and thermal protection. Typical applications are mobile phones, personal digital assistants (PDAs), cordless phones and similar battery-powered systems. DFN6 (3 x 3 mm) Table 1. Device summary
1 Diagrams
Figure 1. Schematic diagram for the LD39050PU Figure 2. Schematic diagram for the LD39050PUxx
2 Pin configuration
Figure 3. Pin connection (top view) Table 2. Pin description
3 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 3. Absolute maximum ratings Table 4. Thermal data Table 5. ESD performance
4 Electrical characteristics
Table 6. Electrical characteristics for the LD39050PU
- All transient values are guarant eed by design, not production tested
- Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
- Turn-on time is time measured bet ween the enable input just exceeding V
Table 6. Electrical characteristics for the LD39050PU (continued)
Table 7. Electrical characteristics for the LD39050PUxx
- All transient values are guarant eed by design, not production tested
- Dropout voltage is the input-to-output voltage difference at whic h the output voltage is 100 mV below its nominal value. This
- Turn-on time is time measured between the enable input just exceeding V
Table 7. Electrical characteristics for the LD39050PUxx (continued)
5 Typical performance characteristics
Figure 4. V ADJ accuracy Figure 5. V OUT accuracy Figure 6. Dropout voltage vs. temperature Figure 7. Dropout voltage vs. temperature Figure 8. Dropout voltage vs. output current Figure 9. Short-circuit current vs. dropout
6 Application information
fixed and adjustable output versions. limiting and thermal protection. The regulator is designed to be stable with ceramic capacitors on the input and the output. upper limit to the value of the input capacitor. Figure 34. Application schematic for fixed version Figure 35. Application schematic for adjustable version
For the adjustable version, the output voltage can be adjusted from 0.8 V up to the input voltage minus the voltage drop across the PMOS (dropout voltage), by connecting a resistor divider between the ADJ pin and the output, thus allowing remote voltage sensing. The resistor divider should be selected using the following equation: V OUT = VADJ (1 + R1 / R2) with VADJ = 0.8 V (typ.) It is recommended to use resistors with values in the range of 10 kΩ to 50 kΩ. Lower values can also be suitable, but will increase current consumption.
6.1 Power dissipation
An internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 160 °C. This feature protects the device from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without risk of damaging the device. It is very important to use a good PC board layout to maximize power dissipation. The thermal path for the heat generated by the device is from the die to the copper lead frame through the package leads and exposed pad to the PC board copper. The PC board copper acts as a heat sink. The footprint copper pads should be as wide as possible to spread and dissipate the heat to the surrounding ambient. Feed-through vias to inner or backside copper layers are also useful in improving the overall thermal performance of the device. The power dissipation of the device depends on the input voltage, output voltage and output current, and is given by: P D = (VIN -VOUT) IOUT The junction temperature of the device is: T J_MAX = TA + RthJA x PD where: T J_MAX is the maximum junction of the die,125 °C; TA is the ambient temperature; RthJA is the thermal resistance junction-to-ambient.
6.2 Enable function
The LD39050 features an enable function. When the EN voltage is higher than 2 V the device is ON, and if it is lower than 0.8 V the device is OFF . In shutdown mode, consumption is lower than 1 µA. The EN pin does not have an internal pull-up, which means that it cannot be left floating if it is not used.
6.3 Power Good function
Most applications require a flag showing that the output voltage is in the correct range. The Power Good threshold depends on the adjust voltage. When the adjust is higher than 0.92*VADJ, the Power Good (PG) pin goes to high impedance. If the adjust is below
LD39050xx Application information 0.80*VADJ the PG pin goes to low impedance. If the device is functioning well, the Power Good pin is at high impedance. If the output voltage is fixed using an external or internal resistor divider, the Power Good threshold is 0.92*V OUT. The use of the Power Good function requires an external pull-up resistor, which must be connected between the PG pin and VIN or VOUT. The typical current capability of the PG pin is up to 6 mA. The use of a pull-up resistor for PG in the range of 100 kΩ to 1 MΩ is recommended. If the Power Good function is not used, the PG pin must remain floating.
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
LD39050xx Package mechanical data Dim. mm. inch. A1 0 0.02 0.05 0 0.001 0.002 A3 0.20 0.00 8 e0 . 950 . 0 37 DFN6 (3x3 mm) mechanical data 7946637A
Dim. mm. inch. A 330 12. 992 C 12. 8 13.2 0.504 0.51 9 D 20.2 0.7 95 N6 0 2 . 362 T1 8.4 0.724 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.04 3 Po 4 0.157 P 8 0.315 Tape & reel QFNxx/DFNxx (3x3) mechanical data
Figure 36. DFN6 (3x3) footprint recommended data
8 Different output voltage versions of the LD39050xx
Table 8. Options available on request
9 Revision history
Table 9. Document revision history 11-Mar-2009 1 Initial release.